WO2017167792A1

WO2017167792A1 - Method for producing a plurality of semiconductor chips, such a semiconductor chip, and module comprising such a semiconductor chip

Info

Publication number: WO2017167792A1
Application number: PCT/EP2017/057378
Authority: WO
Inventors: Daniel Richter; Konrad Wagner
Original assignee: Osram Opto Semiconductors Gmbh
Priority date: 2016-03-31
Filing date: 2017-03-29
Publication date: 2017-10-05
Also published as: DE102016205308A1

Abstract

The invention relates to a method for producing a plurality of semiconductor chips (10), to such a semiconductor chip (10), and to a module (100) comprising such a semiconductor chip. The method has the following steps: - providing an assembly (12) comprising a support (1) and a semiconductor body (2), - forming a plurality of recesses (4) in the assembly (12), wherein a part of the support (1) is removed in the region of the recesses (4), - at least partly filling the recesses (4) with an electrically conductive contact material (6), and - separating the assembly (12) along a plurality of separation lines (11) in order to form the plurality of semiconductor chips (10), said separation be carried out in some areas using the electrically conductive contact material (6).

Description

METHOD FOR PRODUCING A VARIETY OF SEMICONDUCTOR CHIPS, SUCH A SEMICONDUCTOR CHIP AND MODULE WITH SUCH A SEMICONDUCTOR CHIP

The publication US 2005/0087884 AI describes a flip-chip LED chip.

This patent application claims the priority of German Patent Application 10 2016 205 308.6, the disclosure of which is hereby incorporated by reference.

One problem to be solved is a method

specify, can be produced particularly cost-effective with the particularly small semiconductor chips. Another problem to be solved is to be particularly compact

Specify semiconductor chips that are particularly stable at

Destination can be mounted and are characterized by a particularly good heat dissipation during operation. Another object to be solved is to provide a module with a plurality of semiconductor chips, which is particularly compact.

A method for producing a multiplicity of semiconductor chips is specified. The semiconductor chips are in particular optoelectronic semiconductor chips. The semiconductor chips can be used in operation for example for

Detection or to be provided for the emission of electromagnetic radiation. In particular, it may be at the

Semiconductor chips act around light-emitting diode chips that emit during operation electromagnetic radiation from the spectral range of UV radiation to infrared radiation, in particular visible light. In accordance with at least one embodiment, the method comprises a step in which an arrangement comprising a carrier and a semiconductor body is provided. The arrangement may be, for example, a wafer in which the semiconductor body is epitaxially deposited on the carrier. The carrier is then

for example, a substrate wafer which may be formed with materials such as silicon, SiC or sapphire or consists of at least one of these materials. In particular, it is possible that the carrier is a sapphire growth substrate on which the semiconductor layers of the semiconductor body are epitaxially deposited.

Alternatively, it is possible that the arrangement is formed by connecting the semiconductor body to the carrier.

For example, such a connection can be produced by soldering or "direct bonding." In this case, the support is not the growth substrate used to make the semiconductor body, for example, with materials such as silicon, SiC, sapphire , Glass, ceramics or consist of one of these materials.

The carrier and the semiconductor body are preferably arranged one above the other in a type of layer structure, the semiconductor body in particular in the direction of a

Surface normal of the carrier can be arranged above the carrier. In this case, the support may in particular be a substrate or an auxiliary substrate, to which the

Semiconductor body was grown or transferred. The

Arrangement consisting of carrier and semiconductor body can then for producing a module, for example on a

Connection material arranged or connected. In accordance with at least one embodiment, the method comprises a step in which a multiplicity of recesses are formed in the arrangement, wherein a portion of the carrier is removed in the region of a recess.

From a main surface of the arrangement, a material removal takes place to form the recesses, in which material of the carrier is removed for each recess. The

Recesses can be made by chemical methods such as

Etching, mechanical processes such as drilling or physical processes such as evaporation, for example by means of

Laser radiation, or be generated by combinations of such methods.

As part of the manufacturing tolerance a plurality of similar recesses is produced in the arrangement, which have the same geometric dimensions within the manufacturing tolerance. The recesses are, for example, on a major surface of the arrangement at the grid points of

arranged in a regular grid. For the recesses, it is especially possible that they are not the arrangement

completely penetrate. That is, the recesses

then extend into the arrangement up to a predetermined penetration depth.

Further, it is possible for the recesses to be formed as trenches extending along a major part or the entire major surface of the assembly from which they originate

are formed, for example, along straight lines, extend. These recesses may for example be arranged at regular intervals from each other. In accordance with at least one embodiment of the method, the method comprises a step in which at least partial filling of the recesses takes place with an electrically conductive contact material. That is, a majority, for example, at least 50% of the plurality of recesses, is at least partially associated with the electrically conductive

Contact material filled. In particular, it is possible that all of the plurality of recesses are at least partially filled with the contact material.

The recesses are at least partially with the

filled electrically conductive contact material, that is, the contact material may fill the recesses completely or in part. It is possible, for example, that the recesses next to the electrically conductive

Contact material with another material, for example, an electrically insulating passivation material, filled so that the recesses are filled with the passivation material and the electrically conductive contact material. The electrically conductive contact material is in particular a material comprising at least one metal, several metals or a metal alloy. The electrically conductive contact material can, for example, with application methods such as sputtering, chemical

Vapor deposition or vapor deposition, electroless, galvanic or melt introduced into the recesses in the assembly.

According to at least one embodiment of the method, the method comprises a step in which separating the

Arrangement along a plurality of dividing lines in the

Variety of semiconductor chips takes place. The dividing lines

Run along, for example, along the main surfaces of the Arrangement. The separation then occurs, for example, in a direction perpendicular to the major surfaces through the array. By separating the arrangement can

For example, cylindrical or cuboid

Semiconductor chips are generated, each comprising a part of the carrier and a part of the semiconductor body.

According to at least one embodiment of the method, the separation takes place in places by the electrically conductive

Contact material. That is, in the separation of the arrangement into individual semiconductor chips and the contact material is cut, so that a part of the contact material of a

Recess is present in a semiconductor chip and another part of the contact material of a recess in another, adjacent semiconductor chip is present.

In the event that the recesses are formed as trenches, for example, along the entire

Main surface of the arrangement, from which they are introduced into the arrangement, extend, it is possible that the

Dividing lines run along the recesses. In the event that the recesses at the grid points of a regular grid, for example in the form of holes with

square or round cross-section, are placed in the arrangement, it is possible that each dividing line passes through a plurality of recesses.

In accordance with at least one embodiment of the method for producing a multiplicity of semiconductor chips, the method comprises the following steps:

Providing an arrangement comprising a carrier and a semiconductor body, Forming a plurality of recesses in the assembly, wherein a portion of the carrier is removed in the region of the recesses,

- At least partially filling the recesses with an electrically conductive contact material, and

- Separating the assembly along a variety of

Dividing lines in the plurality of semiconductor chips, wherein

- The separation takes place in places by the electrically conductive contact material.

In accordance with at least one embodiment of the method, at least one, in particular each, of the plurality of

Semiconductor chips, a first contact point and a second contact point generated, each comprising the electrically conductive contact material. That is, the electrically conductive contact material in the recesses forms in the finished

Semiconductor chip in each case a contact point of the semiconductor chip. For this purpose, further electrically insulating or electrically conductive material can be applied to the contact material or the contact material forms after the separation of the

Arrangement in the semiconductor chips on its side facing away from the semiconductor chip outer surface each have a contact point. During the operation of the semiconductor chip, the current required for the operation of the semiconductor chip is injected into the contact point via the contact points

Semiconductor chip impressed.

In accordance with at least one embodiment of the method, each of the contact points locally forms a side surface of the semiconductor chip, and each of the contact points extends in places on a bottom surface of the semiconductor chip. When separating the assembly along the plurality of

Dividing lines in the plurality of semiconductor chips are separated by the contact material. This creates Side surfaces of the generated semiconductor chip, which are formed at least in places by the contact material. The exposed on the side surfaces contact material then forms a contact point, so that a side surface of the

Semiconductor chips in places formed by the contact point. The side surfaces are those surfaces that the bottom surface and a top surface of the semiconductor chip

connect with each other. For example, the bottom surface and the top surface are transverse or perpendicular to one another

Growth direction with the epitaxial layers of the

Grown semiconductor chips. The side surface could then be parallel or substantially parallel to, for example

Growth direction. If the recesses are formed, for example, as trenches in the arrangement, it is possible that a

Side surface of the semiconductor chip along its entire length is formed by the contact point, wherein, depending on

Penetration depth of the recess in the arrangement of a lower, a bottom surface of the semiconductor chip facing part of the side surface through the contact point and a

subsequent upper part of the side surface is or is formed by material of the carrier and / or the semiconductor body. For example, the part of the contact material which is exposed at the opening of the recess forms in

finished semiconductor chip then the part of

Pad, which extends in places on the bottom surface of the semiconductor chip. Overall, each contact point then extends in places on a side surface of the semiconductor chip and on the

Floor surface of the semiconductor chip. One and the same

Contact point can in this way be part of at least one Side surface and part of the bottom surface of the

Form semiconductor chips. Furthermore, it is possible that one and the same contact point in each case a part of two or three side surfaces and a part of the bottom surface of

Semiconductor chips forms.

In accordance with at least one embodiment of the method, the recesses are produced when the plurality of recesses are formed from the side of the semiconductor body facing away from the carrier. In this embodiment, the recesses then extend in a direction perpendicular to the

Main surfaces of the assembly completely through the

Semiconductor body and penetrate from there into the material of the carrier.

Such an embodiment has the advantage that a

Contacting of the semiconductor chip via the contact points is made possible in a simplified manner since plated-through holes for contacting, for example, an active layer of the semiconductor body do not have to extend through the carrier, but only through the semiconductor body, which is generally much thinner. In this embodiment, however, a portion of the semiconductor body is removed by the recesses, which is, for example, consuming

manufactured semiconductor layers can act. Further, in this embodiment, the active area of the

Semiconductor body reduced by the material removal due to the recesses. Especially at

This can lead to a reduced light-generating area radiation-emitting semiconductor chips.

In accordance with at least one embodiment of the method, the recesses are formed when the plurality of recesses are formed generated from the semiconductor body side facing away from the carrier forth and the recesses extend into the

Carrier without completely penetrating the carrier. This embodiment has the advantage that the recesses do not extend into the semiconductor body

extend and in this way no expensive epitaxial material is removed and the active area of the

Semiconductor body is not reduced by the recesses. On the other hand, the plated-through holes for contacting, for example, an active layer of the

Semiconductor body extend completely through the carrier, which can complicate the production of the vias, as an adjustment effort is greater than for

Through holes, which are formed only in the semiconductor body.

In accordance with at least one embodiment of the method, a multiplicity of plated-through holes are produced, which extend in places through the semiconductor body, and the plated-through holes are electrically conductively connected to the electrically conductive contact material. The

Through-holes serve, for example, for contacting doped layers of the semiconductor body. About the

Through-contacts can then be operated, for example, an active layer arranged between the doped layers of the semiconductor body. The vias make it possible to contact the semiconductor chip from a single side, for example, from its bottom surface. It is possible that the plated-through holes extend only in the semiconductor body. In this case, the recesses are produced on the side of the assembly which faces away from the carrier. Furthermore, it is possible that the Vias extend completely through the carrier. In this case, the recesses are produced on the side of the carrier facing away from the semiconductor body and do not extend into the semiconductor body.

Furthermore, a semiconductor chip is specified. Of the

Semiconductor chip can be produced by a method described here. That is, all features disclosed for the method are also for the semiconductor chip

revealed and vice versa. In particular, the im

Described in connection with the method also described for the semiconductor chip and vice versa. In accordance with at least one embodiment of the semiconductor chip, the semiconductor chip comprises a carrier and a semiconductor body, a first contact point and a second contact point, which are used for electrical contacting of the semiconductor chip

are formed, wherein the first contact point and the second contact point comprise an electrically conductive contact material, each contact point locally forms a side surface of the semiconductor chip and each contact point in places on a bottom surface of the semiconductor chip

extends.

The semiconductor chip is based inter alia on the following considerations. It is possible to form radiation-emitting semiconductor chips in a so-called flip-chip design, in which the semiconductor chips can be contacted from a single side of the semiconductor chip. The

electrical contacts of the semiconductor chip are then

either on the side of the semiconductor body or on the

Side of the carrier. In the first case, the light extraction for radiation-emitting semiconductor chips takes place through the carrier, for which purpose it must be transparent. in the second case, the emission of electromagnetic radiation takes place directly at the top of the semiconductor chip and the electromagnetic radiation does not need the carrier

run through. Both approaches have the advantage that the electrical connection points of the semiconductor chip, so for example anode and cathode, on a single

common side of the semiconductor chip are accessible. In this way, the chip can be particularly easily mounted at the destination, without further wiring technologies such as wire bonding or metallized tracks are necessary.

In such semiconductor chips, which are contacted from a single side, however, there is the problem that for the cooling of the semiconductor chip in operation and to a

sufficiently large adhesion of the semiconductor chip on

Ensure destination, the contact points on the mounting side of the semiconductor chip must have the largest possible area. On the other hand, the distance between the contact points can not be reduced arbitrarily, since otherwise threatening short circuits or mounting on standardized circuit boards is not possible. It is therefore not possible to provide single-sided contacted semiconductor chips having side surfaces of a lateral extent of less than 300 ym.

The semiconductor chips described here and the here

described method is now based on the idea that a part of the contact surface on the flanks, so the

Side surfaces, the semiconductor chip can be formed. In this way, the contact area of the semiconductor chip can be increased without the distance between the

Contact points on the bottom surface of the semiconductor chip must be reduced. That is, the distance between the pads on the bottom surface of the semiconductor chip can be maximized or semiconductor chips with a smaller chip pitch can be realized, so here described

Semiconductor chips edge lengths of less than 300 ym,

in particular, can have edge lengths of less than 250 ym.

Due to the fact that the contact points locally form a side surface of the semiconductor chip and not only extend to the bottom surface of the semiconductor chip, the contact points have an enlarged

Contact surface, which improves the heat dissipation of the chip and increases the area at which a contact material can wet the contact points increases.

According to at least one embodiment of the semiconductor chip, the first contact point and the second contact point on its outer surface facing away from the carrier in the region of the side surface of the semiconductor chip, which form the contact points in places, traces of a separation process. The contact points, as described in connection with the method, for example, be generated by the separation by the electrically conductive material in the recesses. By this separation, which can be done for example via sawing, cutting or laser cutting, are at the contact points in the area of the side surfaces of

Semiconductor chips, where the contact points through the

Separation process are generated, characteristic traces of

Separation process generated. These tracks may be, for example, grooves, roughening or the like. Advantageously, the traces of the separation process may increase the area of the pads on the side surfaces of the chip at least at the microscopic level, for example, improving the adhesion of a lead material, such as a solder or an electrically conductive adhesive, to the pads in that region. This may, for example, to an improved wetting of the

Contact points in the region of the side surfaces of the chip come, what the adhesive force between the semiconductor chip and the

Destination increased.

According to at least one embodiment of the semiconductor chip, the first contact point and the second one close

Contact point on the side surfaces, which form the contact points in places, flush with the carrier. Due to the fact that the contact points on the side surfaces of the

Semiconductor chips can be formed by the same separation process, with which also the carrier and the

Semiconductor bodies are generated, it is possible that the contact points on the side surfaces in the context of

Complete manufacturing tolerance flush with the other components of the semiconductor chip. In this way, for example, the metallic contact points on the side surfaces of the semiconductor body are not on the carrier and / or the

Semiconductor body over, but form with this one

common area. That is, the lateral dimensions of the semiconductor chip are not increased by the laterally arranged contact points, which in particular enables particularly compact semiconductor chips.

According to at least one embodiment of the semiconductor chip, at least two plated-through holes, which are themselves

extend in places through the semiconductor body, in Semiconductor chip formed, wherein the plated-through holes electrically conductive with the electrically conductive

Contact material are connected. That is to say, in the case of a semiconductor chip electrically contacted via the contact points, a current injection first takes place via the contact points to the plated-through holes and from there, for example, to an active layer of the semiconductor chip. In this case, it is possible that the plated-through holes extend completely through the carrier, in which case the bottom surface of the semiconductor chip is arranged on the side of the carrier facing away from the semiconductor body.

It also specifies a module. The module can in particular a semiconductor chip described here

include. That is, all for the semiconductor chip

disclosed features are also disclosed for the module and vice versa.

In accordance with at least one embodiment of the module, the module comprises a semiconductor chip described here as well as a connection carrier, the first connection points and the second connection

Having connection points. The semiconductor chip is by means of a connection material, which in places between the

Semiconductor chip and the connection carrier is arranged, mechanically and electrically conductively connected to the connection carrier. For this purpose, it is possible that the connection material has a mechanical and electrically conductive connection between the contact points of the semiconductor chip and the

Connection points of the connection carrier mediated. The connection material is, for example, a

Solder material or an electrically conductive adhesive. In accordance with at least one embodiment of the module, the connection material with the contact points is located on an underside of the contact points facing the connection carrier and on the side surfaces which form the contact points

train in places, in direct contact. That is, the semiconductor chip is not only attached to its bottom surface with the connection carrier, but the connection material, which may be, for example, a solder material or an electrically conductive adhesive, wets the contact points both at its the connection carrier

facing bottom and on the side surfaces of the semiconductor chip. In this way, a particularly strong adhesion between the semiconductor chip and the results

Connection carrier.

In accordance with at least one embodiment of the module, the module comprises a sheath which places the semiconductor chip in places on its side surfaces, the connection material on its side facing away from the semiconductor chip and the connection carrier

Outer surface and the connection carrier at its the

Semiconductor chip facing top surface at least partially covered. The sheath may be, for example, a plastic material such as a silicone or an epoxy resin. Further, the cladding may be radiation absorbing, radiation scattering, or radiation reflective

Additives, for example particles, which impart the casing with desired mechanical and optical properties. Thus, the envelope may be formed, for example, colored, black or white reflective.

The envelope may terminate flush with its upper side facing away from the connection carrier with the upper side of the semiconductor chip facing away from the connection carrier or laterally thereof overtop. The top of the semiconductor chip facing away from the connection carrier is preferably free of the envelope.

Due to the fact that the cladding laterally surrounds not only the chip but also the terminal material, the cladding also provides one in addition to its optical properties and its protective properties for the semiconductor chip

mechanical and chemical protection for the connection material. The enclosure can therefore also the

mechanical connection between semiconductor chip and

Stabilize connection carrier and protect against external influences.

According to at least one embodiment of the module, the module comprises a plurality of semiconductor chips, wherein the

Connection carrier at least two Verschaltungselemente

comprising, by at least one insulating layer

are electrically isolated from the connection points of the connection carrier. At least two of the

Semiconductor chips over at least one of

Connection elements must be connected in series. Furthermore, the interconnection elements in another level of

Connection carrier may be arranged as the connection points. In other words, the connection carrier may in particular be a multilayer connection carrier, in which interconnection elements are arranged in a different plane than the connection points of the connection carrier. The connection points can, for example, via

Through holes in the connection carrier with the

Connected interconnection elements.

In this way, it is possible, for example, to connect a string of semiconductor chips in series by means of interconnection elements which are arranged in a position or plane of the Connection carrier are arranged below the position or level of the connection points. Between

Connection points and the interconnection element is then at least one insulation layer, which with a

electrically insulating material is formed. For example, the levels can be parallel or as part of the

Manufacturing tolerance parallel to the main extension plane of the connection carrier run. In this way, modules with a large number of semiconductor chips can be realized in a particularly compact manner, in which the semiconductor chips can be controlled in the sense of a passive matrix display. Due to the fact that the semiconductor chips described here can be made particularly small, particularly compact modules can be realized with these semiconductor chips.

In the following, the method described here, the semiconductor chip described here, as well as the module described here will be described on the basis of exemplary embodiments and the associated embodiments

Figures explained in more detail.

With reference to the schematic sectional views of Figures 1A,

1B, 1C, 1D, IE, 1F, 1G, 1H, 2A, 2B, 2C, 2D, 2E, 2F, 2G are exemplary embodiments of the invention described herein

Explained method.

An exemplary embodiment of a semiconductor chip described here is explained in more detail with reference to the schematic sectional view of FIG. With reference to the schematic representations of Figures 4, 5, 6A, 6B exemplary embodiment of modules described here are explained in more detail. The same, similar or equivalent elements are provided in the figures with the same reference numerals. The figures and the proportions in the figures

Elements shown with each other are not as

to scale. Rather, individual elements for better presentation and / or for better

Comprehensibility must be exaggerated.

Figures 1A to 1H show process steps of a first embodiment of a method described herein in schematic sectional views. The figure IG shows a schematic sectional view of an embodiment of a semiconductor chip described here.

In the method, firstly an arrangement 12 comprising a carrier 1 and a semiconductor body 2 is provided. The semiconductor body 2 is epitaxially grown on the carrier 1, for example. The carrier 1 is then, for example, a sapphire substrate which is transparent in the spectral range of visible light. Of the

Semiconductor body 2 may include, for example, an active layer 21. The active layer 21 is in operation of the

produce semiconductor chips for the production of

provided and designed electromagnetic radiation. For example, it may include a quantum well structure with a plurality of barriers and quantum wells. In addition to the active layer 21, the semiconductor body 2 may be a first doped layer 22, which is, for example, n-doped, and a second doped layer 23, which may be p-doped, for example is, include. The semiconductor body 2 may be based on, for example, a III-V compound semiconductor material.

The provision of the arrangement 12 shown in connection with FIG. 1A can be achieved by epitaxially depositing the structure

Semiconductor body carried on the carrier.

In conjunction with FIG. 1B, a method step is shown, in which first vias 24 for

Contacting the first doped layer 22 and second vias 25 for contacting the second

doped layer 23 are produced in the semiconductor body 2. To generate the vias 24, 25 can

For example, openings are produced in the semiconductor body 2, which in places with an electrically insulating passivation material and an electrically conductive

Contact material for forming the vias

(English: vias) are filled. In the subsequent process step, Figure IC, are in the region of dividing lines 11, along which later

Dicing is done in individual semiconductor chips, recesses 4 generated by material removal. In the present case, the

Recesses from the side facing away from the carrier

Arrangement produced 12 ago. That is, the recesses

extend completely through the semiconductor body 2 and partially into the carrier 1 inside.

In the schematic plan view of Figure 1D is shown that the recesses 4 along the parting lines 11 as

Trenches can extend. The recesses 4 can then be along straight lines over the entire main surface of the

Arrangement 12 extend where they are generated. Alternatively, as shown in Figure IE, it is possible that the recesses, for example, at the intersections of the dividing lines 11 and thus at the grid points of a

generated regular square grid. Due to the formation of the recesses 4 at the intersections of

Dividing lines 11, the recesses can be formed with a particularly large diameter, without, for example, that too much material of the semiconductor body must be removed per semiconductor chip. After separating each one becomes

Recess with the contact material therein 6 used to a quarter of each chip, so pro

Semiconductor chip even with a recess with a large

Diameter is not lost too much chip area. Passivation and metallization of the recesses is particularly easy with large recesses.

In the case of FIG. 1D, the recesses therefore each extend over the entire length of a side surface; in the case of FIG. 1E, the recesses are formed only at the corners of the semiconductor chips to be produced.

In the next process step, Figure 1F, a

Passivation 5 generated on the inner surfaces of the recess, which extends to the carrier 1 remote from the surface of the semiconductor body 2 to the plated-through holes 24, 25. The passivation can be formed, for example, with an electrically insulating material such as silicon dioxide or silicon nitride.

In the next process step, FIG

remaining recesses 4 filled with the electrically conductive contact material 6. The passivation will be in advance Area of the plated-through holes 24, 25 is open or there has an opening, so that an electrically conductive

Connection between the contact material 6 and the

Through holes 24, 25 exists.

In the subsequent method step, a separation takes place along the parting lines 11 through the electrically conductive contact material 6. This results in semiconductor chips, as shown for example in Figure 1H. By separating along the parting lines 11 by the electrically conductive contact material 6 first contact points 61 and second contact points 62 are generated, wherein each of the

Pads 61, 62 places a side surface 10c of the semiconductor chip is formed. Another area of

Side surface 10 c of the semiconductor chip 10 is formed, for example, by a part of the carrier 1. In this way, the contact points 61, 62 extend along

Side surfaces to the bottom surface 10 b of the semiconductor chip 10, where they are electrically connected to the vias 24, 25. The contact points 61, 62 close to the

Side surface 10c of the semiconductor chip 10 flush with the carrier 1 from.

If, as shown in connection with FIG. 1D, the recesses are formed along trenches which extend along parting lines 11, then each of the recesses extends

Contact points 61, 62 along opposite

Side surfaces 10c of the semiconductor chip 10. Are the

Contact points only at the intersections of

Dividing lines 11 formed so in particular the corners of the semiconductor chip 10 in places by the contact points 61, 62 are formed. As can be seen in FIG. 1H, the distance B between the contact points 61, 62 may be as described herein

Semiconductor chip are chosen to be particularly large without the total contact area AI + A2 of the contact points is reduced. This is achieved by being part of the

Outside surface of the contact surface is arranged on the side surface of the chip and therefore on the bottom surface 10b of the chip, a region of larger area for the formation of the distance between the contact points is available, without the cooling of the semiconductor chip or the adhesion of the contact points is deteriorated on a connection material ,

A further exemplary embodiment of a method described here is explained in more detail in conjunction with the schematic sectional views of FIGS. 2A to 2G. The

schematic sectional view of Figure 2G shows a second embodiment of a described here

Semiconductor chips. Also in the embodiment of Figures 2A to 2G, first, an arrangement 12 of the carrier 1 and the

Semiconductor body 2 is provided. Again, can

For example, the semiconductor body 2 may be epitaxially deposited on the carrier 1.

In the next process step, FIG

Difference to the previous embodiment the

Via contacts 24, 25 produced by the semiconductor body 2 side facing away from the arrangement 12 ago. That is, the plated-through holes 24, 25 extend through the complete carrier 1 into the semiconductor body 2. In the subsequent method step, Figure 2C, the recesses 4 are generated in the region of the later dividing lines 11, wherein the recesses 4 exclusively by

Material removal are generated in the carrier and not in this embodiment in the semiconductor body. 2

extend.

In connection with the schematic plan views of FIGS. 2D and 2E, it is again shown that the recesses 4 can extend as trenches along the parting lines 11 or are formed at intersections of the parting lines 11, for example with a round cross section. Due to the formation of the recesses 4 at the intersections of the dividing lines 11, the recesses with a particularly large

Diameter be formed. After singulation, each recess with the contact material 6 therein is used to a quarter of each chip, so that per chip even with a large diameter recess is not lost too much chip area. Also a passivation and

Metallization of the recesses is particularly easy with large recesses.

If the carrier is formed with an electrically insulating material, such as sapphire, the application of a passivation 5 may be omitted in the next method step. This is shown in connection with Figure 2F, after which the recesses 4 with the electrically conductive

Contact material 6 are filled and this at the

Semiconductor body 2 remote from the underside of the carrier 1 is guided directly to the plated-through holes 24, 25, so that an electrically conductive connection between the electrically conductive contact material 6 and the

Vias 24, 25 is made. After separation along the parting lines 11, the result is shown schematically in connection with FIG. 2G

Semiconductor chip 10, in turn, the first and second

Contact points 61, 62 which extend in places along the bottom surface 10b and along the side surface 10c of the semiconductor chip 10 extend. Also for this

Semiconductor chip, the distance between the contact points 61, 62 are particularly large, without the

Total area AI plus A2 of the contact points 61, 62 must be reduced.

In connection with Figure 3 is another

Embodiment of a semiconductor chip described here described. In this embodiment, the

Recesses 4 formed such that they extend through the entire assembly 12 of the carrier 1 and the semiconductor body 2. As a result, the contact points 61, 62 extend from the carrier 1 to the semiconductor body 2 along the entire side surface 10 c of the semiconductor chip 10

Contact material 6 and the arrangement 12, the passivation 5 is arranged. Advantageously, it is possible to mount the semiconductor chip 10 with the semiconductor body 2 upwards, without the plated-through holes 24, 25 extending through the entire carrier. The plated-through holes 24, 25 are formed only in the semiconductor body 2.

In conjunction with the schematic sectional view of Figure 4 is a first embodiment of one here

described module explained in more detail. The module comprises the semiconductor chip 10, as explained in greater detail in connection with FIGS. 1H, 2G or 3, for example. Furthermore, the module 100 comprises a connection carrier 7, which has a Insulation layer 74 made of an electrically insulating

Material and first connection points 71 and second

Connecting points 72 has. Between the connection carrier 7 and the semiconductor chip 10, the connection material 8 is arranged, which may be, for example, a solder material. As can be seen from FIG. 4, the connection material 8 wets the contact points 61, 62 both in the

Area of the bottom surface 10b of the semiconductor chip 10 and in the region of the side surfaces 10c of the semiconductor chip. This is a particularly good thermal, electrical and

mechanical contacting of the semiconductor chip 10 am

Connection carrier 7 realized.

In connection with the figure 5 is another

Embodiment of a module described here explained in more detail. In addition to in connection with Figure 4

The module comprises a sheath 9. The sheath 9 encloses the semiconductor chip 10 at its

Side surfaces 10c, the connection material 8 at its

exposed outer surfaces and the connection carrier 7 at its uncovered by the semiconductor chip 10, the semiconductor chip 10 facing upper side. The wrapping material 9 may be, for example, a silicone material filled with reflective titanium dioxide particles. The envelope 9 is flush with the carrier 1 facing away from the outer surface of the

Semiconductor body 2 from. As semiconductor chip 10, each of the semiconductor chips described here can be used.

The connection carrier 7 of FIG. 5 in conjunction with FIG

described module comprises insulating layers 74, 78, through which different circuit levels of the module are formed. The insulating layer 74 separates the first and second terminals 71, 72 from the Interconnection elements 73a and 73b. The insulating layer 78 separates the interconnection elements 73a, 73b from the

Connection points 76a, 76b, with which the module can be contacted from the outside. The connection between the

individual conductive elements of the connection carrier 7 are produced by plated-through holes 75a, b and 79a, b.

The multi-layer connection carrier can be, for example, ceramic insulation layers 74, 78

include, in which the vias and the

Interconnection elements are monolithically integrated. Furthermore, it is possible that the connection carrier 7 is a multilayer printed circuit board in which the

Insulating layers 74, 78 are formed by plastic materials. In a module as described in connection with FIG. 5, for example, red, green and blue light-emitting semiconductor chips can be connected to one another, whereby a particularly cost-effective and compact RGB light-emitting diode can be specified

With a multi-layer connection carrier 7, as described in more detail in connection with Figure 5, can also

Matrix interconnections of semiconductor chips can be realized. This is explained in greater detail for example in connection with FIGS. 6A and 6B.

FIG. 6A shows a module with a plurality of

Semiconductor chips 10 in the schematic plan view; FIG. 6B shows a schematic sectional representation. Such a trained module may, for example, as part of a

Large-screen displays are used. As explained in connection with FIG. 6B, semiconductor chips 10 can be connected via the

Verschaltungselemente 73b are connected in series, wherein the interconnection element 73b through the insulating layer 74 of the first connection points 71 and the second

Connection points 72 of the connection carrier 7 is isolated. In the exemplary embodiment of FIG. 6, for example, the second connection locations 72 via the interconnection element 73a in the plane that pass through the insulation layer 74 from the first connection locations 71 and the second connection locations

72 is disconnected, interconnected. This plane can via the junction 76 b, which through the via 79 b through the insulating layer 78 with the through

Verschaltungselement 73b is connected to be contacted. For this purpose, all second connection points 72 via the

Through contacts 75b electrically connected to the interconnection element 73b.

Via vias 75a, the first

Connection points 71 of the semiconductor chips 10 are connected via a not shown Verschaltungselement 73a to the connection point 76a.

The semiconductor chips 10 of the module 100 can be controlled in this way in the sense of a passive matrix display.

The invention is not limited by the description based on the embodiments of these. Rather, the invention encompasses every new feature as well as every combination of features, which in particular includes any combination of features in the patent claims, even if this feature or combination itself is not explicitly described in the claims

Claims or embodiments is given. Reference sign list

1 carrier

10 semiconductor chips

10c side surface

10b floor space

11 dividing line

12 arrangement

2 semiconductor body

21 active layer

22 first doped layer

23 second doped layer

24 first via

25 second via

4 recess

5 passivation

6 contact material

61 first contact point

62 second contact point

7 connection carrier

7a deck area

71 first connection point

72 second connection point

73a, b Interconnection elements

74.78 Isolation layer

75a, b through-connection

76a, b junction

79a, b through-connection

8 connection material

8c outer surface

9 serving 100 module

B distance

AI contact area

A2 contact surface

Claims

claims

1. A process for producing a variety of

Semiconductor chips (10) comprising the following steps:

Providing an arrangement (12) comprising a carrier (1) and a semiconductor body (2),

Forming a plurality of recesses (4) in the

Arrangement (12), wherein in the region of the recesses (4) a part of the carrier (1) is removed,

- At least partially filling the recesses (4) with an electrically conductive contact material (6), and

- Separating the assembly (12) along a plurality of

Dividing lines (11) in the plurality of semiconductor chips (10), wherein

- The separation takes place in places by the electrically conductive contact material (6).

2. The method according to the preceding claim, wherein

- At least one of the plurality of semiconductor chips (10) has a first contact point (61) and a second contact point

(62) comprising the electrically conductive contact material (6) is generated,

each contact point (61, 62) locally forms a side surface (10c) of the semiconductor chip (10),

each contact point (61, 62) extends in places on a bottom surface (10b) of the semiconductor chip (10), and

- The contact points (61, 62) for electrically contacting the semiconductor chip (10) are formed.

3. The method according to any one of the preceding claims, wherein

- When forming the plurality of recesses (4) the

Recesses (4) from the carrier (1) facing away from the semiconductor body (2) are produced forth, and - The semiconductor body (2) in the region of the recesses (4) is completely removed.

4. The method according to any one of claims 1 to 2, wherein

- When forming the plurality of recesses (4) the

Recesses (4) from the semiconductor body (2) facing away from the carrier (1) are produced forth, and

- The recesses (4) extend into the carrier (1) without completely penetrate the carrier (1).

5. Method according to one of the preceding claims,

wherein a plurality of plated-through holes (24, 25) is produced,

- The vias (24, 25) in places extend through the semiconductor body (2), and

- The vias (24, 25) are electrically conductively connected to the electrically conductive contact material (6).

6. The method according to the preceding claim, wherein

- The vias (24, 25) extend completely through the carrier (1).

7. The method according to any one of the preceding claims, wherein - when providing the arrangement (12) of the semiconductor body (2) epitaxially deposited on the carrier (1).

8. semiconductor chip (10) with

a carrier (1) and a semiconductor body (2), and

- A first contact point (61) and a second

Contact point (62), which are designed for electrical contacting of the semiconductor chip (10), wherein the first contact point (61) and the second contact point (62) comprise an electrically conductive contact material (6),

- Each contact point (61, 62) in places a side surface (10c) of the semiconductor chip (10) is formed, and

- Each contact point (61, 62) extends in places on a bottom surface (10b) of the semiconductor chip (10).

9. Semiconductor chip according to the preceding claim,

wherein the first contact point (61) and the second

Contact point (62) facing away from the carrier (1)

Outside surface in the area of the side surface (10c) of

Semiconductor chips (10) which form the contact points (61, 62) in places, traces of a separation process

exhibit .

10. Semiconductor chip after one of the two previous ones

Claims,

wherein the first contact point (61) and the second

Contact point (62) on the side surfaces (10c), the

Make contact points (61, 62) in places, flush with the carrier (1).

11. The semiconductor chip according to one of the previous three claims, wherein

- At least two vias (24, 25) are formed, which extend in places through the semiconductor body (2), and

- The plated-through holes (24, 25) are electrically conductively connected to the electrically conductive contact material (6).

12. Semiconductor chip according to the preceding claim,

in which - The vias (24, 25) extend completely through the carrier (1).

13. Module with

- At least one semiconductor chip (10) according to one of the previous five claims, and

- A connection carrier (7), the first connection points (71) and second connection points (72), and

- A terminal material (8) that is arranged in places between the semiconductor chip (10) and the connection carrier (7), wherein

- The terminal material (8) provides a mechanical and electrically conductive connection between the contact points (61, 62) of the semiconductor chip (10) and the connection points (71, 72) of the connection carrier (7), and

- The terminal material (8) with the contact points (61, 62) on one of the connection carrier (7) facing bottom of the contact points (61, 62) and on the side surfaces (10c), which form the contact points (61, 62) in places, in direct contact.

14. Module according to the previous claim with

- a sheath (9), the semiconductor chip (10)

in places on its side surfaces (10c), the

Connection material (8) on its the semiconductor chip (10) and the connection carrier (7) facing away from the outer surface (8c), and the connection carrier (7) on its the semiconductor chip (10) facing the top surface (7a) covered at least in places.

15. Module according to one of the preceding claims with

- A plurality of semiconductor chips (10), wherein

- The connection carrier (7) at least two

Verschaltungselemente (73a, b) comprises, by at least an insulating layer (74, 78) electrically from the

Connection points (71, 72) are insulated,

- At least two of the semiconductor chips (10) via at least one of the interconnection elements (73 a, b) are connected in series, and

- The formwork elements (73a, b) in a different plane of the connection carrier (7) than the connection points (71, 72) are arranged.