WO2012107290A1 - Puce semiconductrice optoélectronique à couche miroir encapsulée - Google Patents

Puce semiconductrice optoélectronique à couche miroir encapsulée Download PDF

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Publication number
WO2012107290A1
WO2012107290A1 PCT/EP2012/051145 EP2012051145W WO2012107290A1 WO 2012107290 A1 WO2012107290 A1 WO 2012107290A1 EP 2012051145 W EP2012051145 W EP 2012051145W WO 2012107290 A1 WO2012107290 A1 WO 2012107290A1
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WIPO (PCT)
Prior art keywords
layer
semiconductor chip
semiconductor
layer sequence
sequence
Prior art date
Application number
PCT/EP2012/051145
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German (de)
English (en)
Inventor
Lutz Höppel
Original Assignee
Osram Opto Semiconductors Gmbh
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Filing date
Publication date
Application filed by Osram Opto Semiconductors Gmbh filed Critical Osram Opto Semiconductors Gmbh
Publication of WO2012107290A1 publication Critical patent/WO2012107290A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body

Definitions

  • the present application relates to a so-called thin-film LED chip in which the
  • Carrier substrate side facing the semiconductor layer sequence is provided with a mirror layer to deflect in the direction of the carrier substrate emitted radiation in the direction of the radiation exit surface and thereby the
  • silver is particularly suitable as the material for the mirror layer, since it is characterized by high reflection, but silver is, on the other hand, sensitive to corrosion.
  • Optoelectronic semiconductor chips are usually contacted via a bonding pad, which is arranged on the carrier surface opposite the radiation exit surface. This has the disadvantage that part of the
  • Radiation exit surface is shadowed by the Bondpad.
  • Semiconductor chip are a first and second electrical
  • Connection layer disposed on one of the radiation exit surface opposite back of the LED chip and isolated from each other by means of a separating layer, wherein a portion of the second electrical
  • Terminal layer extends from the back side of the semiconductor chip through an opening of the active layer toward the front side of the semiconductor chip.
  • the present application has for its object to provide an improved optoelectronic semiconductor chip, wherein the contact is designed such that the entire surface of the semiconductor chip can be used for light emission and no significant shadowing of
  • optoelectronic semiconductor chip a carrier substrate and a semiconductor layer sequence containing a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and an active layer disposed therebetween.
  • the first semiconductor region faces the carrier substrate and is preferably a p-type semiconductor region.
  • the second semiconductor region faces the radiation exit surface of the semiconductor chip and is preferably an n-type semiconductor region.
  • the optoelectronic semiconductor chip is preferably a so-called thin-film semiconductor chip, in which the original growth substrate is detached from the semiconductor layer sequence and the semiconductor layer sequence at the
  • a mirror layer is advantageously arranged, which is a
  • the mirror layer may comprise or consist of aluminum or silver, for example. Particularly preferred is silver as a material for the mirror layer, since silver is characterized by a high
  • the optoelectronic semiconductor chip comprises an electrically insulating transparent encapsulation layer, which covers the side edges of the mirror layer and the
  • the electrically insulating transparent encapsulation layer protects the mirror layer from corrosion.
  • the side flanks of the semiconductor layer sequence are electrically insulated by the transparent encapsulation layer.
  • the optoelectronic semiconductor chip has a bonding pad, which laterally displaces the semiconductor layer sequence
  • the bonding pad is thus not arranged in particular on the radiation exit surface of the semiconductor layer sequence, but next to the semiconductor layer sequence over the carrier substrate.
  • the bondpad is preferred
  • the bondpad may also comprise a plurality of sub-layers, for example a Ti / Pt / Au layer sequence.
  • a contact layer is at least on partial regions of
  • Radiation exit surface arranged.
  • the contact layer on the radiation exit surface is electrically conductively connected to the bond pad by means of an electrical connection layer.
  • Connecting layer is on the transparent
  • the optoelectronic semiconductor chip has no significant shading of the radiation exit surface since
  • Semiconductor layer sequence is arranged on the carrier substrate. Within the semiconductor layer sequence are no
  • the semiconductor layer sequence preferably has a projection over the mirror layer on all side flanks of the semiconductor chip.
  • a gap which is formed between the semiconductor layer sequence and a layer sequence applied to the carrier substrate, advantageously adjoins the side flanks of the mirror layer.
  • Gap is beneficial from the transparent
  • the transparent encapsulation layer is advantageously prepared by means of atomic layer deposition (ALD - atomic layer deposition).
  • Methods can advantageously produce very dense layers with low defect density. Furthermore, this one has
  • the transparent encapsulation layer preferably comprises an aluminum oxide, a zirconium oxide, a titanium oxide, a hafnium oxide or a silicon oxide. These materials are advantageously transparent and electrically insulating.
  • Encapsulation layer may in particular also several
  • the transparent encapsulation layer may contain one or more layers of Al 2 O 3 , ZrC> 2, T1O 2 or HfC> 2, wherein a protective layer of SiO 2 is applied to the at least one sublayer. In this way, on the one hand, a good protection of
  • connection layer and the side edges of the semiconductor chip achieved. Furthermore, by means of the transparent encapsulation layer, an electrical insulation between metallic layers applied to the carrier substrate, which leads to the electrical connection of the first
  • the transparent encapsulation layer preferably has a thickness of 1 ⁇ or less. If the transparent
  • Encapsulation layer has multiple sub-layers, is under the thickness of the total thickness of the transparent
  • the contact layer is preferably transparent.
  • the fact that the contact layer is transparent occurs in comparison to an absorbent contact layer such as a metal layer no shading of
  • the transparent conductive oxide is indium tin oxide (ITO).
  • Contact layer structured such that it covers only portions of the radiation exit surface. This is advantageous in particular if the surface of the semiconductor layer sequence serving as the radiation exit surface is for
  • Auscooppel Modell or roughening has.
  • the radiation extraction from the uncovered by the contact layer portions of the radiation exit surface is particularly efficient.
  • the contact layer may in particular have one or more contact webs extending over the radiation exit surface.
  • a uniform current injection is advantageously effected in the semiconductor layer sequence. This is advantageous in particular when the electrical connection layer adjoins only one corner or one side edge of the semiconductor layer sequence.
  • the contact webs preferably form a lattice structure.
  • the contact webs can have an edge web which runs around the edge of the radiation exit surface in order to supply the stream in particular also to the edge regions of the web Impress semiconductor chips. Starting from the edge web, one or more contact webs advantageously extend over the radiation exit surface in order to achieve the most uniform possible current injection into the semiconductor layer sequence. The extending over the radiation exit surface
  • contact webs can form a rectangular grid.
  • the electrical connection layer has a transparent conductive oxide. In this case are advantageous both the electric
  • the electrical connection layer may in particular comprise indium tin oxide.
  • the electrical connection layer has the same material as the contact layer, so that, for example, both the contact layer and the electrical connection layer have a transparent conductive oxide such as indium tin oxide.
  • the semiconductor layer sequence preferably has a lateral extent of 300 ⁇ or less.
  • the semiconductor layer sequence can be a rectangular or
  • Shadowing would occur because the bondpad is on a
  • the semiconductor layer sequence has a plurality of partial regions arranged next to one another, wherein the partial regions are separated from one another by one or more trenches.
  • the at least one trench preferably runs a metallic contact strip, which connects the bonding pad with the electrical connection layer electrically conductive.
  • a metallic contact strip may emanate from a bonding pad, wherein at least one subregion of the semiconductor layer sequence is in each case connected to each of the contact strips by means of the electrical
  • Connection layer is connected. In this way, for example, several sub-areas of a
  • the total lateral extent of the chip in this case can be much greater than the lateral extent of the
  • Subregions preferably take place via a single bond pad, which is connected in each case to the electrical connection layer by means of the contact strip extending in the at least one trench between the semiconductor regions.
  • FIG. 1 shows a schematic representation of a cross section through an optoelectronic semiconductor chip according to a first exemplary embodiment
  • Figures 2A to 21 is a schematic representation of a
  • FIG. 3 shows a schematic representation of a plan view of an optoelectronic semiconductor chip according to a second exemplary embodiment
  • FIG. 4 shows a schematic illustration of a plan view of an optoelectronic semiconductor chip according to a third exemplary embodiment, a schematic representation of a cross section through an optoelectronic semiconductor chip according to a fourth exemplary embodiment
  • Figures 6A to 6E is a schematic representation of a
  • FIG. 7 shows a schematic representation of a plan view of an optoelectronic semiconductor chip according to a fifth exemplary embodiment. Same or equivalent components are in the
  • the optoelectronic semiconductor chip 1 shown schematically in cross section in FIG. 1 contains a
  • semiconductor region 3 of a first conductivity type and a second semiconductor region 5 of a second conductivity type are semiconductor regions 3 of a first conductivity type and a second semiconductor region 5 of a second conductivity type.
  • the first semiconductor region 3 is a p-type semiconductor region and the second semiconductor region 5 is an n-type semiconductor region. Between the first semiconductor region 3 is a p-type semiconductor region and the second semiconductor region 5 is an n-type semiconductor region. Between the first semiconductor region 3 and the second semiconductor region 5 is an n-type semiconductor region.
  • an active region 4 is arranged.
  • the active zone 4 of the optoelectronic semiconductor chip 1 is preferably an active zone suitable for the emission of radiation.
  • the active zone 4 may be a pn junction, a double heterostructure, a simple
  • Quantum well structure or multiple quantum well structure may be formed.
  • the semiconductor layer sequence 2 of the semiconductor chip 1 is preferably based on an I I I-V compound semiconductor material, in particular on an arsenide, nitride or phosphide compound semiconductor material.
  • an I I I-V compound semiconductor material in particular on an arsenide, nitride or phosphide compound semiconductor material.
  • III-V compound semiconductor material does not necessarily have a
  • the optoelectronic semiconductor chip 1 has a
  • Carrier substrate 11 which is preferably not equal to the growth substrate of the semiconductor layer sequence 2 and, for example, by means of a connection layer 12, which may be in particular a solder layer of a metal or a metal alloy, is connected to the semiconductor chip 1.
  • the carrier substrate 11 may alternatively also be produced galvanically. Preferably that is
  • Carrier substrate 11 electrically conductive and serves for
  • the carrier substrate 11 preferably comprises silicon, nickel, copper or molybdenum.
  • a mirror layer 6 is arranged downstream of the first semiconductor region 3 on the side facing the carrier substrate 11 and can, in particular, adjoin the semiconductor layer sequence 2. It is also possible that between the first semiconductor region 3 and the Mirror layer 6 is an intermediate layer,
  • a thin adhesive layer (not shown).
  • Mirror layer 6 are, for example, the connection layer 12, in particular a solder layer made of a metal or a metal alloy, a contact metallization 13, which may in particular be a Ti / Pt / Au layer sequence, and a barrier layer 14, which may be, for example can be a TiW (N) layer.
  • connection layer 12 in particular a solder layer made of a metal or a metal alloy
  • contact metallization 13 which may in particular be a Ti / Pt / Au layer sequence
  • a barrier layer 14 which may be, for example can be a TiW (N) layer.
  • Barrier layer 14 in particular prevents diffusion of constituents of the mirror layer 6 in the
  • the mirror layer 6 contains in particular silver, aluminum or a metal alloy with silver or aluminum. These materials are characterized by a high reflectivity in the visible spectral range and a good electrical
  • the mirror layer 6 on the one hand has the function of the active layer 4 in the direction of
  • Carrier substrate 11 emitted radiation for
  • the electrical contacting of the second semiconductor region 5 takes place by means of a contact layer 7 which, at least on partial regions of the radiation exit surface 15 of the
  • Semiconductor chips 1 is arranged. The surface of the
  • Radiation exit surface 15 of the semiconductor chip 1 forms, preferably has a roughening or decoupling structure 18th on to the radiation extraction from the
  • the contact layer 7 is preferably transparent.
  • transparent contact layer 7 has in particular
  • Radiation exit surface 15 is transparent, the
  • Semiconductor chip 1 advantageously not or only slightly affected.
  • the contact layer 7 covers only partial regions of the radiation exit surface 15.
  • the transparent contact layer 7 may have one or more contact webs (not shown) extending over the radiation exit surface 15, which may in particular form a lattice structure.
  • Encapsulation layer 10 on the one hand has the function that
  • Mirror layer 6 to protect against corrosion.
  • the mirror layer 6 is protected by the encapsulation layer 10 from oxidation or the ingress of moisture.
  • the side edges 16 of the mirror layer 6 are preferably surrounded on all sides by the encapsulation layer 10, so that the Mirror layer 6 at any point directly to the
  • the transparent encapsulation layer 10 preferably has at least one of the materials Al 2 O 3 , ZrC> 2 , T1O 2 , HfO 2 or S1O 2 .
  • the transparent encapsulation layer 10 preferably has at least one of the materials Al 2 O 3 , ZrC> 2 , T1O 2 , HfO 2 or S1O 2 .
  • the transparent encapsulation layer 10 preferably has at least one of the materials Al 2 O 3 , ZrC> 2 , T1O 2 , HfO 2 or S1O 2 .
  • the transparent encapsulation layer 10 preferably has at least one of the materials Al 2 O 3 , ZrC> 2 , T1O 2 , HfO 2 or S1O 2 .
  • Encapsulation layer 10 at least two partial layers
  • the encapsulation layer 10 may comprise a base layer of aluminum oxide, zirconium oxide, titanium oxide or hafnium oxide and a top layer of silicon oxide. Such a transparent encapsulation layer 10 protects the mirror layer 6 in a particularly effective manner
  • the thickness of the transparent encapsulation layer 10 is
  • Encapsulation layer 10 is made of several layers, the thickness of the encapsulation layer 10 is to be understood as the total thickness. In a particularly preferred embodiment, the
  • Semiconductor layer sequence 2 extend.
  • the side edges 16 of the mirror layer 6 are in this embodiment
  • the distance between the side edges 21 of the semiconductor layer sequence 2 and the side edges 16 of the mirror layer 6 is preferably between 0.5 ⁇ and 5 ⁇ , more preferably about 3 ⁇ . In this way, the mirror layer 6 is particularly effectively protected.
  • the contact layer 7 on the radiation exit surface 15 is connected to a bonding pad 9 by means of an electrical connection layer 8.
  • the bonding pad 9 is arranged in a lateral direction away from the semiconductor layer sequence 2 and in particular does not cover the radiation exit surface 15
  • the electrical connection layer 8 extends from an edge region of the radiation exit surface 15, to which the electrical connection layer 8 is connected to the transparent contact layer 7, over a partial region of the encapsulation layer 10 which covers the side edges 21 of the semiconductor layer sequence 2, except for a region of the encapsulation layer 10 covering the carrier substrate 11 with the layers 12, 13, 14 applied thereon.
  • Bondpad 9 is on a range of electrical
  • Connection layer 8 is arranged, which is spaced from the side edges 21 of the semiconductor layer sequence 2 and extends parallel to the main plane of the semiconductor layer sequence 2 on the above the carrier substrate 11 arranged encapsulation layer 10.
  • the electrical connection layer 8 preferably contains a transparent conductive oxide, in particular indium tin oxide.
  • the electrical connection layer can therefore be formed in particular from the same material as the transparent contact layer 7 on the radiation exit surface of the
  • the electrical connection layer 8 is advantageously transparent. This has the advantage that radiation, which is transparent Encapsulation layer 10 penetrates at the side edges 21 of the semiconductor chip, is not absorbed, which could lead to heating of the semiconductor chip and to a reduction in efficiency.
  • FIG. 1 An exemplary embodiment of a production method for producing the optoelectronic semiconductor chip illustrated in FIG. 1 is explained below with reference to FIGS. 2A to 21.
  • Method is the semiconductor layer sequence 2, the first semiconductor region 3, the active zone 4 and the second
  • Semiconductor region 5 has been grown on a growth substrate 20.
  • the growth preferably takes place epitaxially, in particular by means of MOVPE.
  • Semiconductor layer sequence 2 may be, for example
  • Nitride compound semiconductor materials and the growth substrate 20 may be a sapphire substrate.
  • Semiconductor region 3 is preferably a p-type
  • Semiconductor region and the second semiconductor region 5 is preferably an n-type semiconductor region.
  • a mirror layer 6 is applied to the growth substrate 20
  • Mirror layer 6 preferably contains silver.
  • the barrier layer 14 has been applied, which may contain, for example, TiW (N).
  • the barrier layer 14 has the function of diffusion of the Material of the mirror layer in subsequent
  • the barrier layer 14 is followed by a contact metallization 13, which may have a plurality of partial layers, in particular a Ti / Pt / Au layer sequence.
  • the layer sequence produced in this way is on the side opposite the growth substrate 20,
  • connection layer 12 with a carrier substrate 11 has been connected.
  • the carrier substrate 11 may in particular be electrically conductive and has
  • connection layer 12 may be, for example, a
  • Be solder layer in particular an AuSn solder layer.
  • the growth substrate 20 has been detached from the semiconductor layer sequence 2.
  • the optoelectronic semiconductor chip 1 is shown rotated by 180 ° in comparison to the previous figures, since now the carrier substrate 11 opposite the original growth substrate 20 acts as the sole carrier of the semiconductor chip 1.
  • the growth substrate 20, in particular a sapphire substrate, may, for. B. by means of a laser lift-off process of the semiconductor layer sequence 2 are replaced.
  • Decoupling structure 18 can be produced for example by etching with KOH. In this way, the
  • the semiconductor layer sequence 2 becomes a mesa structure
  • Structuring is preferably carried out by photolithography, it being possible for example to use H 3 PO 4 as etchant.
  • Process step is the mirror layer 6 with a
  • Etching process has been structured such that it has a smaller lateral extent than the semiconductor layer sequence 2.
  • the semiconductor layer sequence 2 preferably has a projection on all sides over the mirror layer 6. On the side edges 16 of the mirror layer 6 so each adjacent to a gap between the
  • the side edges 16 of the mirror layer 6 are spaced from the side edges 21 of the semiconductor layer sequence 2. The distance is
  • the layer sequence produced in this way is an electrical step in the intermediate step shown in FIG. 2G insulating transparent encapsulation layer 10 has been applied.
  • the transparent encapsulation layer 10 preferably contains at least one of the materials Al 2 O 3 , ZrO 2 , TiO 2 , HfC> 2 or S1O 2.
  • the transparent encapsulation layer 10 is preferably produced by means of atomic layer deposition (ALD). With this procedure for
  • Layer deposition can be advantageously deposited particularly pure and dense layers. Furthermore, this method has the advantage that a layer deposition is possible even in comparatively small spaces,
  • a layer 7, 8 is made of a transparent conductive oxide
  • conductive oxide layer 7, 8 may in particular be an ITO layer and, for example, have a thickness of about 250 nm.
  • Another part 8 of the transparent conductive oxide layer extends from an edge region of the transparent
  • Encapsulation layer 10 provided side edge 21 of
  • the transparent contact layer 7 and the electrical connection layer 8 are thus made of the same material and can be applied and / or structured in particular in the same step.
  • Optoelectronic semiconductor chip 1 is in a further process step on the range of electrical
  • Connecting layer 8 which is parallel to the main plane of the
  • the bonding pad 9 may include one or more metal layers
  • FIG. 3 shows an embodiment of the optoelectronic semiconductor chip 1 in a plan view.
  • the contact webs 17 form a lattice structure on the radiation exit surface 15.
  • the exemplary embodiment is a rectangular lattice, in which the contact lugs 17 are arranged in, for example, eight rows and eight columns.
  • the structuring of the transparent contact layer 7 to contact webs 17, in particular to a lattice structure has the advantage that on the one hand a good flow expansion is achieved, d. H. the current is impressed uniformly over the entire cross-sectional area of the semiconductor layer sequence into the semiconductor chip 1. Furthermore, remain between the contact areas, where the
  • Radiation exit surface 15 is free of the contact layer 7, so in this way a particularly good
  • Contact layer 7 is by means of an electrical
  • Connecting layer 8 electrically conductively connected to a bonding pad 9.
  • the electrical connection layer 8 is like the transparent contact layer 7 of a transparent
  • conductive oxide in particular ITO formed.
  • the electrical connection layer 8 has a region 8a in which it is in an edge region of the
  • Electrical connection layer 8 extends over the provided with the encapsulation layer 10 side edges 21 of the semiconductor chip 1.
  • a third region 8c of the electrical Connection layer is on a parallel to the main plane of the semiconductor layer sequence extending region of
  • the transparent encapsulation layer 10 is arranged.
  • the bonding pad 9 is arranged laterally offset from the semiconductor layer sequence.
  • the electrical connection layer 8 and the bonding pad 9 are in a corner of the optoelectronic
  • Radiation exit surface 15 is not from the bonding pad.
  • This type of electrical contacting is particularly advantageous for optoelectronic semiconductor chips 1, whose side length is about 300 ⁇ or less. In such comparatively small optoelectronic
  • Semiconductor chips 1 would be absorbed by absorbing material of the bonding pad 9 in an arrangement of the bonding pad 9 on the radiation exit surface 15, a significant portion of the emitted radiation.
  • FIG. 4 shows a further exemplary embodiment of the invention
  • Semiconductor layer sequence are each configured as in the embodiment shown in Figure 3.
  • the optoelectronic semiconductor chip 1 has a central bonding pad 9 which is disposed on the electrical connection layer 8 is arranged, which is guided over the side edges of the regions 22 of the semiconductor layer sequence respectively to the transparent contact layers 7.
  • a central bonding pad 9 which is disposed on the electrical connection layer 8 is arranged, which is guided over the side edges of the regions 22 of the semiconductor layer sequence respectively to the transparent contact layers 7.
  • the trenches 19 extending from the bond pad 9 metallic
  • Contact strip 23 which may be formed for example of the same material as the bonding pad and
  • Bondpad can be made. The electric
  • Connecting layer 8 contacts the contact layer 7 not only at the corners of the portions 22 of the
  • the partial regions 22 of the semiconductor layer sequence preferably each have a side length of 300 ⁇ m or less.
  • FIG. 5 shows a further exemplary embodiment of the invention
  • Optoelectronic semiconductor chip 1 shown in a cross section.
  • the optical semiconductor chip 1 shown in a cross section.
  • the contact layer 7 is applied to the surface of the second semiconductor region 5, which is preferably provided with a coupling-out structure 18, which is preferably an n-type semiconductor region.
  • the contact layer 7 preferably comprises a transparent conductive oxide such as ITO and can
  • Encapsulation layer 10 These process steps correspond to those previously described in connection with FIGS. 2E to 2G
  • a metallization such as a Ti / Pt / Au layer sequence, applied and structured, which the electrical
  • Connecting layer 8 and the bonding pad 9 forms.
  • the optoelectronic semiconductor chip is essentially as shown in FIG.
  • the metallization which forms the bonding pad 9 in addition to the semiconductor layer sequence 2, therefore also extends beyond the side flanks of the semiconductor chip 1 provided with the electrically insulating encapsulation layer 10 as far as the radiation exit area 15, where it abuts the transparent contact layer 7 and electrically connects it to the bonding pad 9.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

L'invention concerne une puce semiconductrice optoélectronique (1), comprenant un substrat support (11), une succession de couches semiconductrices (2) qui comprend une première zone semiconductrice (3) d'un premier type de conduction, une seconde zone semiconductrice (5) d'un second type de conduction et une couche active (4) placée entre ces deux zones, une couche miroir (6) placée entre le substrat support (11) et la succession de couches semiconductrices (2), une couche d'encapsulage (10) transparente électriquement isolante qui recouvre des flancs latéraux (16) de la couche miroir (6) et des flancs latéraux (21) de la succession de couches semiconductrices (2), une plage de connexion (9) placée de manière latéralement décalée par rapport à la succession de couches semiconductrices (2), une couche de contact (7) permettant la mise en contact électrique de la seconde zone semiconductrice (5), laquelle couche de contact est placée au moins sur des parties de la surface de sortie de rayonnement (15), ainsi qu'une couche de liaison électrique (8) qui relie la plage de connexion (9) à la couche de contact (7) de manière électriquement conductrice, et qui est guidée sur la couche d'encapsulage (10) transparente vers la plage de connexion (9) par l'intermédiaire des flancs latéraux (21) de la succession de couches semiconductrices (2).
PCT/EP2012/051145 2011-02-07 2012-01-25 Puce semiconductrice optoélectronique à couche miroir encapsulée WO2012107290A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE201110010504 DE102011010504A1 (de) 2011-02-07 2011-02-07 Optoelektrischer Halbleiterchip
DE102011010504.2 2011-02-07

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US10658548B2 (en) 2016-03-18 2020-05-19 Osram Oled Gmbh Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip

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EP4089746A1 (fr) * 2021-05-11 2022-11-16 Excellence Opto. Inc. Structure verticale de diode électroluminescente comportant une couche métallique pouvant tester et protéger les parois latérales

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