EP2380198A1 - Interrupteur autobloquant - Google Patents

Interrupteur autobloquant

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Publication number
EP2380198A1
EP2380198A1 EP09799288A EP09799288A EP2380198A1 EP 2380198 A1 EP2380198 A1 EP 2380198A1 EP 09799288 A EP09799288 A EP 09799288A EP 09799288 A EP09799288 A EP 09799288A EP 2380198 A1 EP2380198 A1 EP 2380198A1
Authority
EP
European Patent Office
Prior art keywords
transistor
contact
voltage
self
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP09799288A
Other languages
German (de)
English (en)
Inventor
Ingo Daumiller
Ertugrul SÖNMEZ
Mike Kunze
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microgan GmbH
Original Assignee
Microgan GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microgan GmbH filed Critical Microgan GmbH
Publication of EP2380198A1 publication Critical patent/EP2380198A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the invention relates to a self-locking switch with at least one transistor which is conductive in the non-switched state.
  • Transistors are used in circuits for controlling the flow of current. In switched applications, they serve as electronic switches to allow or block the flow of current. Depending on
  • an electronic switch shows a certain and usually unwanted series resistance in the on state as well as an Isier lierfestmaschine up to a characteristic voltage in the off state.
  • the electronic switches are in the non-controlled state (ie when there is no voltage between gate and source), they are in the off state, they are of the so-called self-locking type, and vice versa. returns from the so-called self-conducting type when they are conducting without voltage applied.
  • self-locking transistors are preferred for safety reasons, in order to avoid unwanted short circuits in the event of failure of the control electronics.
  • One transistor used in power electronics is the AlGaN / GaN High Electron Mobility Transistor (HEMT, High Electron Mobility Transistor).
  • HEMT High Electron Mobility Transistor
  • at least one AlGaN layer and at least one GaN layer adjoin one another.
  • a two-dimensional electron lake (2DEG, also two-dimensional electron gas) is formed, which is contacted by ohmic contacts "source” (S) and “drain” (D) and controlled by means of a gate electrode (G).
  • S source
  • D drain
  • G gate electrode
  • the transistor is of the normally-on type and thus poorly suited for common circuit topologies in power electronics.
  • the conductive region in the transistor, ie where the two-dimensional electron gas is present, is referred to as the channel.
  • the channel is cut off at the normally-on transistor only by a suitable negative voltage between the gate and source, whereby the transistor is set in an insulating operating state. If in this application of a conductive or insulating or non-conductive transistor is mentioned, this refers to the distance between the source and drain.
  • the voltage between gate and source, below which the channel can be regarded as being pinched off, is referred to as a threshold voltage or threshold voltage and is negative in the case of a self-conducting transistor (V th ⁇ 0 V).
  • V th self-conducting transistor
  • the most widely used approach in research and industry is to deplete the channel or the 2DEG under the gate electrode by means of suitable bandgap engineering, in order to make the transistor self-locking in this way, so that the 2DEG first generated by applying a positive gate-to-source voltage and the transistor is turned on (so that V th > 0 V.)
  • the two most widely used approaches for the suitable bandgap engineering are reducing the AlGaN layer thickness below the Position of the gate electrode by suitable etching methods and / or the introduction of p-type dopants below the channel and below the gate contact in the GaN layer
  • Another method for lowering the charge carriers in the AlGaN / GaN boundary layer under the gate region, of the is reported, placed under the gate region in the AlGaN layer negative fluorine ions by ion bombardment. The introduction of the fluorine ions to the charge carriers in the channel u nter the gate area deplete.
  • this method is currently still controversial.
  • Layer thickness is particularly critical.
  • the adjustment of the function of the normally-off operation is dependent on a low-damage etching of the semiconductor layer located above the 2DEG with an accuracy in the (sub) -nm range.
  • the disadvantage of the etching depth-sensitive adjustment of the threshold voltage to values greater than zero can be mitigated by applying a topcoat layer over the AlGaN layer under the ohmic contacts.
  • the formation of the 2DEG is determined by the barrier material thickness t, ie the thickness of the AlGaN layer, the aluminum molar content x of the AlGaN layer, the choice of the semiconductor material of the final layer, which has a thickness in the range of a few nanometers, and the gate metallization , which forms the Schottky contact at the location of the channel.
  • the barrier material thickness t ie the thickness of the AlGaN layer, the aluminum molar content x of the AlGaN layer, the choice of the semiconductor material of the final layer, which has a thickness in the range of a few nanometers
  • the gate metallization which forms the Schottky contact at the location of the channel.
  • the objective is to maximize channel conduction away from gate metallization by appropriate setting of said parameters and to inhibit formation of the 2DEG below gate metallization with the purpose of obtaining minimum parasitic series resistances in the transistor for V th > 0V ,
  • first approximation is
  • the object of the present invention is to provide a temperature-insensitive switch, which i.a. is usable in the power electronics and in the non-controlled state is in a blocking, non-self-conductive state.
  • the channel conductivity should be maintained and the series resistance of the switch should remain low.
  • the switch should also be economically producible and have a stable characteristic.
  • a switch which is self-locking, ie interrupts a current flow between an outer drain and an outer source contact, when no control voltage is applied to an outer gate contact.
  • the switch has at least one transistor which is conductive when a control voltage of the transistor, ie a voltage between a gate contact and a source contact of the transistor, is zero.
  • the switch according to the invention thus makes it possible to provide the function of a normally-off switch using self-conducting transistors. In particular, it is therefore possible to realize the function of a self-locking switch by means of high-temperature transistors which are self-conducting. ren.
  • the self-locking switch according to the invention has at least one non-linear element, to which a voltage can be applied between two contacts of the non-linear element.
  • the non-linear element is non-conductive between the contacts when the voltage applied between the contacts is less than a characteristic voltage of the non-linear element. Is that between the
  • the non-linear element is electrically conductive.
  • the resistance of the non-linear element is preferably as small as possible and goes to zero.
  • the sign of the characteristic stress is defined as positive.
  • the at least one non-linear element is electrically contacted with one of its contacts with the source contact of the transistor, preferably electrically contacted directly.
  • the non-linear element is thus connected in series with the source-drain path of the transistor.
  • the transistor may be a normally-on transistor or a transistor whose threshold voltage is greater than zero, but whose channel is not completely pinched off at a control voltage of 0 V, so that a negative control voltage is still required to turn the transistor itself into one non-conductive state.
  • the transistor is a self-conducting transistor, the transistor is on its way between see source and drain non-conductive when a voltage between the gate and source is applied, which is smaller than a threshold voltage, which is less than zero in the case of a normally-on transistor, is so negative. If this voltage is greater than the threshold voltage, the transistor between the source and drain is preferably conductive.
  • the characteristic stress of the nonlinear element is greater than or equal to
  • the self-locking switch according to the invention has at least one gate block, which has two contacts and is in electrical contact with a contact with the gate contact of the transistor, preferably in direct electrical contact.
  • the gate block is then in electrical contact with its other contact with that contact of the nonlinear element, preferably directly in electrical contact, which is not in contact with the contact
  • the gate block may have the task, in the freewheeling state, of pulling the gate potential of the transistor to the interface potential of the contact of the non-linear element which is not in contact with the transistor, this block representing the applied control voltage between the gate and the said contact of the non-linear element preferably not influenced.
  • the non-linear block may preferably build up a voltage higher than the threshold voltage of the transistor without current flow.
  • the non-linear block drives that between the gate and source of the transistor voltage in the blocking operating state of Transistor (ie, the voltage between the gate and source of the transistor is smaller than the threshold voltage of the transistor), without going even in the conductive operating state (in which the voltage applied to the non-linear element voltage is greater than the characteristic voltage of the non-linear element) , Only when there is a voltage which is greater than the sum of the threshold voltage of the transistor and the characteristic voltage of the non-linear element between the gate contact and that contact of the non-linear element which is not in contact with the transistor is the transistor able to conduct go over and turn on the switch.
  • the gate block advantageously satisfies at least one.
  • the gate block is to ensure that in the uncontrolled state of the switch, that is, when no voltage is applied between its outer gate contact and its outer source contact and the outer gate potential is in a floating state, the outer gate Potential is drawn to the external source potential.
  • the gate block should not prevent the switch from being externally applied a voltage between the outer gate contact and the outer source contact can be controlled.
  • the circuit according to the invention leads to a switch which has contacts to the outside such as a transistor, ie an external gate contact G *, an external drain contact D * and an external source contact S *.
  • the switch has an external threshold voltage V * th , which is the sum of the threshold voltage of the transistor and the characteristic voltage of the non-linear element.
  • the transistor of the switch is a transistor whose threshold voltage is greater than zero, but which is not completely closed for an applied control voltage of 0 V and therefore requires a negative control voltage for closing
  • V r is the negative voltage required to put the transistor in the off-state condition and the non-linear element characteristic voltage is chosen to be V c # n ii n > -V r .
  • the gate block may include or be a resistor R. This is particularly useful on the assumption that no appreciable current flows through the gate contact of the transistor.
  • the switch is set to the conductive operating state. If V * sat is a saturation voltage of the switch at which the current flowing between the drain and source current does not increase further with increasing gate voltage, then the voltages n * V c , di O > V D * s * > V * sat and the switch behaves resistively, with the resistance of the switch on the path between drain D * and source S * being the sum of the differential flow resistance of the diode or diodes r d i O and the on-resistance of the transistor R FET ,
  • the transistor used in the switch is preferably a high-electron mobility transistor (HEMT).
  • HEMT high-electron mobility transistor
  • this transistor has a semiconductor heterostructure with at least one first and one second semiconductor layer, wherein preferably the first semiconductor layer comprises or consists of AlGaN and the second semiconductor layer comprises or consists of GaN.
  • the transistor of the switch is designed so that it supports the function of the switch in the desired manner. This is particularly advantageous when the nonlinear element is replaced by is formed and / or the gate block has a resistance. In this case, by suitable design of the transistor, the characteristic of the switch, as it appears to the outside, can be adjusted.
  • the material of the semiconductor layers of the transistor can be suitably adjusted, that is, in the case of an AlGaN layer, the aluminum molar content.
  • the thickness of the semiconductor layers of the transistor can be suitably adjusted, that is, in the case of an AlGaN layer, the aluminum molar content.
  • Semiconductor layers particularly preferably the thickness of that semiconductor layer on which the ohmic contacts are housed, so for example AlGaN layer, are set.
  • the adaptation can be carried out without destroying the channel at the location of the gate metallization, as is the case in the prior art, since the transistor in the switch according to the invention does not have to be set in a self-locking state.
  • V c , dio can also be adjusted by the choice of the semiconductor material, for example, the aluminum molar content in an AlGaN semiconductor, and by the thickness of the semiconductor layers, eg, the AlGaN layer so that the characteristic voltage of a diode multiplied by The number of diodes is greater than the negative of the negative threshold voltage V th of the transistor or greater than the negative of a negative voltage V r , which must be applied to put the transistor in a blocking state.
  • an alternative or additional possibility of suitably adapting the transistor of the switch is to place in the semiconductor layer of the transistor carrying the ohmic contacts at the location of the gate contact of the transistor. to etch a depression or a ditch.
  • the metal of the gate contact may be at least partially disposed in the opening in the semiconductor layer, filling the opening or as a layer on a wall surface in the interior of the opening, preferably the semiconductor material directly touching.
  • the corresponding semiconductor layer of the transistor is an AlGaN layer
  • an opening or a trench or a depression is introduced, for example etched, in which the gate contact is accommodated in a corresponding manner.
  • a trench etching of the transistor at the location of the gate metallization in the overall circuit can be realized.
  • the V th of the HEMT can only be adjusted by adjusting the thickness of the AlGaN layer at the gate metallization site.
  • the thickness variation and aluminum mole content change in the AlGaN layer, depending on the location on the wafer, must be considered in the design of the V * th value.
  • the yield on a semiconductor wafer can be set on self-locking switches.
  • a termination layer can be arranged which influences the two-dimensional electron gas at the boundary layer between this semiconductor layer and the other semiconductor layer arranged thereunder.
  • the negative threshold voltage -V t h of the transistor for V t h ⁇ 0 V is directly proportional to a thickness t of the upper semiconductor layer, ie in the case of AlGaN / GaN HEMT the thickness t of the AlGaN layer.
  • the characteristic voltage of the diode V C depends only on the aluminum molar content in the AlGaN layer, so that the threshold voltage of the transistor and the characteristic voltage of the diode can be set largely independent of one another in the switch according to the invention It is not necessary, as in the prior art, to set the threshold voltage of the transistor, for example, through the layer thickness t, such that this threshold voltage becomes greater than 0 V, whereby the channel conductivity drops very sharply can satisfy only the condition that the sum of the characteristic voltages of series-connected diodes is greater than the amount of the threshold voltage of the transistor (if the non-linear element is formed of diodes), the high channel conductivity can be largely retained, so that in an area-efficient way e can be achieved in small flow resistance in the switch.
  • the described method of etching a trench or an opening or depression in the upper semiconductor layer of the transistor makes it possible to set the threshold voltage of the transistor.
  • the thickness t of the barrier layer ie the upper layer on which the ohmic contacts are arranged, is adjusted at the location of the gate metallization such that the characteristic voltage of the nonlinear element is greater than the magnitude of
  • Threshold voltage of the transistor or greater than the Amount of that voltage required to put the transistor, which is not completely blocking when a voltage is applied, into a blocking state.
  • the nonlinear element is formed by n diodes connected in series, it is possible to set n * V c # dio > -V t h or n * V c / d io> -V r by producing such a depression.
  • This method makes it possible to increase the threshold voltage of the transistor independently of the characteristic voltage of the diode, so that the switch for smaller values for n * V C / di o is in the normally-off operating state, without the channel conductivity of the transistor being approximated in the first approximation Be affected.
  • the individual blocks of the described concept ie nonlinear element, transistor and gate block, from FIG. 6, can be interconnected both hybrid and monolithically integrated on a chip.
  • the advantage of the hybrid design is that you can optimize the function of the individual blocks or use optimally fitting components. So you can combine components based on different material systems, such as GaAs, IP, Si, SiGe, Ge, SiC and GaN in a circuit.
  • the switch according to the invention can be configured particularly advantageously as a horizontal power component.
  • Horizontal power devices have a plurality of individual unit cells on a chip. len, also referred to as fingers.
  • a total current through the component is distributed, for example, laterally next to the fingers or vertically above the fingers in a star shape to the individual fingers and correspondingly recombined after flowing through the component and guided to the interface of the component to the outside.
  • Contacts of the same function of the unit cells can therefore be contacted together and can therefore be electrically connected to one another directly.
  • Gate contacts, source contacts and / or drain contacts and / or those contacts of the non-linear element which are not connected to the transistor can be contacted together from the outside.
  • the contacts or fingers can in this case be band-shaped elongated and be arranged side by side parallel to each other.
  • the different functions can be laterally nested.
  • an elementary cell of such a device has a finger of a transistor and a finger of a non-linear element
  • the transistor fingers of several or all of the elementary cells can be contacted together and the diode fingers of several or all elementary cells can be contacted together.
  • the total flow through the component can be distributed here by a lateral or vertical bus to the transistor fingers and be merged together again after flowing through the elec- tronic cell.
  • the fingers or contacts of the individual unit cells can be arranged side by side sorted by functions, so that all contacts of a first function are arranged side by side and all contacts of another function are arranged side by side, but not next to the contacts of the first function. It could thereby be e.g. all transistor fingers may be juxtaposed and all contacts of the nonlinear element.
  • the disadvantage here is that the metal system of the IC technology is burdened with a considerably higher current density and therefore results in a higher parasitic voltage drop.
  • the switch according to the invention can be used particularly advantageously in all clocked voltage converter applications, such as in downwards, upwards, inverting, blocking, single-ended flow, half-bridge flow, half-bridge push-pull, full-bridge gentakt converters and in power factor precursors (PFC).
  • PFC power factor precursors
  • the application areas are located in the consumer, industrial, automotive and aerospace markets.
  • FIG. 1 shows a field-effect transistor as can be used in the switch according to the invention
  • FIG. 2 shows a field-effect transistor as can be used according to the invention, the two-dimensional electron gas being influenced by a gate contact arranged in a depression,
  • FIG. 3 shows a field-effect transistor as can be used in the switch according to the invention, wherein the two-dimensional electron gas is influenced by a doping
  • FIG. 4 shows a schematic transfer characteristic of an HEMT
  • FIG. 5 shows a schematic current-voltage characteristic of an idealized, nonlinear element
  • FIG. 6 shows a block diagram of a switch according to the invention
  • FIG. 7 shows a schematic transfer characteristic of a switch according to the invention
  • FIG. 8 shows a block diagram of a switch according to the invention with diodes as non-linear element and resistor as gate block.
  • FIG. 9 shows a schematic transfer characteristic of the switch shown in FIG. 8,
  • Figure 10 shows a possible arrangement of contacts of a device with a plurality of single cells
  • FIG. 11 shows a further possibility of arrangements of contacts of a component composed of a multiplicity of switches according to the invention.
  • FIG. 1 shows a transistor, as it can be used in the switch according to the invention.
  • a lower semiconductor layer 2 which comprises or consists of GaN
  • an upper semiconductor layer 3 is disposed in contact with the lower semiconductor layer 2 having Al x Gai -x N.
  • the lower semiconductor layer 2 and the upper semiconductor layer 3 are arranged in contact with each other.
  • a two-dimensional electron gas (2DEG) 4 is formed, which forms a conductive channel of the transistor.
  • an end layer 5 which covers the surface of the upper semiconductor layer 3 is arranged on the upper semiconductor layer 3 at the upper side facing away from the lower semiconductor layer.
  • the finishing layer 5 is optional.
  • a source contact 6, a gate contact 7 and a drain contact 8 are arranged on the upper side of the termination layer 5.
  • FIG. 2 shows a further example of a high-electron mobility transistor whose layer construction corresponds to the transistor shown in FIG. 1 and which can be used in the switch according to the invention.
  • no termination layer 5 is provided here.
  • the gate contact 7 is arranged in a recess 9 or opening 9 in the upper semiconductor layer 3, and in this case projects on a wall of the opening 9 and a part of the surface above the semiconductor layer 3.
  • the gate contact 9 contacts the semiconductor material of the upper semiconductor layer 3 directly in the opening and on the surface.
  • the recessed gate contact 7 changes the electrode density in the contact area between the upper semiconductor layer 3 and the lower semiconductor layer 2, thereby changing the channel conductivity of the transistor. This effect can be used to adjust the threshold voltage of the transistor V th to set that the switch provided with the transistor has the desired characteristic, in particular the desired threshold voltage.
  • Figure 3 shows another possible embodiment of the transistor, as it can be used in the switch according to the invention.
  • the construction of the layer system again corresponds to that shown in FIG. 1, but here as well, no termination layer 5 is present, but the contacts 6, 7 and 8 are arranged directly on the upper semiconductor layer 3.
  • a p-doping 10 is introduced into the lower semiconductor layer 2 below the gate contact 7.
  • This doping 10 causes the electron density of the two-dimensional electron gas at the interface between the semiconductor layer 2 and the semiconductor layer 3 to change, so that the channel conductivity changes.
  • the threshold voltage of the transistor can also be influenced here and adjusted so that the switch equipped with the transistor has the desired characteristic, in particular the desired threshold voltage.
  • FIG. 4 shows a schematic transfer line of a high electron mobility transistor (HEMT, high electron mobility transistor).
  • HEMT high electron mobility transistor
  • FIG. 5 now shows a current-voltage characteristic of a nonlinear element, as can be used in the switch according to the invention.
  • the course of the characteristic curve is idealized here. On the vertical axis in this case a current through the non-linear element is applied, while on the horizontal
  • Axis applied to the non-linear element voltage is applied.
  • the current flow through the nonlinear element is equal to zero for voltages applied to the nonlinear element that are smaller than a characteristic voltage of the nonlinear element V c , n in-once, however, as soon as the applied voltage reaches the characteristic voltage V c , n ii n , a current flows through the nonlinear ele- ment.
  • the current flows with a resistance of zero.
  • real non-linear elements will have a current flow with a certain resistance, so that the distance of the characteristic shown vertically here would in reality be inclined with a positive slope.
  • FIG. 6 shows a block diagram of an inventive The switch 11 shown has a high-electron mobility transistor 12 and a nonlinear element 13 and a gate block 14.
  • the transistor 12 has a drain contact 15, a gate contact 16 and a source contact 17. From the outside, the switch 11 can be contacted via an outer drain contact 18, an outer gate contact 19 and an outer gate contact 20 , The outer drain contact 18 corresponds to the drain contact of the transistor 15. Between the outer source
  • the non-linear element 13 is arranged so that current flows from the source contact 17 of the transistor through the non-linear block 13 to the external source contact 20.
  • the outer gate contact 19 is electrically directly in contact with the gate contact 16 of the transistor.
  • the gate block 14 is arranged between the outer source contact 20 and the outer gate contact 19, the gate block 14 is arranged. It can be seen that the non-linear element 13 is connected in series with the path between the drain contact 15 of the transistor and the source contact 17 of the transistor.
  • the nonlinear element 13 is also connected in series with the path between gate contact 16 and source contact 17 of the transistor.
  • the non-linear element 13 has a
  • a characteristic voltage of the nonlinear E element 13 is greater than the magnitude of a (negative) threshold voltage V th of the transistor or greater than the magnitude of a negative voltage V r to be applied to the transistor so that it transitions to a fully-off state when the transistor at a Control voltage of zero volts still passes, but the threshold voltage is greater than zero.
  • FIG. 7 shows a schematic transfer characteristic of the switch 11, as shown in FIG.
  • the switch 11 has an effective threshold voltage V * th which appears outwardly.
  • V * th the current intensity of the current of the switch 11 flowing into the outer drain contact 18 is plotted on the vertical axis.
  • the voltage applied between the outer gate contact 19 and the outer source contact 20 is applied to the control voltage of the switch.
  • Control voltage is less than the effective threshold voltage of the switch V * th , the switch is in the non-conductive state.
  • a current begins to flow between the outer drain contact 18 and the outer source contact 20 which initially runs substantially linear.
  • V sat the current flow I D no longer increases with a further increase in voltage.
  • Threshold voltage V * th is greater than zero. As a result, the switch 11 is at a control voltage of zero in the blocking state. The switch 11 is thus self-locking.
  • FIG. 8 shows another possible embodiment of the switch 11 according to the invention.
  • the same elements and their interconnection correspond to the elements as shown in FIG.
  • the nonlinear element 13 is now configured as n series-connected diodes 13a.
  • the gate block 14 is configured as a resistor R 14.
  • R resistor
  • FIG. 9 shows a schematic current-voltage characteristic of the switch 11 shown in FIG. 8.
  • the drain current I D which flows into the drain contact 18 of the switch, is plotted on the vertical axis.
  • a voltage applied between drain contact 18 and outer source contact 20 is applied. It can be seen that below a voltage corresponding to the characteristic diode voltage multiplied by the number of diodes connected in series, no current flows into the drain contact 18.
  • n * V C / d io At higher voltage between drain contact 18 and source contact 20 as n * V C / d io, a current begins to flow, which increases substantially linearly with increasing voltage V ⁇ a * s * i ⁇ i.
  • the slope in the linear range corresponds to the sum of the resistance of the transistor and the resistance of the diodes.
  • the resistance of the switch r is thus just the internal resistance of the diodes plus the internal resistance of the field effect transistor.
  • FIG. 10 shows an example of a component having a plurality of switches according to the invention, which are used as unit cells for a horizontal power supply. element are joined together.
  • a circuit diagram of an elementary cell is shown in the right part of the figure and on the left side a plan view of a contacting surface in which transistor contacts and drain contacts of a plurality of unit cells are arranged side by side.
  • Each unit cell here has a transistor 12 and a diode 13 as a nonlinear element 13.
  • Each unit cell also has a transistor contact 18, here corresponding to the drain contact 18, and an external source contact 20, which is a contact of the diode 13.
  • the plurality of transistor contacts 18 is now, as seen in the left partial image, arranged side by side.
  • the multiplicity of transistor contacts 18a, 18b, 18c are elongated and arranged parallel to one another next to one another.
  • the outer source contacts or diode contacts 20a, 20b, 20c are elongated and arranged side by side parallel to each other.
  • all the transistor contacts 18a, 18b, 18c are arranged in the upper half of the contacting surface 21, and all the diode contacts 20a, 20b, 20c in the lower half.
  • the contacting surface 21 may preferably be flat.
  • FIG. 11 shows a further horizontal power component with a multiplicity of unit cells, wherein in turn each unit cell is a switch 11 according to the invention.
  • a schematic electrical circuit is shown in the right-hand part of the drawing and a plan view of a contacting surface 21 in the left-hand part.
  • the power component is contacted via common contacts 22 as a common transistor contact and 23 as a common diode contact. It can be seen in the left-hand part of the drawing that in turn here the transistor contacts 18a, 18b, 18c and the diode contacts 20a, 20b, 20c are oblong are formed.
  • both transistor contacts 18 and diode contacts 20 are arranged side by side parallel to each other and each extend over the entire width of the contacting surface 21.
  • Die Transistor Level. Drain contacts 18a, 18b, 18c and the diode contacts or external source contacts 20a, 20b, 20c are now interleaved such that at least one source contact is located next to a transistor contact and at least adjacent to each external source contact 20 a transistor contact 18 is located.
  • the embodiment shown in FIG. 11 is preferred over that shown in FIG. 10, since here the metal system of the IC technology is loaded with low current densities and therefore has a lower parasitic voltage drop.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

L'invention concerne un interrupteur autobloquant comportant au moins un transistor (12) qui est conducteur lorsqu'il est hors tension. L'interrupteur autobloquant contient au moins un transistor à déplétion ainsi qu'au moins un élément non linéaire (13) qui présente deux contacts et qui n'est pas conducteur lorsqu'une tension inférieure à une tension caractéristique est présente entre les contacts, et qui est conducteur lorsqu'une tension supérieure ou égale à la tension caractéristique est présente entre les contacts, le signe de la tension caractéristique étant défini comme positif. L'élément non linéaire est en contact électrique avec le contact source du transistor par un de ses contacts.
EP09799288A 2009-01-07 2009-12-23 Interrupteur autobloquant Withdrawn EP2380198A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102009004254 2009-01-07
PCT/EP2009/009285 WO2010081530A1 (fr) 2009-01-07 2009-12-23 Interrupteur autobloquant

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EP2380198A1 true EP2380198A1 (fr) 2011-10-26

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WO (1) WO2010081530A1 (fr)

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WO2012055570A1 (fr) * 2010-10-28 2012-05-03 Microgan Gmbh Circuit à diode
EP2608269A1 (fr) * 2011-12-23 2013-06-26 Imec Transistor à puits quantique, procédé de fabrication de celui-ci et son utilisation
JP6111821B2 (ja) * 2013-04-25 2017-04-12 三菱電機株式会社 電界効果トランジスタ
JP6347685B2 (ja) 2014-07-08 2018-06-27 ルネサスエレクトロニクス株式会社 半導体装置

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US7382001B2 (en) * 2004-01-23 2008-06-03 International Rectifier Corporation Enhancement mode III-nitride FET
JP2006100645A (ja) * 2004-09-30 2006-04-13 Furukawa Electric Co Ltd:The ＧａＮ系半導体集積回路
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