EP2376930A1 - Procédé d'essai de plaquettes à circuit imprimé - Google Patents

Procédé d'essai de plaquettes à circuit imprimé

Info

Publication number
EP2376930A1
EP2376930A1 EP10700178A EP10700178A EP2376930A1 EP 2376930 A1 EP2376930 A1 EP 2376930A1 EP 10700178 A EP10700178 A EP 10700178A EP 10700178 A EP10700178 A EP 10700178A EP 2376930 A1 EP2376930 A1 EP 2376930A1
Authority
EP
European Patent Office
Prior art keywords
test
circuit board
printed circuit
tested
contact elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP10700178A
Other languages
German (de)
English (en)
Inventor
Gilbert Volpert
Martin Faulhaber
Victor Romanov
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ASM Assembly Systems Switzerland GmbH
Original Assignee
DTG International GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by DTG International GmbH filed Critical DTG International GmbH
Publication of EP2376930A1 publication Critical patent/EP2376930A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G01R31/2812—Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2805—Bare printed circuit boards
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
    • G01R31/2808—Holding, conveying or contacting devices, e.g. test adapters, edge connectors, extender boards

Definitions

  • the present invention relates to a method of testing printed circuit boards with a tester.
  • the present invention relates to a method for testing bare boards for breaks and short circuits using continuity measurements.
  • continuous measurements is meant measurements in which an electrical resistance between two contact points of one or more tracks is measured by contacting the two contact points and applying a sense current or voltage and measuring the resulting voltage or current .
  • the contact points of a printed circuit trace are referred to below as printed circuit board test points.
  • Interruptions of a printed circuit trace are detected by contacting two printed circuit board test points of a printed conductor and detecting a predetermined minimum resistance.
  • Short circuits between two adjacent interconnects are detected by each contacting a circuit board test point of one of the two interconnects and measuring a resistance that is less than a predetermined threshold value.
  • Testers for testing printed circuit boards can basically be divided into two groups, the group of the flying test testers and the group of parallel testers.
  • the parallel testers are test devices which simultaneously contact all or at least most of the contact points of a printed circuit board to be tested by means of an adapter.
  • Finger testers are test devices for testing bare or populated printed circuit boards, which scan the individual contact points sequentially with two or more test fingers.
  • a finger tester is described in EP 0 468 153 A1 and a method for testing printed circuit boards by means of a finger tester is described in EP 0 853 242 A1.
  • Parallel testers are, for example, from US Pat. No. 3,564,408 or US Pat. No. 4,417,204, DE 32 40 916 C2, DE 33 40 180 C1, German Utility Model DE 88 06 064 U1, EP 0 875 767 A2, WO 02/31516 or US Pat EP 1 322 967 B1, EP 1 083 434 A2 and US 6,445,173 B1, respectively.
  • a test device which has on each side to be tested of the test specimen at least two coplanar needle boards, which are mutually movable.
  • These needle boards are provided with a plurality of probes, with each of which a contact point of a conductor track to be tested are contacted can.
  • the two needle boards can be moved with respect to the circuit board so that certain contact points of a conductor can be contacted simultaneously, with a plurality of contact points of the needle boards also several tracks are contacted simultaneously.
  • the contact needles of each needle board are individually operable, so that only selected contact needles a contact board with the respective circuit board to be tested in contact.
  • a test apparatus for testing circuit boards having a plurality of contact elements arranged on a support member and selectively movable on the support member towards a circuit board to be tested.
  • the individual contact elements can therefore be controlled individually.
  • the carrier elements are displaceable in a plane parallel to the test printed circuit board, so that each contact point of the printed circuit board to be tested can be contacted by at least one contact element.
  • the two testers discussed above combine the benefits of the parallel tester and the finger tester. They have not enforced in practice, however, since the individual control of the individual contact elements is very complex. Such a device is on the one hand expensive and on the other prone to error and therefore maintenance-intensive. Furthermore, due to the individual controllability, the individual contact elements are arranged at a relatively large distance from each other, so that these devices are only of limited use for current printed circuit boards.
  • test devices emerge, with which the surfaces of printed circuit boards are traversed by means of contact brushes, wherein the contact brushes produce electrical contacts to the individual contact points.
  • electrical quantities are measured and compared with predefined values. This allows the elimination of certain contact points for a subsequent detailed electrical examination of the circuit board to be tested.
  • EP 0 831 332 A1 shows devices and methods, with which in a parallel tester to be tested circuit board is aligned with respect to the adapter, in each case a relative movement between the circuit board to be tested and the adapter is performed.
  • the adjusting devices for carrying out this adjustment movement can be arranged completely within the adapter body (EP 0 831 332 A1) or else outside the adapter body so that the entire adapter is moved (US Pat. No. 4,820,975).
  • DE 199 57 286 A1 describes a method in which different areas of a printed circuit board are aligned individually with respect to an adapter of a parallel tester.
  • an adapter which is specific for the printed circuit board is used, whose contact points are arranged in the grid of the printed circuit board test points of the printed circuit board to be tested.
  • DE 143 728 A1 discloses a method in which a printed circuit board is first tested by means of a parallel tester. Board test points that can not be contacted are measured with a device independent of the parallel tester. In general, this independent device is a finger tester.
  • the present invention has for its object to provide a method and an apparatus for testing printed circuit boards, with which no special adaptation of the device to the respective type of printed circuit boards to be tested, such as by an adapter is necessary and on the other hand fast measuring sen of at least most of the tracks on interruptions and / or short circuits is possible.
  • a test apparatus which has a test arrangement for contacting printed circuit board test points of a circuit board to be tested, the test arrangement having test contact elements in a predetermined regular grid.
  • the following steps are carried out: a) pressing the test arrangement to the circuit board to be tested in a first test position with respect to the printed circuit board to be tested, so that several circuit board test points are in contact with at least one test contact element, b) measuring several interconnects for interruptions and / or short circuit by means of continuity measurements, c) shifting the test arrangement with respect to the printed circuit board to be tested into a further test position, in which at least one printed circuit board test point of a printed circuit is in contact with at least one test contact element, which has not yet been fully monitored and / or short-circuited d) measuring further interconnects for interruptions and / or short circuits by means of continuity measurements; e) repeating steps c) and d) until at least the majority of the interconnects of the circuit
  • test arrangement with regularly arranged test contact elements is used for different types of printed circuit boards. This is contacted with grid arranged PCB test points, as they are common in current printed circuit boards. It is thus not necessary to make a separate test arrangement for each type of printed circuit board. This test arrangement can therefore also be referred to as a "universal adapter".
  • the method according to the invention is particularly well suited for testing short-circuits between adjacent interconnects, since these can be completely measured in most circuit boards with few displacements.
  • test arrangement with respect to the circuit board to be tested in the plane parallel to the test circuit board in two orthogonal directions by ⁇ half the distance between two adjacent test contact elements is movable.
  • test contact elements are preferably arranged rigidly on the test arrangement, as a result of which the test arrangement can be formed simply and inexpensively with contact elements of the required density.
  • a rigid arrangement is understood to mean an arrangement of the test contact elements in which the individual test contact element is not movable with respect to the entire test arrangement. However, this does not mean that the individual test contact elements must be formed integrally with the test arrangement.
  • a rigid test arrangement can For example, as a test contact elements have separately formed test needles, which are fixed by means of guide plates in position on a basic grid.
  • test needles can all be arranged parallel to one another in an embodiment of the test contact elements by means of test needles.
  • conventional parallel testers there are adapters with test probes, which are usually tilted.
  • the parallel arrangement of the probes is advantageous over the skew because all the probes are arranged with their end facing the printed circuit board in a plane so that they simultaneously contact the printed circuit board to be tested and only a relatively low contact pressure is necessary to ensure that all probes are in contact with the printed circuit board to be tested.
  • test probes are tilted, which as a rule are inclined at different levels, the less skewed test probes must be compressed more strongly, so that the more obliquely set test probes also come into contact with the circuit board to be tested. As a result, much higher contact forces are generated. Furthermore, the inclination reduces the distance between adjacent test probes. Since the test needles are arranged parallel to each other, it is also possible to use with such a high density of test probes which have a resilient portion, e.g. in the form of a coil spring.
  • the circuit board can be subjected to another measurement with a finger tester. In this case, only a few printed circuit board test points must be contacted, so that this measurement process can be carried out very quickly.
  • the entire measurement, including stepwise parallel scanning of the printed circuit board under test with the test assembly and retiming with the finger tester, is much faster than completely scanning and measuring the printed circuit board under test in a finger tester.
  • the method according to the invention thus combines the universal applicability of the test device, as known from the finger tester, with an approximately as fast throughput as in a parallel tester.
  • the invention will be explained in more detail by way of example with reference to the drawings.
  • the drawings show in:
  • FIG. 1 shows schematically the structure of a testing device according to the invention
  • FIG. 2 shows a detail of the arrangement of the test contact elements of the test apparatus from FIG. 1, FIG.
  • FIG. 3 schematically shows a region of a contacting unit of the testing device shown in FIG. 1, FIG.
  • 5A, 5B show the dependence of the number of detected board test points on the number of measuring operations or the displacements for different densities of the test contact elements in a respective diagram
  • Fig. 8 shows the proportion of non-feasible continuity measurements for open (interruptions) in certain printed circuit boards for a predetermined number of shifts in a table.
  • FIG. 1 schematically shows the construction of a test device 1 according to the invention for the one-sided testing of printed circuit boards 2.
  • This test device has a main body 3, in which a part of the evaluation is located, and which is formed on its surface with a basic grid 4. A section of the basic grid is shown in FIG. 2. Modules for the formation of this basic grid are disclosed in the German patent application DE 10 2006 059 429. This patent application is hereby incorporated by reference.
  • a contacting unit 6 is arranged, on which there is a printed circuit board 2 to be tested.
  • the basic grid 4 has contact points 8, which are circular.
  • the grid in which the contact points 8 are arranged is composed of two mutually restricted square grids.
  • the contact points 8 are each 1, 27 mm apart, with a contact point 8 is arranged at each corner of a square.
  • a contact point of the other square grid is arranged.
  • These two rasters are thus offset from each other by half the distance between two adjacent contact points of a square grid. This half distance is 0.635 mm (Fig. 2).
  • the density of the contact points of this grid is about 124 contact points per cm 2 .
  • This grid can also be described as a square grid, wherein the side edges of the squares in each case inclined by 45 ° relative to the vertical or horizontal in Fig. 2. In this illustration, the distance between two adjacent contact points is 0.898 mm.
  • the full grid cassette 5 has spring contact pins 9.
  • the spring contact pins 9 are arranged in the grid of the basic grid 4, so that each contact point 8 of the basic raster 4 is assigned in each case a spring contact pin 9.
  • the spring contact pins 9 are arranged parallel to each other in the full grid cassette 5.
  • the contacting unit 6 is constructed similar to conventional adapters and has test probes 10 which each lead from a spring contact pin 9 of the full grid cassette 5 upwards in the direction of the circuit board 2 to be tested and contact them.
  • Conventional adapters are designed so that they map the grid of the basic grid or the full grid cassette by tilting the test probes on the arrangement of the board test points of the printed circuit board to be tested. It will Thus, the arrangement of the board test points of the printed circuit board to be tested adapted to the basic grid.
  • the test needles 10 of the contacting unit 6 like the spring contact pins 9 of the full grid cassette 5, are arranged in a regular grid, namely in the grid of the basic grid 4. They are all aligned parallel to each other. This contacting unit 6 is thus not an adapter. When placing a printed circuit board 2 to be tested on the contacting unit 6, not all printed circuit board test points of the printed circuit board to be tested are contacted simultaneously.
  • the contacting unit 6 has a plurality of guide plates 11, which are provided with holes 7/1, which are each arranged in the grid of the basic grid. Through these holes, the test probes extend 10.
  • the guide plates 11 are held at the edge by resilient columns 12 at a distance.
  • One of the guide plates 11, preferably the one which delimits the contacting unit 6 on the conductor plate side, is designed as a needle guide plate 13.
  • Adjacent to the needle guide plate 13, a positioning plate 14 is arranged, whose bores 7/2 have a larger diameter than the bores of the remaining guide plates 11, so that the test needles 10 are arranged in the positioning plate 14 with considerable play.
  • an adjusting or displacement device 15 is fixed, which has an upwardly projecting adjusting pin 16, with respect to the positioning plate 14 a predetermined path of, for example, 0.9 mm in one direction by means of an actuator 15 located in the actuator displaceable is.
  • This adjusting pin 16 engages positively in a positioning hole 17 of the needle guide plate 13 a.
  • the contacting unit 6 has a plurality of such adjusting means 15 for independently moving the positioning plate 14 with respect to the needle guide plate 13 in two orthogonal directions (X direction and Y direction).
  • PCB receiving pins 18 are fixed, which extend through corresponding holes 19 in the needle guide plate 13 in the direction of the circuit board 2 and in positioning holes 20 in the circuit board 2 form- intervene conclusively.
  • the holes 19 in the needle guide plate 13 are significantly larger than the diameter of the board receiving pins 18, so that the relative movement between the needle guide plate 13 and the positioning plate 14 is not limited thereby.
  • the positioning plate 14 and the board receiving pins 18 thus form a positioning device for the printed circuit board 2.
  • the relative movement between the needle guide plate 13 and the positioning plate 14 is thus also a relative movement between the needle guide plate 13 and the printed circuit board 2.
  • circuit board receiving pins 18 are provided so that the circuit board 2 is uniquely positioned with respect to the positioning board 14.
  • the actuator of the adjusting device or displacement device 15 is a piezoelectric displacement unit, as is known from EP 0 831 332 A1. This document is referred to with reference to the Piezo Positioner.
  • This piezoverstelltechnik has two sets of piezoelectric element rods which are mutually orthogonal. The piezoelectric element rods are subjected to a voltage so that they stretch or contract. The voltages applied to a pair of piezoelectric element rods are oppositely poled, so that the piezoelectric element rods bend due to the opposite length contraction or longitudinal expansion and execute a pivoting movement.
  • Such an adjustment unit can be provided within the contacting unit 6 for moving the needle guide plate 13 or outside the contacting unit 6 for moving the unit comprising the main body 3, the full-screen cassette 5 and the contacting unit 6. It is also possible to move the circuit board 2 directly by means of the adjusting unit.
  • Another actuator may be formed of a motor with reduction gear, which drives an eccentric.
  • the motor may be a stepper motor or a servo motor with feedback, wherein by means of a motion sensor, the displacement is detected and fed back to the drive of the motor accordingly.
  • test device has been described above with reference to a device for one-sided testing of a printed circuit board.
  • devices for double-sided PCB testing are common today.
  • the unit comprising the main body 3, the full grid cassette 5 and the contacting unit 6 is to be provided twice, once below and once above the printed circuit board to be tested, each aligned with the contacting unit 6 towards the printed circuit board.
  • These two units are arranged between a press, so that the contacting units 6 are pressed from above and from below against the printed circuit board.
  • a two-sided tester adjustment may be provided for positioning the needle guide plates of both contacting.
  • adjusting means are provided only for positioning a needle guide plate and a further adjusting unit for positioning the circuit board. It is expedient to arrange the adjusting device such that both contacting units can be moved independently of one another with respect to the printed circuit board to be tested.
  • the method for inspecting bare circuit boards will be explained with reference to FIG. 6.
  • step S1 The process starts with step S1.
  • step S2 the test arrangement is pressed against the circuit board 2 to be tested.
  • the contacting unit 6 forms the test arrangement.
  • the two contacting units 6 for testing the top and the bottom of the printed circuit board to be tested represent the test arrangement.
  • Such a test arrangement is thus characterized by test contact elements arranged in a regular grid and with respect to the test contact elements Circuit board are movable.
  • the test needles 10 form the test contact elements.
  • step S3 conductor tracks and conductor track sections whose printed circuit board test points arranged at the respective ends of the conductor tracks or printed conductor sections are contacted by a test contact element are checked for interruption by means of a continuity measurement. Adjacent printed conductors, of which in each case one printed circuit test point is contacted with a test contact element, are tested for a short circuit by means of a continuity measurement.
  • step S4 it is checked whether a sufficient number of traces have been tested for open and short.
  • step S5 in which the test arrangement is moved with respect to the circuit board to be tested. If the printed circuit board is tested on both sides, then preferably a part of the test arrangement which contacts one side of the printed circuit board is displaced independently of the part of the test arrangement which contacts the other side of the printed circuit board. The displacement is carried out in such a way that conductor tracks and conductor track sections, which have not yet been tested, are contacted at their printed circuit board test points formed at the end regions by means of test contact elements, so that these further Tracks and trace sections can be tested for open circuit and / or short circuit. The measurement takes place again in step S3. Thereafter, it is again checked whether a sufficient number of traces has been tested (step S4).
  • a grid of at least about 100 test contact elements per cm 2 and in particular the grid shown in FIG. 2 is sufficient for the printed circuit test points of all printed conductors to be contacted so that the printed circuit test points of a printed circuit trace in a specific test arrangement are contacted simultaneously and the conductor track or the corresponding conductor track section can be measured for interruption.
  • the circuit board probes which are normally formed as vias or pads, often have a size greater than the distance between two adjacent test contact elements, so that such a circuit board test point is contacted in each test position of the test device. and a further circuit board test point of this conductor, which is designed as a small pad field, can be selectively contacted and the large board test point is also reliably contacted.
  • step S4 If a printed circuit board is tested in which all conductor tracks can be reliably scanned with the test arrangement, then the number of conductor tracks is preferably determined as sufficient number of conductor tracks in step S4, so that the circuit board is completely tested when steps S3, S4 and S5 are repeated is. The method then ends with step S6.
  • the determination of a displacement path is repeated until all or at least a majority of the pairs of adjacent interconnects have been tested for a short circuit.
  • each test position When measuring for interruptions, in each test position it is checked which printed conductor sections are contacted at their end points. These trace sections can then be tested by means of a continuity measurement.
  • the already tested track section will be noted.
  • the displacement path is determined in such a way that a conductor track section, which has not yet been tested, is contacted after being displaced at its end points. Preferably, the displacement is kept as small as possible.
  • both pairs of contacted adjacent ones become Tracks as well as already contacted trace sections noted.
  • the displacement path is preferably optimized on conductor track sections, since this almost always results in complete detection of potential short circuits. But it is also possible to determine the displacement path alternately to conductor track sections and pairs of adjacent tracks.
  • the conductor track 21 a has pad fields 22a, 22b as printed circuit board test points.
  • the pad fields 22a, 22b are square, with the pad field 22a having an edge length of 1 mm and the plurality of pad fields 22b having an edge length of 0.1 mm. Since the pad fields 22b are significantly smaller than the pitch L (0.9 mm) between two adjacent test contact elements, it is not possible to contact all the small pad fields 22b in pairs. This is not necessary, because to test the conductor 21 a, it is sufficient if each of the small pad fields 22 b once contacted in pairs simultaneously with the large pad field 22 a, so that each running between these two pad fields track section can be tested for interruption.
  • the test arrangement with a test contact element can be precisely aligned with one of the small pad fields 22b and the size of the large pad field 22a ensures that one or more test contact elements be in contact with this pad field 22a.
  • all traces having at least a board pad as a square pad field with the edge length of the pitch of the test set can be fully tested for break.
  • square pad fields are common to a minimum edge length of 0.05 mm. There are also often square pads with an edge length of 0.1 mm.
  • interconnects which are connected to such small pad fields are usually also connected to a larger pad field with a edge length of at least 1 mm and / or a through-connection.
  • Vias typically have a metallization ring 0.5 to 1 mm wide, so that the vias are normally contacted simultaneously with multiple test contact elements of the test device, and thus paired with any of the other board probes connected to the via Allow track.
  • the conductor 21 c in Fig. 7 connects two pad fields 22 d with an edge length of 0.1 mm. These two pad fields are not arranged in the grid of the test arrangement. The two pad fields 22d of this conductor 21 c can not be contacted simultaneously with the test arrangement, whereby the conductor 21 c can not be checked for interruption.
  • a threshold must be used in step S4 for the sufficient number of traces tested that is less than the number of non-testable boards.
  • a threshold of 5% to 10% of non-testable interconnects can be met with respect to all interconnects.
  • step S4 If it is thus determined in step S4 that a sufficient number of printed conductors have been tested, not all printed conductors having been tested, then the non-tested printed conductors are remeasured in step S7 by means of a further measuring method.
  • the circuit board is checked in step S7 with a finger tester. Since the incorrectly scannable interconnects are usually very short and have only a few printed circuit board test points, the remeasurement of these interconnects can be performed very quickly by means of a finger tester. Calculations have shown that with such a test arrangement (pitch about 0.9 mm) in today's unpopulated printed circuit boards about 20 to 30 shifts are necessary to test all tracks fully for open circuit and short circuit. There are few printed circuit boards that can not be completely scanned. These must then be measured by means of a finger tester.
  • a test array with test contact elements uses a density of at least 100 test contact elements per square centimeter, a plurality of board test points are contacted simultaneously by a plurality of test contact elements or probes 10. This makes it possible to check the correct positioning of the test arrangement on the printed circuit board by checking, at certain board test points, which are to be contacted by at least two test contact elements, between these two test contact elements. in each case via the circuit board test point an electrical contact has been made. If this test is performed at several board test points, if a connection is made between the adjacent test contact elements at all of these board test points, it can be concluded that the test array is in the desired position on the board.
  • Fig. 4 shows a table in which the information on printed circuit boards for which the calculation has been carried out is included.
  • the graphs of Figs. 5A and 5B show the percentage of scanned circuit board test points of the traces in relation to the number of displacements and measurements.
  • the calculations according to FIG. 5A are based on the contact arrangement shown in FIGS. 1 and 2.
  • the calculations according to FIG. 5B were carried out with a twice as high density of the contact arrangement compared to the embodiment shown in FIGS. 1 and 2.
  • Only a single printed circuit board (type no. 09102300) could not be contacted with a number of 20 to 30 shifts in all printed circuit board test points.
  • all board test points can be contacted.
  • printed conductors must additionally be provided e.g. be measured by means of a finger tester for interruptions.
  • the proportion is between 6.8% and 55.7%. Values of up to about 30% are very advantageous because such printed circuit boards can usually be tested for short circuits with the method according to the invention and, for the most part, for undercuts, so that the night soldering in a finger tester can be carried out very quickly.
  • the number of shifts must be increased or a higher density test arrangement of the test contact elements used.
  • FIGS. 5A, 5B and 8 show that the method according to the invention is very efficient for a large number of printed circuit boards, permits rapid checking for interruptions and short circuits, without the need to create individual adapters for the individual types of printed circuit board.
  • a test arrangement is used whose test contact elements are provided with a density of at least 100 per cm 2 .
  • the test arrangement may also be defined by the pitch of adjacent test contact elements, which in the above embodiment is about 0.9 mm.
  • a reduction in the mesh dimension to a maximum of 0.8 mm, 0.7 mm, 0.6 mm or 0.5 mm corresponds to an increase in the density of the contact elements and a corresponding reduction in the number of displacements, in order to ensure complete contacting of a to achieve testing PCB.
  • a grid dimension of approximately 0.9 mm is completely sufficient to ensure complete or almost complete contacting of the printed conductors.
  • the test apparatus comprises a full grid cassette and a contacting unit. Since the test probes of the contacting unit 6 are all arranged parallel to one another, it is also possible to use spring contact pins in the contacting unit for contacting the printed circuit board instead of straight-line, wire-shaped test needles.
  • Such spring contact pins are, for example helically wound from a wire spring contact elements having with respect to the helical winding centrally arranged ends. It is sufficient if the helical winding extends only over a part of the length of the spring contact pin and is preferably arranged in the central region, so that the rectilinear ends of the spring contact pin can be guided exactly by means of the guide plates.
  • a contacting unit equipped with such spring contact pins thus also includes the function of the full-screen cassette, which can then be omitted.
  • a universal testing device and a universal testing method are thus created whose throughput of printed circuit boards to be tested is somewhat smaller than when testing with a conventional adapter-based parallel tester, but which is nevertheless considerably higher than with a conventional fingertester ,
  • the residence time of a printed circuit board to be tested in the parallel tester according to the invention is about 10 to 30 seconds. This is 5 to 10 times longer than in a conventional parallel tester but about 10 times faster than in a conventional finger tester.
  • the method according to the invention is particularly efficient when testing short-circuits, since short circuits can be detected completely with few displacements ( ⁇ 10) in almost all printed circuit boards.
  • All circuit board test points, the one Have diameter or an edge length in the size of the grid spacing I of the test arrangement are contacted in any position of the test arrangement on the circuit board. This means that all interconnects connected to at least one such board test point are contacted in any position of the test arrangement. This usually applies to a large part of the interconnects, so that in the first test position already many pairs of adjacent interconnects are contacted simultaneously. Short circuits can thus almost always be recorded completely with a few shifts. Therefore, it may also make sense to use the inventive method only for testing short circuits on certain printed circuit boards and then to measure interruptions by means of a finger tester.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

L'invention concerne un procédé d'essai de plaquettes à circuit imprimé, mettant en oeuvre un dispositif d'essai présentant un agencement pour un essai, permettant la mise en contact de points de test d'une plaquette à circuit imprimé à tester. L'agencement pour essai présente des éléments de contact test sous forme d'une grille régulière, prédéterminée. Le procédé comprend les étapes suivantes : a) application par pression de l'agencement d'essai sur la plaquette à circuit imprimé à tester, dans une première position d'essai, ou de la plaquette à circuit imprimé à tester, de façon que plusieurs points test de la plaquette à circuit imprimé viennent en contact avec au moins un élément de contact test; b) mesure de plusieurs pistes conductrices, relative à des coupures et court-circuit, au moyen de mesures de continuité; c) déplacement de l'agencement pour essai, ou de la plaquette à circuit imprimé à tester, en une autre position d'essai, dans laquelle au moins un point test de la plaquette à circuit imprimé d'une piste conductrice vient en contact avec au moins un élément de contact test, qui au préalable, n'a pas été encore complètement mesuré quant aux coupures et court-circuit; e) répétition des étapes c) et d) jusqu'à ce qu'au moins la pluralité des pistes conductrices de la plaquette à circuit imprimé à tester aient été mesurés. On utilise pour ce procédé un agencement d'essai dont les éléments de contact test sont disposés avec une densité d'au moins 100 points de contact par centimètre carré.
EP10700178A 2009-01-14 2010-01-13 Procédé d'essai de plaquettes à circuit imprimé Withdrawn EP2376930A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102009004555A DE102009004555A1 (de) 2009-01-14 2009-01-14 Verfahren zum Prüfen von Leiterplatten
PCT/EP2010/050361 WO2010081834A1 (fr) 2009-01-14 2010-01-13 Procédé d'essai de plaquettes à circuit imprimé

Publications (1)

Publication Number Publication Date
EP2376930A1 true EP2376930A1 (fr) 2011-10-19

Family

ID=42109863

Family Applications (1)

Application Number Title Priority Date Filing Date
EP10700178A Withdrawn EP2376930A1 (fr) 2009-01-14 2010-01-13 Procédé d'essai de plaquettes à circuit imprimé

Country Status (9)

Country Link
US (1) US20110273203A1 (fr)
EP (1) EP2376930A1 (fr)
JP (1) JP2012515339A (fr)
KR (1) KR101337911B1 (fr)
CN (1) CN102282475A (fr)
BR (1) BRPI1007227A2 (fr)
DE (1) DE102009004555A1 (fr)
TW (1) TW201037328A (fr)
WO (1) WO2010081834A1 (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011056371B4 (de) 2011-12-13 2014-01-09 abele rößler technologies GmbH Vorrichtung zur Überprüfung von Leiterstrukturen
CN103267908A (zh) * 2013-04-22 2013-08-28 高德（无锡）电子有限公司 一种双排版印刷线路板的测试工艺
CN103344905B (zh) * 2013-06-18 2016-02-10 大族激光科技产业集团股份有限公司 运动针床测试机及测试方法
US9274166B2 (en) 2013-08-26 2016-03-01 Fujitsu Limited Pin verification device and method
CN104569780A (zh) * 2013-10-12 2015-04-29 深圳市爱德特科技有限公司 一种基于fpga的测试装置
CN105161037B (zh) * 2015-08-20 2017-12-22 京东方科技集团股份有限公司 位置校准方法、测试电路板、样本面板和位置校准装置
CN105425094B (zh) * 2015-11-24 2018-04-27 深圳怡化电脑股份有限公司 一种pcba短路点检测方法及装置
CN106872878A (zh) * 2017-02-21 2017-06-20 济南浪潮高新科技投资发展有限公司 一种pcb中自动检测电气连接的方法及系统
CN109917270A (zh) * 2019-01-31 2019-06-21 国核自仪系统工程有限公司 仪控系统的板卡的测试数据的分析装置、方法及仪控系统
US11818842B1 (en) * 2020-03-06 2023-11-14 Amazon Technologies, Inc. Configurable circuit board for abstracting third-party controls
CN111707921B (zh) * 2020-07-23 2024-08-27 苏州朗之睿电子科技有限公司 一种测试精准的半导体器件用测试座
CN113325295B (zh) * 2021-05-13 2022-07-19 江苏普诺威电子股份有限公司 平面埋容基板微短路的可靠性测试方法
CN113539349B (zh) * 2021-07-23 2024-05-28 曙光信息产业股份有限公司 一种测试基板、llcr测量方法及测试基板测试方法
CN117076991B (zh) * 2023-10-16 2024-01-02 云境商务智能研究院南京有限公司 治污设备用电异常监测方法、装置及计算机设备

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3564408A (en) 1968-08-12 1971-02-16 Bendix Corp Test device for an electrical circuit card
DE3013215A1 (de) 1980-04-03 1981-10-15 Luther & Maelzer Gmbh, 3050 Wunstorf Adapter fuer ein selbstprogrammierbares leiterplattenpruefgeraet
DE3240916C2 (de) 1982-11-05 1985-10-31 Luther, Erich, Ing.(Grad.), 3003 Ronnenberg Vorrichtung zum Prüfen von elektrischen Leiterplatten
DE3340180C1 (de) 1983-11-07 1985-05-15 MANIA Elektronik Automatisation Entwicklung und Gerätebau GmbH Kontaktfeldanordnung fuer ein rechnergesteuertes Leiterplattenpruefgeraet
JPS63124969A (ja) 1986-11-14 1988-05-28 Kyoei Sangyo Kk プリント配線板検査機用オフグリツドアダプタ
GB8700754D0 (en) 1987-01-14 1987-02-18 Int Computers Ltd Test apparatus for printed circuit boards
DE8806064U1 (de) 1988-05-06 1989-09-07 atg electronic GmbH, 6980 Wertheim Testgerät
JPH0299200A (ja) 1988-10-06 1990-04-11 Fujita Corp 汚泥の嫌気性消化法
DE4012839B4 (de) 1989-04-26 2004-02-26 Atg Test Systems Gmbh & Co.Kg Verfahren und Prüfvorrichtung zum Prüfen von elektrischen oder elektronischen Prüflingen
US5408189A (en) 1990-05-25 1995-04-18 Everett Charles Technologies, Inc. Test fixture alignment system for printed circuit boards
JPH0438480A (ja) 1990-06-03 1992-02-07 Kyoei Sangyo Kk プリント配線板検査機用アダプタ上下タイプ
JPH0454468A (ja) * 1990-06-25 1992-02-21 Hitachi Electron Eng Co Ltd セラミック配線基板の導通／絶縁検査装置
EP0468153B1 (fr) 1990-07-25 1995-10-11 atg test systems GmbH Dispositif pour contacter des éléments à tester
US5204615A (en) * 1991-10-24 1993-04-20 Interconnect Devices, Inc. Module attachment for printed circuit board test fixtures
JP2720688B2 (ja) 1992-01-31 1998-03-04 ジェイエスアール株式会社 回路基板の検査方法
DE4406538A1 (de) 1994-02-28 1995-08-31 Mania Gmbh Leiterplatten-Prüfeinrichtung mit Prüfadapter und Verfahren zum Einstellen desselben
EP0760104B1 (fr) 1994-05-20 1999-02-03 Luther & Maelzer GmbH Procede et systeme pour controler dans un dispositif de controle la position correcte d'une carte de circuits imprimes comportant des ilots de contact et des traces conducteurs
IT1282827B1 (it) * 1995-09-22 1998-03-31 New System Srl Macchina per il controllo contrapposto dei circuiti stampati
IT1282829B1 (it) 1995-12-22 1998-03-31 New System Srl Macchina di test elettrico per circuiti stampati con posizione registrabile degli aghi di sonda
US5818248A (en) * 1996-07-29 1998-10-06 Delaware Capital Formation, Inc Loaded board test fixture with integral translator fixture for testing closely spaced test sites
DE29616272U1 (de) 1996-09-18 1998-01-29 atg test systems GmbH, 97877 Wertheim Adapter zum Prüfen von elektrischen Leiterplatten
DE19718637A1 (de) 1997-05-02 1998-11-05 Atg Test Systems Gmbh Vorrichtung und Verfahren zum Prüfen von Leiterplatten
DE19700505A1 (de) 1997-01-09 1998-07-16 Atg Test Systems Gmbh Verfahren zum Prüfen von Leiterplatten
IT1290345B1 (it) 1997-02-18 1998-10-22 Circuit Line Spa Metodo e dispositivo per la correzione dell'errore di allineamento fra aghi di test e punti di test nella fase di test elettrico di
IT1291643B1 (it) 1997-04-22 1999-01-19 Circuit Line Spa Metodo di regolazione automatica per l'eliminazione dell'errore di centraggio in fase di test elettrico di circuiti stampati
GB9722998D0 (en) 1997-11-01 1998-01-07 Matrix Test Limited A contacting device
JPH11160380A (ja) * 1997-11-27 1999-06-18 Fujitsu Ltd 回路基板の試験用ヘッドおよび回路基板の試験方法
DE19847146A1 (de) 1998-10-13 2000-05-04 Test Plus Electronic Gmbh Testadapter
US6191600B1 (en) 1999-01-22 2001-02-20 Delaware Capital Formation, Inc. Scan test apparatus for continuity testing of bare printed circuit boards
JP2001074814A (ja) * 1999-09-07 2001-03-23 Sony Corp 回路基板検査装置
DE19943388B4 (de) 1999-09-10 2010-04-08 Atg Luther & Maelzer Gmbh Vorrichtung zum Prüfen von Leiterplatten
DE19957286A1 (de) * 1999-11-29 2001-07-05 Atg Test Systems Gmbh Verfahren und Vorrichtung zum Testen von Leiterplatten
DE60140330D1 (de) * 2000-06-16 2009-12-10 Nhk Spring Co Ltd Mikrokontaktprüfnadel
DE10043728C2 (de) * 2000-09-05 2003-12-04 Atg Test Systems Gmbh Verfahren zum Prüfen von Leiterplatten und Verwendung einer Vorrichtung zum Ausführen des Verfahrens
DE10049301A1 (de) 2000-10-04 2002-05-02 Atg Test Systems Gmbh Modul für eine Prüfvorrichtung zum Testen von Leiterplatten
US6788078B2 (en) 2001-11-16 2004-09-07 Delaware Capital Formation, Inc. Apparatus for scan testing printed circuit boards
GB2383263B (en) 2001-11-17 2005-11-16 Medi Plinth Healthcare Group L Bed
DE10160119A1 (de) * 2001-12-07 2003-10-02 Atg Test Systems Gmbh Prüfsonde für einen Fingertester
US20030197514A1 (en) * 2002-04-22 2003-10-23 Howard Hsu System and method for testing a printed circuit board by employing a ceramic substrate with micro-probes formed on the ceramic substrate
JP2007304008A (ja) * 2006-05-12 2007-11-22 Nidec-Read Corp 基板検査用接触子、基板検査用治具及び基板検査装置
DE102006059429A1 (de) * 2006-12-15 2008-06-26 Atg Luther & Maelzer Gmbh Modul für eine Prüfvorrichtung zum Testen von Leiterplatten

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2010081834A1 *

Also Published As

Publication number Publication date
WO2010081834A1 (fr) 2010-07-22
KR101337911B1 (ko) 2013-12-09
CN102282475A (zh) 2011-12-14
DE102009004555A1 (de) 2010-09-30
BRPI1007227A2 (pt) 2016-02-16
JP2012515339A (ja) 2012-07-05
TW201037328A (en) 2010-10-16
KR20110112836A (ko) 2011-10-13
US20110273203A1 (en) 2011-11-10

Similar Documents

Publication Publication Date Title
WO2010081834A1 (fr) Procédé d'essai de plaquettes à circuit imprimé
DE2360801C2 (de) Schaltungsprüfeinrichtung für integrierte Schaltkreise auf Schichtschaltungsträgern
DE3408704C2 (de) Verfahren zum Prüfen von starren oder flexiblen elektrischen Verbindungsnetzwerk-Schaltungen und Vorrichtung zur Durchführung des Verfahrens
EP0285799B1 (fr) Dispositif de test électrique du fonctionnement de rangées de fils électriques, en particulier pour cartes de circuit
EP0470118B1 (fr) Dispositif de controle pour controler des elements electriques ou electroniques
EP0468153B1 (fr) Dispositif pour contacter des éléments à tester
EP1982203B1 (fr) Procédé et dispositif pour tester des cartes de circuits imprimés nus
DE112005003667B4 (de) Elektrische Prüfsonde
EP2210115B1 (fr) Cassette à grille pleine surface pour un testeur parallèle servant à tester un circuit imprimé nu, pointe de contact à ressort pour une telle cassette à grille pleine surface et adaptateur pour un testeur parallèle servant à tester un circuit imprimé nu
WO2001071371A1 (fr) Dispositif pour le test de cartes imprimees
DE2744299C2 (de) Verfahren zum elektrischen Prüfen eines Leiterbahnmusters auf einem Substrat
EP0508062A1 (fr) Méthode et dispositif pour tester un arrangement de conducteurs électriques
WO2002021893A2 (fr) Procede et dispositif pour controler des cartes de circuits imprimes au moyen d'un controleur en parallele
WO2006133808A1 (fr) Procede pour tester des cartes de circuits imprimes de grandes surfaces non equipees, au moyen d'un testeur a pattes
DE60217619T2 (de) Vorrichtung zur Abtastprüfung von Leiterplatten
DE19718637A1 (de) Vorrichtung und Verfahren zum Prüfen von Leiterplatten
EP0005727B1 (fr) Sonde de touche pour déterminer la position de structures électriquement conductrices
WO2004059329A1 (fr) Adaptateur permettant de tester des structures a conducteurs
DE4109684C2 (de) Kontaktierungsvorrichtung für Prüfzwecke
EP2238461B1 (fr) Module pour un testeur parallèle conçu pour tester des cartes de circuit imprimé
DE19644725C1 (de) Vorrichtung und Verfahren zum Prüfen von Leiterplatten
WO2001040809A1 (fr) Procede et dispositif pour tester des cartes de circuits
DE69512231T2 (de) Testsystem für bestückte und unbestückte schaltungsplatten
WO2002012911A1 (fr) Procede et dispositif permettant de tester le fonctionnement de cartes de circuits imprimes
WO2013004775A1 (fr) Adaptateur destine a un dispositif de controle et dispositif de controle de cartes a circuits imprimes

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20110630

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR

DAX Request for extension of the european patent (deleted)
REG Reference to a national code

Ref country code: HK

Ref legal event code: DE

Ref document number: 1157447

Country of ref document: HK

17Q First examination report despatched

Effective date: 20141121

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20150402

REG Reference to a national code

Ref country code: HK

Ref legal event code: WD

Ref document number: 1157447

Country of ref document: HK