EP2329496A4 - SERIAL SWITCHED STORAGE SYSTEM WITH OUTPUT DELAY SETTING - Google Patents

SERIAL SWITCHED STORAGE SYSTEM WITH OUTPUT DELAY SETTING

Info

Publication number
EP2329496A4
EP2329496A4 EP09817125A EP09817125A EP2329496A4 EP 2329496 A4 EP2329496 A4 EP 2329496A4 EP 09817125 A EP09817125 A EP 09817125A EP 09817125 A EP09817125 A EP 09817125A EP 2329496 A4 EP2329496 A4 EP 2329496A4
Authority
EP
European Patent Office
Prior art keywords
serial
memory system
delay adjustment
output delay
connected memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP09817125A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP2329496A1 (en
Inventor
Hakjune Oh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Novachips Canada Inc
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/241,832 external-priority patent/US8181056B2/en
Priority claimed from US12/241,960 external-priority patent/US8161313B2/en
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Publication of EP2329496A1 publication Critical patent/EP2329496A1/en
Publication of EP2329496A4 publication Critical patent/EP2329496A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
EP09817125A 2008-09-30 2009-09-17 SERIAL SWITCHED STORAGE SYSTEM WITH OUTPUT DELAY SETTING Withdrawn EP2329496A4 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/241,832 US8181056B2 (en) 2008-09-30 2008-09-30 Serial-connected memory system with output delay adjustment
US12/241,960 US8161313B2 (en) 2008-09-30 2008-09-30 Serial-connected memory system with duty cycle correction
PCT/CA2009/001271 WO2010037205A1 (en) 2008-09-30 2009-09-17 Serial-connected memory system with output delay adjustment

Publications (2)

Publication Number Publication Date
EP2329496A1 EP2329496A1 (en) 2011-06-08
EP2329496A4 true EP2329496A4 (en) 2012-06-13

Family

ID=42072981

Family Applications (1)

Application Number Title Priority Date Filing Date
EP09817125A Withdrawn EP2329496A4 (en) 2008-09-30 2009-09-17 SERIAL SWITCHED STORAGE SYSTEM WITH OUTPUT DELAY SETTING

Country Status (6)

Country Link
EP (1) EP2329496A4 (enExample)
JP (2) JP2012504263A (enExample)
KR (1) KR20110081958A (enExample)
CN (1) CN102165529B (enExample)
TW (1) TW201027556A (enExample)
WO (1) WO2010037205A1 (enExample)

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US8665665B2 (en) * 2011-03-30 2014-03-04 Mediatek Inc. Apparatus and method to adjust clock duty cycle of memory
US9257164B2 (en) * 2013-03-14 2016-02-09 Altera Corporation Circuits and methods for DQS autogating
JP6232313B2 (ja) * 2014-02-25 2017-11-15 新日本無線株式会社 同期式シリアル通信方法およびスレーブ装置
KR102757627B1 (ko) * 2016-09-23 2025-01-23 삼성전자주식회사 케스-케이드 연결 구조로 레퍼런스 클록을 전달하는 스토리지 장치들을 포함하는 전자 장치
KR20190009534A (ko) * 2017-07-19 2019-01-29 에스케이하이닉스 주식회사 반도체장치
KR101999125B1 (ko) * 2017-11-24 2019-07-11 파밀넷 주식회사 Rs-422와 rs-485 시리얼 통신을 위한 출력신호 자동 제어기
KR102679157B1 (ko) 2018-10-30 2024-06-27 삼성전자주식회사 모드 레지스터 쓰기 명령을 이용하여 쓰기 클럭의 듀티 사이클의 트레이닝을 수행하는 시스템 온 칩, 시스템 온 칩의 동작 방법, 및 시스템 온 칩을 포함하는 전자 장치
JP2020155841A (ja) * 2019-03-18 2020-09-24 キオクシア株式会社 半導体集積回路及び送信装置
US10937468B2 (en) * 2019-07-03 2021-03-02 Micron Technology, Inc. Memory with configurable die powerup delay
CN111339024A (zh) 2020-04-17 2020-06-26 深圳比特微电子科技有限公司 计算装置以及计算系统
CN112332881B (zh) * 2020-10-19 2022-04-26 深圳市信锐网科技术有限公司 使能电路及通信装置
CN112698683B (zh) * 2020-12-28 2024-07-19 深圳市合信自动化技术有限公司 一种可配置总线解决传输延时数据出错的方法、装置及plc
JP2022141178A (ja) * 2021-03-15 2022-09-29 キオクシア株式会社 メモリシステム
WO2023089778A1 (ja) * 2021-11-19 2023-05-25 株式会社ソシオネクスト メモリ回路
US12424264B2 (en) * 2023-03-14 2025-09-23 Powerchip Semiconductor Manufacturing Corporation Stacked memory with a timing adjustment function

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040148482A1 (en) * 2003-01-13 2004-07-29 Grundy Kevin P. Memory chain
US20050058233A1 (en) * 2003-09-12 2005-03-17 Huy Nguyen System and method for adaptive duty cycle optimization
US6950956B2 (en) * 1999-10-19 2005-09-27 Rambus Inc. Integrated circuit with timing adjustment mechanism and method
US20060136618A1 (en) * 2004-07-30 2006-06-22 International Business Machines Corporation System, method and storage medium for a multi-mode memory buffer device
WO2007106766A2 (en) * 2006-03-16 2007-09-20 Rambus Inc. Signaling system with adaptive timing calibration
US20080028123A1 (en) * 2006-07-26 2008-01-31 Gerald Keith Bartley Computer System Having Daisy Chained Memory Chips

Family Cites Families (16)

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Publication number Priority date Publication date Assignee Title
JP2000148674A (ja) * 1998-11-09 2000-05-30 Sharp Corp シリアルデータ伝送方法
US6839393B1 (en) * 1999-07-14 2005-01-04 Rambus Inc. Apparatus and method for controlling a master/slave system via master device synchronization
JP2003140962A (ja) * 2001-10-30 2003-05-16 Mitsubishi Electric Corp 信号送受信システム
JP3843002B2 (ja) * 2001-11-26 2006-11-08 株式会社ルネサステクノロジ 可変遅延回路及びその可変遅延回路を用いたシステムｌｓｉ
US7533218B2 (en) * 2003-11-17 2009-05-12 Sun Microsystems, Inc. Memory system topology
US6980042B2 (en) * 2004-04-05 2005-12-27 Micron Technology, Inc. Delay line synchronizer apparatus and method
US7352219B2 (en) * 2005-08-30 2008-04-01 Infineon Technologies Ag Duty cycle corrector
KR101260632B1 (ko) 2005-09-30 2013-05-03 모사이드 테크놀로지스 인코퍼레이티드 출력 제어 메모리
US7747833B2 (en) 2005-09-30 2010-06-29 Mosaid Technologies Incorporated Independent link and bank selection
US20070076502A1 (en) 2005-09-30 2007-04-05 Pyeon Hong B Daisy chain cascading devices
US7652922B2 (en) 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
US8069328B2 (en) 2006-03-28 2011-11-29 Mosaid Technologies Incorporated Daisy chain cascade configuration recognition technique
WO2008022454A1 (en) * 2006-08-22 2008-02-28 Mosaid Technologies Incorporated Scalable memory system
JP4952177B2 (ja) * 2006-10-02 2012-06-13 富士通株式会社 記憶装置
US8140803B2 (en) * 2007-01-09 2012-03-20 International Business Machines Corporation Structure for reducing latency associated with read operations in a memory system
CN101617371B (zh) * 2007-02-16 2014-03-26 莫塞德技术公司 具有多个外部电源的非易失性半导体存储器

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6950956B2 (en) * 1999-10-19 2005-09-27 Rambus Inc. Integrated circuit with timing adjustment mechanism and method
US20040148482A1 (en) * 2003-01-13 2004-07-29 Grundy Kevin P. Memory chain
US20050058233A1 (en) * 2003-09-12 2005-03-17 Huy Nguyen System and method for adaptive duty cycle optimization
US20060136618A1 (en) * 2004-07-30 2006-06-22 International Business Machines Corporation System, method and storage medium for a multi-mode memory buffer device
WO2007106766A2 (en) * 2006-03-16 2007-09-20 Rambus Inc. Signaling system with adaptive timing calibration
US20080028123A1 (en) * 2006-07-26 2008-01-31 Gerald Keith Bartley Computer System Having Daisy Chained Memory Chips

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2010037205A1 *

Also Published As

Publication number Publication date
WO2010037205A1 (en) 2010-04-08
CN102165529A (zh) 2011-08-24
KR20110081958A (ko) 2011-07-15
JP2012504263A (ja) 2012-02-16
CN102165529B (zh) 2014-12-31
JP2013008386A (ja) 2013-01-10
EP2329496A1 (en) 2011-06-08
TW201027556A (en) 2010-07-16
JP5599852B2 (ja) 2014-10-01

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Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

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Owner name: NOVACHIPS CANADA INC.

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