Classifications

• • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
  • F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
  • F02D—CONTROLLING COMBUSTION ENGINES
  • F02D13/00—Controlling the engine output power by varying inlet or exhaust valve operating characteristics, e.g. timing
  • F02D13/02—Controlling the engine output power by varying inlet or exhaust valve operating characteristics, e.g. timing during engine operation
• • H—ELECTRICITY
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  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
  • B81C1/00349—Creating layers of material on a substrate
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/185—Joining of semiconductor bodies for junction formation
  • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
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  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
  • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• • H—ELECTRICITY
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  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L23/53204—Conductive materials
  • H01L23/53276—Conductive materials containing carbon, e.g. fullerenes
• • H—ELECTRICITY
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  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
  • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
  • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
  • H01L29/0669—Nanowires or nanotubes
  • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
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  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
  • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
  • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
  • H01L29/0669—Nanowires or nanotubes
  • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
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  • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
  • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
  • H01L2221/1068—Formation and after-treatment of conductors
  • H01L2221/1094—Conducting structures comprising nanotubes or nanowires
• • H—ELECTRICITY
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  • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
  • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
  • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
  • H01L25/0657—Stacked arrangements of devices
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
  • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
  • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
  • H10K71/10—Deposition of organic active material
  • H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
  • H10K71/164—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering using vacuum deposition
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
  • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
  • Y02T10/00—Road transport of goods or passengers
  • Y02T10/10—Internal combustion engine [ICE] based vehicles
  • Y02T10/12—Improving ICE efficiencies

Definitions

• the present invention relates to electronic or electromechanical devices with nano elements. More particularly, it proposes a substrate for at least one electronic or electromechanical component and one or more nanoelements, this substrate being a multilayer structure.
• Nanoelements are used for example in the production of electronic devices. They are generally obtained by catalytic growth CVD, which is the abbreviation of "Chemical Vapor Deposition", or in French “chemical vapor deposition”. Their particular electronic and / or electromechanical properties make it possible to build high performance electronic or electromechanical devices, such as CMOS transistors, interconnections or actuators.
• multilayer structures for the growth of nanoelements. They are generally formed of a base support which may be in a partially conductive material ⁇ , for example monocrystalline silicon, covered with a catalyst layer or a stack at least one layer is catalytic, usually based on metals, from which will grow nanoelements, usually silicon or carbon. Thereafter will be designated by "catalytic system", the catalytic layer or the stack of layers, at least one of which is catalytic for the growth of nanoelements.
• FIG. 1 Such a structure is included in the description of the document US 2007 / 0045691A, it is illustrated in FIG. 1. It is formed of an insulating layer 102 made of silicon oxide (SiO 2 ), resting on a base support 101 made of silicon and a catalytic system 103 overlying the oxide layer 102. This catalytic system 103 allows the growth of nanoelements 104, in this case nanotubes. In order to separate the groups of nano-elements 104 from each other, insulating elements 105 have been formed which delimit boxes 107. Each group of nano-elements is located in a box. These insulating elements 105 serve to support a multilayer electrode 106. This electrode 106 is that of a remote electronic component such as a memory device (not shown), generally made in an area of the substrate 101 juxtaposed to the area described in FIG. these two zones are electrically connected by the electrode 106.
• a remote electronic component such as a memory device (not shown)
• This structure has the major disadvantage of not having the nano-elements and the electronic component in the immediate vicinity of one another, which generates problems of compactness and thereby capacity and resistance problems. connection parasites. But if the catalytic system and the electronic component were arranged in close proximity, they could interact and mutually deteriorate or the catalytic system could disrupt the operation of the electronic component.
• the present invention aims to provide a substrate for the growth of one or more nanoelements and the establishment of at least one electronic or electromechanical component, which does not have the disadvantages of the prior art, namely in particular, the risk of interaction between the catalytic material and the electronic or electromechanical component that may lead to their mutual deterioration. Indeed, a risk is that the catalyst system can be degraded, because of the physical and chemical treatments that the structure undergoes during the component manufacturing steps. However, for a successful growth of the nanoelements, this catalytic system must be of good quality. The stresses exerted on the structure during the manufacturing process must not alter it.
• An object of the invention is therefore to propose a substrate intended to support at least one component electronic or electromechanical and one or more nanoelements and which comprises a catalytic system in which the catalytic system is not likely to interact with the component while playing its role optimally during the growth of the nanoelements.
• Another object of the invention is to provide a substrate for supporting at least one electronic or electromechanical component and one or more nanoelements in which the nanoelements can be accessible.
• the present invention provides a substrate for supporting at least one electronic or electromechanical component and one or more nano-elements, formed of a base support, a catalyst system for the growth of nano-elements comprising at least a catalytic layer, a barrier layer, and a layer adapted to receive the electronic or electromechanical component.
• the catalytic system is based on the base support without contact with the layer suitable for receiving the electronic or electromechanical component and the barrier layer is sandwiched between the catalytic system and the layer able to receive the electronic or electromechanical component so as to avoid a interaction between the catalytic layer and the electronic or electromechanical component, this barrier layer being without contact with the base support.
• the layer capable of accommodating the electronic component or electromechanical is Si monocrystalline or Ge or a mixture of these materials.
• the catalytic system may be formed of one or two groups of layers, each group comprising at least one catalytic layer. At least one of the groups may further comprise a protective layer on the catalytic layer and / or a support layer under the catalytic layer. It is possible that when the catalyst system has two groups of layers, the support layer is common to both groups.
• the catalytic system may be formed of a catalytic layer sandwiched between two support layers, the two support layers optionally being sandwiched between two protective layers.
• the catalytic layer may be made from iron, nickel or cobalt, these elements being taken alone or in alloy.
• the protective layer and the support layer may be made of a material selected from Al 2 O 3 , SiN, SiC, SiON, TiN, TiO 2 , or TaN.
• the base support, the barrier layer and / or the layer capable of accommodating the electronic or electromechanical component may be multilayer.
• the present invention also provides an electronic or electromechanical device comprising at least one structure comprising a substrate thus characterized.
• the structure further comprises at least one electronic or electromechanical component disposed on or in the layer capable of accommodating the electronic or electromechanical component, at least one caisson dug in the substrate exposing locally the catalytic system on which one or more nanoelements support.
• the caisson may have flanks that transversely interrupt the barrier layer revealing a slice of the barrier layer, this slice contributing to form the flanks of the box.
• the box may have flanks that transversely interrupt the catalytic device revealing a slice of the catalytic system, this slice contributing to form the sidewalls of the box, the base support, exposed locally, forming a bottom of the box.
• the structure may furthermore comprise at least one contact device housed in another well dug in the substrate, the well of the nano-elements and the well of the contact device, each having a bottom, the well of the nano-elements and the well of the contact being opposed by their funds.
• the electronic or electromechanical device may comprise several structures stacked on each other.
• the present invention also relates to a method of manufacturing a substrate thus characterized, in which: the catalyst system is formed on the base support;
• the barrier layer is formed on the catalytic system;
• the layer capable of receiving the electronic or electromechanical component made of monocrystalline Si or Ge or a mixture of these materials on the barrier layer is formed.
• the barrier layer and the layer capable of accommodating the electronic or electromechanical component can be formed from:
• a first bonding layer covering the base support, itself covered by the catalytic system, the first bonding layer being overlying the catalytic system or being a surface layer of the catalytic system,
• second bonding layer by assembling the base support and the auxiliary semiconductor substrate by molecular adhesion of their bonding layers, their bonded bonding layers giving the barrier layer, and then effecting a thermal fracture of the auxiliary semiconductor substrate at ion implantation level, a layer of the auxiliary semiconductor substrate remaining bonded to the barrier layer following this fracture giving the layer capable of accommodating the electronic or electromechanical component.
• the barrier layer and the layer capable of receiving the electronic or electromechanical component from a part of a first bonding layer covering the base support, itself covered with the catalytic system, the first layer bonding being overlying the catalytic system or being a surface layer of the catalytic system,
• a second bonding layer covering an SOI-type substrate having an electrically insulating layer sandwiched between two semiconductor layers of different thicknesses, the second bonding layer covering the semiconductor layer and the less thick, by assembling the base support and the SOI-type substrate by molecular adhesion of their bonding layers, their bonded bonding layers giving the barrier layer, and then removing the thickest semiconducting layer and the electrically insulating layer of the SOI type substrate, the thinnest semiconductor layer of the SOI type substrate giving the layer capable of accommodating the electronic or electromechanical component.
• FIG. 1 already described, is a multilayer structure known from the prior art
• FIG. 2 represents a substrate according to the invention
• FIGS. 3A to 3E show various catalytic systems used in the substrate of the invention
• FIGS. 4A to 4D show various steps of a first method of producing a substrate according to the invention using Smart Cut TM technology
• FIGS. 5A to 5D represent different steps of a second method of producing a substrate according to the invention
• FIGS. 6A to 6F illustrate an exemplary method of manufacturing an electronic or electromechanical device according to the invention
• FIGS. 7A to 7D show another example of a method for producing an electronic or electromechanical device according to the invention.
• FIG. 2 represents a substrate according to the invention. It is formed of a stack from a base support 301.
• This base support 301 is preferably made of semiconductor material. It may be for example mono-crystalline silicon, germanium or a mixture of these materials.
• a catalytic system 302 for the growth of one or more nano-elements comprising at least one catalytic layer.
• This catalytic system is generally formed of one or more groups of layers.
• the nanoelements can be, for example, carbon nanotubes, nanowires, nanofibers, etc.
• On this catalytic system rests a barrier layer 303.
• This barrier layer 303 is generally formed of silicon oxide or a metal oxide, such as aluminum oxide.
• this barrier layer 303 which, by virtue of its position in the stack, isolates the catalytic system 302 from an electronic or electromechanical component, not shown, which will be produced on and / or in a surface layer 304 suitable for 'to welcome.
• the barrier layer avoids interaction between the catalytic layer and the electronic or electromechanical component.
• This layer 304 is, for example, mono-crystalline silicon, germanium or a mixture of these materials.
• This layer 304 capable of accommodating the electronic or electromechanical component covers the barrier layer 303.
• This substrate may be for example of the type SOI, the English "Semiconductor On Insulator", or “semiconductor on insulator”.
• the component not shown can be an electronic component as well as an electromechanical component.
• this substrate can form a substrate with a buried ground plane.
• the catalytic system forms the ground plane, if it has sufficient electrical conduction conditions, in addition to its catalytic properties.
• These substrates, with a buried ground plane have an advantage with respect to conventionally used substrates, since they make it easier to activate the electronic components that they receive. Indeed, in these substrates, the applied electric fields remain confined above the ground plane.
• the nano-elements can then allow a contact on the catalytic system that acts as a ground plane.
• FIG. 3A shows an example of a catalytic system 400 that can be used in the substrate of the invention. It comprises only one group of stacked layers, each of these layers can itself be formed of a plurality of sub-layers.
• the group of layers comprises at least one catalytic layer 402. More specifically, it is formed, in this example, a support layer 401, on which rests the catalytic layer 402 for the growth of nanoelements, and a layer of protection 403 above the catalytic layer 402. This protective layer 403 must be removed locally to allow the growth of the nanoelements from the catalyzed layer 402 exposed.
• the protective layer 403 and the support layer 401 have the role of effectively confining the catalytic layer 402.
• the support layer 401 is formed for example of at least one element chosen from: Al 2 O 3, SiN, SiC, SiON, TiN, TiO 2 , TaN. Its thickness can be between about 1 nm and 100 nm.
• the support layer 401 and the catalytic layer 402 allow efficient growth of the nanoelements.
• the catalytic layer 402 may be made based on Fe, Ni or Co, these elements being taken alone or in alloy.
• This catalytic layer 402 has a thickness which may be between about 0.1 nm and 10 nm. It is possible that the catalytic layer 402 is a multilayer, such as a bilayer as shown in Figure 3B.
• the protective layer 403 is such that it can be removed by etching without damaging the catalytic layer 402 when using the substrate. It is formed for example of a material chosen from: Al 2 O 3 SiN, SiC, SiON, TiN, TiO 2 , or TaN. Its thickness can range from 1 to 100 nm, for example. It is sought that the protective layer 403 and the support layer 401 are chemically and thermally stable during all the manufacturing steps of the substrate as well as during its use.
• Figure 3B shows a variant of the catalytic system of Figure 3A. It has been reversed from that of Figure 3A, which allows the nanoelements to grow down.
• the catalytic layer 402 is a bilayer formed of a first sublayer 402.1 as described above and a second sublayer 402.2 of interest for the growth and use of nanoelements.
• the second sublayer 402.2 may be formed for example of silicon and have a thickness of between about 1 and 10 nm.
• the first underlayer 402.1 is on the side of the protective layer 403 and may be formed for example of iron and have a thickness of between about 0.1 and 1 nm.
• Figure 3C shows a third embodiment of the catalytic system 400.
• This catalytic system has two groups of layers as described in Figure 3A contiguous and stacked in reverse order.
• the growth of the nano-elements can be done on one side, on the other or on both sides of the catalytic system according to the catalytic layer (s) which will have been laid bare .
• the groups of layers are joined by their support layers 401. But now, the two support layers are one.
• FIG 3D illustrates yet another simplified embodiment of the catalytic device of nanoelements. It now comprises a single catalytic layer 402 sandwiched between two support layers 401. Optionally, the two support layers 401 can be sandwiched between two protective layers 403 as shown in Figure 3E. These last two configurations also allow the growth of nano-elements on one side or the other or on both sides of the catalytic system.
• FIGS. 4A to 4D illustrate a first exemplary embodiment of this method using Smart Cut TM technology, described, for example, in US Pat. No. 6,372,609 B1.
• auxiliary support 500 made of solid monocrystalline silicon, for example, performs on one of its faces, a so-called bonding layer 501 oxide.
• This bonding layer 501 may be in thermal oxide or a deposited oxide layer. It is this bonding layer 501 which will subsequently form, in part, the barrier layer 403.
• An ion implantation, for example hydrogen is performed ( Figure 4A). This creates a weakened zone 502 located deep in the auxiliary support 500 under the bonding layer 501. It is formed of microcavities (not shown) which will allow the fracture in a subsequent step.
• a catalytic system 400 as described above is produced on a base support 503 of monocrystalline silicon.
• a bonding layer 504 can be formed as described in FIG. 4A. If the bonding layer 504 is not produced, the protective layer 403 of the catalytic system 400 may serve as a bonding layer for molecular bonding, if its material is suitable. This variant is not represented.
• the molecular bonding is carried out between the two structures constructed during the two preceding stages and represented in FIG. 4A, 4B. Bonding takes place between the two bonding layers 501, 504 or between the bonding layer 501 and the protective layer 403 which are brought into contact. To improve the quality of the bonding, it is possible beforehand to treat the surfaces that will be brought into contact. It may be a chemical treatment and / or a chemical mechanical polishing and / or a plasma type surface treatment, for example.
• the structure of FIG. 4C is exposed to a thermal treatment of the order of 250 ° C. at 600 ° C. in order to split it in two at the weakened zone 502.
• the first is a reusable monocrystalline silicon element.
• the second part is the substrate according to the invention. It is represented in FIG. 4D. It consists of the basic support made of monocrystalline silicon 503, covered with catalytic system 400, then with barrier layer 403, then with a thin superficial layer of monocrystalline silicon 304.
• thin layer it is meant that the layer is less thick than the base support 503.
• This thin surface layer 304 is the layer capable of accommodating the electronic or electromechanical component.
• this thin layer 304 It is possible to carry out a treatment of this thin layer 304, in order to ensure a good surface state, and to give it a determined thickness. It consists, for example, firstly in annealing at high temperature to consolidate the bonding interface, and secondly in polishing the thin layer in order to adjust its final thickness.
• FIG. 5A shows a first stack of layers 603 formed of a base support 600, of solid monocrystalline silicon, for example, on which a catalytic system 601, as described above, is coated with a bonding layer 602, which can be in silicon oxide for example. It is possible to dispense with the bonding layer 602 as previously seen. In this case, the protective layer of the catalytic system 601 can replace it, if its material is suitable for molecular adhesion.
• FIG. 5B shows another stack which is a SOI 604 type substrate covered with a bonding layer 608, made of silicon oxide, for example.
• the SOI substrate 604 comprises an electrically insulating layer 606, for example silicon oxide, sandwiched between two semiconductor layers 607, 605.
• One of the semiconductor layers 605 is thicker than the other, referenced 607.
• the semiconductor layers may be in mono-crystalline silicon.
• the bonding layer 608 covers the thinnest semiconductor layer 607.
• the two bonding layers are not absolutely necessary, however one of the two stacks 603 or 604 should have a bonding layer as a surface layer.
• FIG. 5C the two stacks obtained above are assembled by molecular adhesion between the bonding layer 602 of the first stack 603 and the bonding layer 608 of the second stack 604, if the two stacks each have a bonding layer.
• a stack shown in FIG. 5C is obtained. It consists of a succession of layers from the base support 600, namely, in this order: the catalytic system 601, the bonding layer 602 of the first stack, the bonding layer 608 surmounting the SOI substrate 604, the semi-layer The thinnest conductor 607 of the SOI substrate 604, the electrically insulating layer 606 of the SOI substrate 604, the thickest semiconductor layer 605 of the SOI substrate.
• the assembly is carried out by molecular adhesion between the bonding layer 602 of the first stack 603 and the thinnest semiconductor layer 607 of the SOI substrate 604 If the first stack 603 does not have a bonding layer, the assembly is carried out by molecular adhesion between the bonding layer 606 which is equipped with the SOI substrate 604 and the catalytic system 601 of the first stack 603. Then, in a In another step, the thickest semiconductor layer 605 of the SOI substrate 604 is removed by mechanical lapping and then by chemical etching. It is the electrically insulating layer 606 which serves as a stop layer for etching. A stack is obtained as represented in FIG.
• 5D comprising starting from the base support 600, in this order: the catalytic system 601, the bonding layer or layers 602, the thinnest semiconductor layer 607 of the SOI substrate. 604 and the electrically insulating layer 606 of the SOI substrate 604.
• the electrically insulating layer 606 of the SOI substrate 604 is removed.
• a stack is obtained as described in the first embodiment, and shown in FIG. 4D.
• An electronic or electromechanical device equipped with one or more nano-elements according to the invention and a method of producing the device from the substrate thus described will now be described.
• FIG. 6A shows a substrate 700 according to the invention provided with at least one electronic or electromechanical component 708 made on and in the layer able to accommodate the electronic or electromechanical component 704. It is formed of a stack of layers with in this order, the basic support of semiconductor material 301, the catalytic system 702, the barrier layer 703, and finally the layer 704 adapted to accommodate the electronic or electromechanical component 708 on and in which the electronic or electromechanical component has been made.
• At least one box 705 is hollowed into the substrate from the layer capable of receiving the electronic or electromechanical component 704. This box 705 has a bottom which exposes the catalytic system 703 locally. The box 705 is obtained, for example, by dry etching of the reactive plasma type.
• the etching makes it possible to disengage the layer capable of accommodating the electronic or electromechanical component 704, and the barrier layer 703 as illustrated in FIG. 6B.
• the etching must not deteriorate the electronic or electromechanical component 708. It will be seen later that the box can be dug from the base substrate.
• the box 705 has flanks.
• the barrier layer 703 is interrupted transversely and has a slice 703a exposed which contributes to forming the flanks of the box 705. It is the same for the layer able to accommodate the electronic or electromechanical component 704.
• the slice of the layer adapted to accommodating the electronic or electromechanical component 704 is referenced 704a.
• the growth of one or more nanoelements 707 is carried out in box 705.
• the growth may be a thermal CVD growth, starting from a carbonaceous gas.
• the substrate 700 is heated to a temperature between about 400 0 C and 900 0 C. This increase in temperature has the effect of structuring the catalyst system 702, for example in the form of nanoparticles.
• the substrate 700 is then placed in contact with a carbonaceous gas, for example C 2 H 2 , CH 4 , CH 3 COOH or CO, which may optionally be mixed with other gases such as, for example, NH 3 , H 2 , H 2 O in vapor form, He or N 2 .
• Nanoelements 707 may be vertically or horizontally aligned or even entangled. In the example described, the nanoelements 707 grow substantially vertically from the bottom of the box 705 towards its opening. Thanks to the various catalytic devices of nanoelements described above, it is also possible to grow the nanoelements downwards if the box is hollowed out in the base support 301 as will be seen later.
• the catalytic system 702 is an electrical conductor, there are several nano-element growth zones and it is necessary to electrically dissociate different zones of the substrate 700, that is to say, for example to avoid that all zones of growth of the nanoelements are at the same electrical potential, it is possible to delimit zones by engraving, for example by reactive plasma-type etching, a trench 710 around the box 705, this trench 710 passing right through the layer capable of accommodating the electronic or electromechanical component 704, the barrier layer 703, the catalytic system 702 but only partially passing through the base support 301. Reference can be made to FIG. 6D. This trench 710 may optionally then be filled with an electrically insulating material (not shown) to mechanically strengthen the device.
• the casing 705 is etched, from the layer capable of receiving the electronic or electromechanical component 704, but deeper than in the preceding example, so that its bottom locally exposes the base support 301 or is located in the support of base 301.
• the catalytic system 702 is interrupted transversely and has a slice 702a which is exposed and which contributes to forming the flanks of the box 705. It is the same for the barrier layer 703 and the layer able to accommodate the component electronic or electromechanical 704.
• a substantially horizontal growth of at least one nano-element 709 is carried out from the exposed slice 702a of the catalytic system 702.
• the nano-element 709 joins a flank of the box 705 to the other.
• This configuration can be used in sensor applications or reconfigurable circuits.
• the present invention proposes a third method of producing an electronic or electromechanical device according to the invention. It starts from a substrate 700 provided with at least one electronic or electromechanical component 708 and provided with at least one box as shown in Figure 6B.
• the bottom of the box now referenced 711 exposes the catalytic system 702.
• a contact device 800 which allows electrical contact.
• This contact device 800 can contact with the electronic component 708.
• Figure 7A it has a section having the shape of a T.
• a second box 801 is etched from the base support 301 and the bottom of which exposes the catalytic system 702. This is a box for nano-elements.
• the two boxes 711 and 801 are placed "back to back", that is to say that they are opposed by their funds but they can also be offset laterally.
• the catalytic system 702 allows it, that is to say if it is in particular in accordance with one of the configurations of FIGS. 3B to 3E, it is possible to carry out a downward growth of one or more nano-elements. 802 in the box 801.
• Figure 7C illustrates such a structure with two boxes 711, 801 placed back to back, one hosting a contact device 800 and the other one or more nanoelements 802.
• the structure 100 obtained in FIG. 7C instead of being used alone can be used with one or more others by stacking them.
• FIG. 7D a stack with two structures 100 is shown. They are assembled together by making the nano-elements 802 of one structure coincide with a contact device 800 of the other adjacent structure 100. Of course we could stack more than two structures on each other. It is of course possible in the structure to invert nano-elements and contacts. The Nanoelements can then be placed in an open box on the side of the electronic or electromechanical component and the contact in a box which is provided with the base support.

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