Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
  • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02002—Preparing wafers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
  • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
  • H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
  • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits

Definitions

• the present invention relates to a substrate of the semiconductor on insulator type for radio frequency applications.
• the invention also relates to a method of manufacturing such a substrate by transferring a layer of a donor substrate onto a recipient substrate.
• the substrates of the semiconductor on insulator type are multilayer structures comprising a support substrate which is generally made of silicon, an electrically insulating layer arranged on the substrate, typically a layer of silicon oxide, and a semiconductor layer, called layer active, arranged on the insulating layer, in which electronic components are made, which is generally a silicon layer.
• Such substrates are called “Semiconductor on Insulator” (acronym SeOI) in English, in particular “Silicon on Insulator” (SOI) when the semiconductor material is silicon.
• SOI Silicon on Insulator
• the oxide layer which is located between the support substrate and the active layer, is then called “buried”, and is called “BOX” for Buried OXide.
• SOI substrates are widely used for the manufacture of radio frequency devices.
• radio frequency components are produced in the active layer.
• a recurring problem of SOI substrates for radio frequency applications is that electrical charges which are trapped in the BOX layer lead to an accumulation under this same layer, in the support substrate, of charges of opposite sign forming an electrically conductive plane.
• the mobile charges are likely to interact strongly with the electromagnetic fields generated by the radiofrequency components of the active layer.
• a strong drop in the resistivity of the support substrate is then observed, in a plane located directly under the BOX layer, even when the support substrate has a high electrical resistivity.
• a charge trapping layer made of polycrystalline silicon.
• the grain boundaries forming the crystal then constitute traps for the charge carriers, these being able to come from the trapping layer itself or from the underlying support substrate. In this way, the appearance of the conductive plane is prevented under the electrically insulating layer and the drop in resistivity of the support substrate.
• the layer of polycrystalline silicon which is in contact with the support substrate which is made of monocrystalline silicon, tends to recrystallize under the effect of heat treatments applied to the substrate during its manufacture and the manufacture of the radio frequency components.
• the support substrate in fact serves as a seed for recrystallization.
• the recrystallization of the polycrystalline silicon layer by reducing the number of grains, also reduces the capacity of said layer to trap electrical charges.
• An object of the invention is to propose a substrate of the semiconductor on insulator type making it possible to overcome the disadvantages mentioned above.
• the invention aims to propose such a substrate making it possible to limit the interactions between the mobile charges in the substrate and the electromagnetic fields generated by the radio frequency components of the active layer.
• the invention therefore aims to limit or even eliminate the phenomena of loss of coupling between the radiofrequency components and the substrate and of generation of undesirable harmonics.
• the invention provides a semiconductor on insulator type substrate for radio frequency applications, comprising:
• the substrate being mainly characterized in that it further comprises a layer of silicon carbide SiC arranged between the support substrate and the electrically insulating layer, which has a thickness of between 1 nm and 5 nm, the surface of the layer of silicon carbide SiC which is on the side of the electrically insulating layer being rough.
• the presence of a rough SiC layer makes it possible to limit the drop in resistivity usually observed at the interface between the support substrate and the charge trapping layer, and to obtain a semiconductor-on-insulator type substrate having better radio frequency performance.
• a thickness of between 1 nm and 5 nm for the rough SiC layer makes it possible to reproduce the level of roughness due to the level of roughness of the support substrate on which it rests, and thus to maximize the surface of this layer of SiC.
• the proposed substrate has the following different characteristics taken alone or according to their technically possible combinations:
• the monocrystalline layer is of the semiconductor type, that is to say that it comprises a semiconductor material
• the monocrystalline layer is of the ferroelectric type, that is to say that it comprises a ferroelectric material.
• the ferroelectric material is chosen from: LiTa0 3 , LiNb0 3 , LiAI0 3 , BaTi0 3 , PbZrTi0 3 , KNb0 3 , BaZr0 3 , CaTi0 3 , PbTi0 3 , KTa0 3 ;
• the surface of the silicon carbide layer has a roughness greater than or equal to 10 nm RMS, preferably greater than or equal to 100 nm RMS;
• the substrate further comprises a charge trapping layer of polycrystalline silicon arranged between the layer of silicon carbide and the electrically insulating layer;
• the support substrate is monocrystalline
• the electrically insulating layer is a layer of silicon oxide.
• the invention also relates to a process for manufacturing a substrate of the semiconductor on insulator type for radiofrequency applications, mainly characterized in that it comprises the following steps:
• the etching is said to be “selective” in that the silicon constituting the support substrate is not attacked uniformly over the entire free surface of the support substrate, but that privileged regions of this surface (corresponding to particular crystalline planes) are attacked faster than other regions. In this way, the roughening is controlled.
• the configuration of the selective etching makes it possible to choose and adjust the desired depth of the cavities formed in the thickness of the support substrate from its free surface, and therefore to adjust the roughness expected from the surface of the layer of SiC formed subsequently.
• the proposed substrate has the following different characteristics taken alone or according to their technically possible combinations:
• the monocrystalline layer is of the semiconductor type, that is to say that it comprises a semiconductor material
• the monocrystalline layer is of the ferroelectric type, that is to say that it comprises a ferroelectric material.
• the ferroelectric material is chosen from: LiTa0 3 , LiNb0 3 , LiAI0 3 , BaTi0 3 , PbZrTi0 3 , KNb0 3 , BaZr0 3 , CaTi0 3 , PbTi0 3 , KTa0 3 ;
• the roughening step comprises a selective etching along crystalline planes of the free surface of the support substrate
• the roughening step includes:
• the silicon carbide layer is formed by exposing said roughened surface to a precursor gas containing carbonaceous chemical species which causes a reaction of said carbonaceous chemical species with silicon of the support substrate;
• the layer of silicon carbide on the roughened surface of the support substrate is formed by chemical vapor deposition
• the method further comprises, before the transfer of the electrically insulating layer and of the monocrystalline layer, the deposition of a layer for trapping charges of polycrystalline silicon on the layer of silicon carbide;
• the transfer step includes: the supply of a donor substrate covered with an electrically insulating layer,
• FIG. 1 is a diagram illustrating an embodiment of a substrate of the semiconductor on insulator type for radiofrequency applications according to the invention
• Figure 2A is a diagram of a silicon support substrate
• FIG. 2B is a diagram illustrating a step of etching the support substrate of FIG. 1, according to a first embodiment
• Figure 2C is a diagram illustrating a step of forming a layer of SiC on the etched surface of the substrate of Figure 2B, according to the first embodiment, to manufacture an intermediate substrate;
• FIG. 3A is a diagram illustrating a step of nucleation of islands of silicon carbide on a support substrate, according to a second embodiment
• FIG. 3B is a diagram illustrating a step of etching the substrate of FIG. 3A;
• FIG. 3C is a diagram illustrating the growth of the SiC layer until a continuous layer of SiC is obtained
• FIG. 4 is a diagram of a semiconductor on insulator type substrate for radiofrequency applications made from the intermediate substrate obtained by the first embodiment of the method illustrated in FIGS. 2A, 2B, and 2C;
• FIG. 5 is a diagram of a semiconductor on insulator type substrate for radiofrequency applications made from the intermediate substrate obtained by the second embodiment of the method illustrated in FIGS. 3A, 3B, and 3C;
• FIG. 6 is a graph representing the resistivity as a function of the thickness of the substrate in the case of a substrate of the semiconductor on insulator type comprising a layer of smooth SiC silicon carbide or a layer of rough SiC silicon carbide.
• a first object of the invention relates to a semiconductor on insulator type substrate, known as an “SOI substrate”, for radio frequency applications.
• FIG. 1 illustrates an embodiment of the SOI substrate according to the invention.
• the SOI substrate under the reference 1, comprises a silicon support substrate 2, an electrically insulating layer 3 arranged on the support substrate, and a monocrystalline layer 4 arranged on the electrically insulating layer.
• a silicon support substrate 2 an electrically insulating layer 3 arranged on the support substrate
• a monocrystalline layer 4 arranged on the electrically insulating layer.
• on is meant a relative position of the layers considering the substrate from its base (on the side of the support substrate) to its surface (on the side of the monocrystalline layer), but this term does not necessarily imply direct contact between the layers considered.
• the support substrate 2 is preferably monocrystalline.
• the electrically insulating layer 3 is preferably an oxide layer. Due to its positioning in the SOI substrate between the support substrate 2 and the monocrystalline layer 4, such an oxide layer is generally designated by the term "BOX" for Buried OXide (buried oxide) in English.
• the electrically insulating layer is preferably a layer of silicon oxide.
• the monocrystalline layer 4 is advantageously an active layer, that is to say a layer intended for producing radio frequency components as a function of the radio frequency application desired for the SOI substrate.
• the monocrystalline layer is preferably of the semiconductor type. In a particularly preferred manner, it is a layer of monocrystalline silicon.
• the SOI substrate 1 further comprises a layer 5 of silicon carbide (SiC), arranged between the support substrate 2 and the electrically insulating layer 3.
• the layer 5 of SiC is in direct contact with the support substrate 2
• the layer 5 of SiC is also in direct contact with the electrically insulating layer 3.
• the silicon carbide is preferably polycrystalline.
• the upper surface 6 of the SiC layer which is at the interface with the electrically insulating layer, is rough.
• the upper surface of the SiC layer has cavities 7. These cavities have a size, that is to say a height (depending on the thickness of the layer) and a width (in a direction perpendicular to the height), which depends on the roughness value of the surface of the SiC layer.
• the surface of a substrate is rough when it does not allow a good quality bonding (that is to say having a sufficiently high and uniform bonding energy on the contact interface with regard to the subsequent process steps) with another substrate, for example another semiconductor substrate, possibly covered with an oxide layer.
• a surface is thus called rough when it has an RMS roughness of at least 6 Angstroms, that is to say 0.6 nanometers (nm).
• the surface of the SiC layer preferably has a roughness greater than or equal to 10 nm RMS, and more preferably greater than or equal to 100 nm RMS.
• the RMS roughness corresponds to the quadratic mean of all the ordinates of the roughness profile in the base length considered. Those skilled in the art know what the RMS roughness is and how to measure it. Also, these elements will not be described in detail in the present text.
• the surface of the electrically insulating layer 3 which is in contact with the layer of SiC 5 has a profile complementary to that of the surface of said layer of SiC, as illustrated in FIG. 1. More specifically, the lower surface of the electrically insulating layer in contact with the SiC layer has a sawtooth profile whose shape of the teeth corresponds to the shape of the cavities of the SiC layer.
• the SiC layer 5, which constitutes the interface between the support substrate 2 and the electrically insulating layer 3, is not smooth but on the contrary irregular, uneven, with cavities.
• the irregular and uneven profile of the SiC layer makes it possible to increase the area of the upper surface of said SiC layer, that is to say the area of the interface between the SiC layer and the electrically layer insulating.
• the SiC 5 layer has a function of trapping electrical charges in the SOI substrate.
• the grain boundaries of the SiC layer forming the silicon carbide crystal are indeed traps for charge carriers.
• the increase in the area of the interface between the support substrate and the electrically insulating layer therefore makes it possible to improve the trapping of the charges in the SOI substrate, compared with a layer for trapping the charges of the state of the polycrystalline silicon art (notably due to the absence of recrystallization during subsequent heat treatments), or to a layer of smooth silicon carbide (due to the larger area of the interface).
• the SOI substrate 1 also comprises at least one charge trapping layer 8, which is different from the SiC layer.
• a charge trapping layer which is known per se, is advantageously made of polycrystalline silicon.
• the charge trapping layer 8 is arranged between the SiC layer 5 and the electrically insulating layer 3.
• the combination of the charge trapping layer and the SiC layer further improves the trapping of the electric charges within the SOI substrate.
• the SiC layer limits the recrystallization of the polysilicon from the charge trapping layer.
• the SiC layer forms a barrier between the silicon of the support substrate 2 and the polysilicon grains of the charge trapping layer 8, thus preventing the polysilicon grains from recrystallizing according to the support substrate.
• the method of the invention consists first of all, from the silicon support substrate, of roughening a free surface of said support substrate by selective etching. This makes it possible to form cavities in the free surface of the support substrate. A layer of silicon carbide SiC is then formed from the roughened surface.
• the type of selective etching and the etching parameters are chosen and adjusted as a function of the desired depth of the cavities, and therefore of the roughness expected from the surface of the layer of SiC formed subsequently.
• the roughening can advantageously be carried out according to two different embodiments which will now be described.
• a support substrate 2 visible in FIG. 2A is first provided.
• a free surface 9 of the support substrate is roughened by selective etching.
• the substrate of FIG. 2B is then obtained.
• Etching is said to be “selective” in that the silicon is not attacked uniformly over the entire surface of the substrate, but that privileged regions of the surface (corresponding to particular crystalline planes) are attacked more quickly than the others. regions.
• Selective etching is preferably carried out dry.
• Hydrochloric acid is particularly suitable for this purpose.
• a layer of SiC 5 is then formed on the etched surface, as illustrated in FIG. 2C.
• the etched surface 9 is exposed to a precursor gas containing carbonaceous chemical species.
• the latter react with the silicon present in the support substrate, to form silicon carbide SiC.
• the growth of the SiC layer therefore takes place from the roughened surface, in the thickness of the support substrate. Therefore, the free surface of the surface of the SiC layer (which was initially the surface of the silicon support substrate) remains rough.
• the experimental parameters for the formation of the SiC layer are adjusted so as to form a thin layer of SiC, preferably of a lower thickness. or equal to 5 nm. It will also be preferred that the thickness of the SiC layer is greater than or equal to 1 nm. Given the temperature applied, the SiC layer advantageously has a polycrystalline structure.
• the etching is preferably carried out at a temperature between 700 ° C and 1300 ° C, at atmospheric pressure or at a pressure below atmospheric pressure.
• Hydrochloric acid HCl is preferably used in gaseous form for etching.
• this is preferably carried out at a temperature between 700 ° C and 1300 ° C, at a pressure below atmospheric pressure.
• precursor gas in particular propane or methane in hydrogen.
• the reaction time is a function of the quantity of precursor gas; in fact, the reaction is self-limiting, that is to say that the carbonaceous gas reacts with the silicon on the surface of the support substrate and the reaction stops when there is no longer any silicon on the free surface.
• the SiC layer is deposited on the etched surface by chemical vapor deposition, commonly called according to the English terminology "Chemical Vapor Deposition” and designated by the acronym CVD.
• the SiC layer grows from the roughened surface, in a direction opposite to the support substrate.
• This embodiment is less preferred because, the SiC layer being deposited at a lower temperature than in the previous embodiment, it has an amorphous structure.
• the SiC layer is deposited in a substantially homogeneous manner over the entire etched surface, but this deposition does not have the effect of filling the cavities of the etched surface, so that the free surface of the SiC layer retains less in part the roughness of the underlying surface 9.
• a charge trapping layer 8 of polycrystalline silicon is deposited on the SiC layer.
• the stages of selective etching, of formation of the SiC layer and possibly of the charge trapping layer are carried out in the same epitaxy frame, which considerably simplifies the process.
• said steps can be carried out using at least two different pieces of equipment.
• a support substrate visible in FIG. 3A is first provided.
• the free surface 9 of the support substrate is then roughened in two stages.
• a first step comprises the nucleation (or germination) of islands of silicon carbide 10 on said upper surface.
• the upper face 9 is first exposed to a precursor gas containing carbonaceous chemical species. The latter react with the silicon present in the support substrate, to form silicon carbide SiC.
• the islets 10 are obtained by stopping the exposure to carbonaceous chemical species before the islets coalesce and form a continuous layer of SiC on the etched surface. At the end of this nucleation step, the SiC islets are separated from each other by 1 1 zones of silicon.
• a selective etching of the support substrate is then carried out.
• Etching is said to be “selective” in that only the silicon zones are etched, while the islands 10 of SiC are not.
• the SiC islands play the role of a mask which protects the material of the underlying support substrate from etching.
• Selective etching is preferably carried out dry. Hydrochloric acid is particularly suitable for this purpose.
• the substrate of FIG. 3B is obtained.
• Each island 10 comprises a portion of the support substrate covered with a layer of SiC, and is separated from the adjacent islands by the etched areas 12 of silicon, the islets and the etched areas together forming a rough surface of the support substrate.
• the formation of the SiC layer (growth) is then continued until a continuous layer 5 of SiC is obtained, as illustrated in FIG. 3C.
• the roughened surface 9 is exposed to a precursor gas containing carbonaceous chemical species.
• the latter react with the silicon present in the support substrate, to form silicon carbide SiC.
• the experimental parameters for the formation of the SiC layer such as the exposure time, the pressure, the reaction temperature, or even the nature of the precursor gas, and the flow of precursor gas are adjusted so as to form a thin layer.
• of SiC preferably of a thickness less than or equal to 5 nm. It will also be preferred that the thickness of the SiC layer is greater than or equal to 1 nm.
• the SiC layer is preferably formed at a temperature between 700 ° C and 1300 ° C, at a pressure below atmospheric pressure.
• the reaction time is preferably of the order of a few minutes for temperatures in the preceding range from 700 ° C to 1300 ° C.
• the flow ratio between carbonaceous gas and hydrogen influences the germination and growth rates and the final thickness of the SiC layer.
• the SiC layer can be deposited on the surface roughened by CVD as described above for the first embodiment of the roughening.
• a charge trapping layer 8 of polycrystalline silicon is deposited on the SiC layer.
• the steps of nucleation of the SiC islets, of selective etching, of further formation of the SiC layer and possibly the formation of the charge trapping layer are carried out in the same epitaxy frame, this which greatly simplifies the process.
• a bonding layer is formed on the SiC layer, then an electrically insulating layer 3 and a monocrystalline layer 4 are transferred to the bonding layer, so that the electrically insulating layer is at the interface with the bonding layer.
• the bonding layer has a smooth surface suitable for ensuring good quality bonding.
• the bonding layer ensures good adhesion of the electrically insulating layer 3 and of the monocrystalline layer 4 on the SiC layer 5. It may be a layer of silicon oxide, an adhesive layer, an adhesive, or any other suitable means for this purpose.
• the transfer is carried out according to the Smart Cut TM method well known per se, the main steps of which are recalled below.
• a first substrate is provided, called the receiving substrate, which comprises the support substrate 2, the layer of silicon carbide SiC 5, and the bonding layer.
• the receiving substrate comprises a charge trapping layer 8 on the SiC layer, and the bonding layer is arranged on the charge trapping layer.
• a second substrate is also provided, called the donor substrate.
• a weakening zone is formed in the donor substrate, so as to delimit a monocrystalline layer 4.
• the weakening zone is formed in the donor substrate at a predetermined depth which corresponds substantially to the thickness of the monocrystalline layer to be transferred.
• the weakening zone is created by implantation of atoms and / or ions of hydrogen and / or helium in the donor substrate.
• the donor substrate is then bonded to the recipient substrate.
• An electrically insulating layer 3 is arranged between the support substrate 2 and the monocrystalline layer 4.
• the electrically insulating layer 3 is on the receiving substrate, arranged on the SiC layer 5 or, when present, on the charge trapping layer 8.
• the monocrystalline layer 4 is bonded to the electrically insulating layer 3 and is therefore at the bonding interface.
• the electrically insulating layer 3 is on the donor substrate. Both the monocrystalline layer 4 and the electrically insulating layer 3 are bonded to the SiC layer via the bonding layer. The electrically insulating layer 3 is therefore located at the bonding interface.
• the layer transfer process is not however limited to the Smart process
• Cut TM thus, it could consist, for example, of sticking the donor substrate to the recipient substrate and then thinning the donor substrate by its face opposite to the recipient substrate until the desired thickness for the monocrystalline layer is obtained.
• the SOI 1 substrates obtained after transfer according to the first embodiment and the second embodiment, are shown respectively in FIGS. 4 and 5.
• the monocrystalline layer 4 comprises a ferroelectric material.
• the ferroelectric material is advantageously chosen from: LiTa0 3 , LiNb0 3 , LiAI0 3 , BaTi0 3 , PbZrTi0 3 , KNb0 3 , BaZr0 3 , CaTi0 3 , PbTi0 3 or KTa0 3 .
• the donor substrate of said monocrystalline layer can advantageously take the form of a circular wafer of standardized size, for example 150 mm or 200 mm in diameter.
• This wafer may have been taken from an ingot of ferroelectric material, this taking having been carried out so as to form a donor substrate having a predetermined crystal orientation.
• the donor substrate may include a layer of ferroelectric material joined to a support substrate.
• the crystalline orientation of the monocrystalline layer of ferroelectric material to be transferred is chosen according to the intended application.
• the LiNb0 3 material it is usual to choose an orientation around 128 ° XY.
• the invention is in no way limited to a particular crystalline orientation.
• the method comprises for example the introduction of species (ions and / or atoms) of hydrogen and / or helium into the donor substrate.
• This introduction may for example correspond to an implantation of hydrogen, that is to say an ion bombardment of hydrogen from the flat face of the donor substrate.
• the atoms or ions implanted are intended to form a weakening plane delimiting a first layer of ferroelectric material to be transferred and another part forming the rest of the substrate.
• the nature, the dose of the implanted species and the type of the implanted species as well as the implantation energy are chosen according to the thickness of the layer to be transferred and the physico-chemical properties of the donor substrate.
• a donor substrate of LiTa0 3 it will be possible particularly to choose to implant a dose of hydrogen of between 1 E16 and 5E17 at / cm 2 with an energy of between 30 and 300 keV to delimit a first layer of around 20 to 2000 nm thick.
• a first substrate was manufactured by depositing a layer of SiC on a support substrate whose free surface is smooth, that is to say without carrying out a prior etching, then transfer of an electrically insulating layer and d 'a monocrystalline layer on the SiC layer.
• the upper surface of the SiC layer, on the side of the electrically insulating layer, is therefore smooth.
• a second substrate was manufactured according to one of the two embodiments of the manufacturing process described above.
• This second substrate therefore comprises a support substrate, a layer of SiC whose top surface is rough, as well as an electrically insulating layer and a monocrystalline layer arranged on the layer of rough SiC.
• the electrical resistivity of each of the two substrates is measured, for example by the four-point method.
• FIG. 6 represents the evolution of the electrical resistivity R (in ohm. Cm) of the substrates as a function of their depth P (in pm) from the surface of the monocrystalline layer for the first substrate whose SiC layer is smooth (curve C1), and for the second substrate whose SiC layer is rough (curve C2).
• the resistivity drops sharply from the free surface of the substrate to a depth slightly less than 1 ⁇ m which corresponds to the depth of the SiC layer, to reach a minimum value of approximately 5 Q.cm.

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• 2018
  • 2018-12-21 FR FR1873888A patent/FR3091011B1/fr active Active
• 2019
  • 2019-12-19 EP EP19848883.5A patent/EP3900029A1/de active Pending
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