EP3900029A1 - Substrate of the semi-conductor-on-insulator type for radiofrequency applications - Google Patents

Substrate of the semi-conductor-on-insulator type for radiofrequency applications

Info

Publication number
EP3900029A1
EP3900029A1 EP19848883.5A EP19848883A EP3900029A1 EP 3900029 A1 EP3900029 A1 EP 3900029A1 EP 19848883 A EP19848883 A EP 19848883A EP 3900029 A1 EP3900029 A1 EP 3900029A1
Authority
EP
European Patent Office
Prior art keywords
layer
substrate
support substrate
electrically insulating
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP19848883.5A
Other languages
German (de)
French (fr)
Inventor
Kim Young Pil
Christelle Veytizou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of EP3900029A1 publication Critical patent/EP3900029A1/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits

Definitions

  • the present invention relates to a substrate of the semiconductor on insulator type for radio frequency applications.
  • the invention also relates to a method of manufacturing such a substrate by transferring a layer of a donor substrate onto a recipient substrate.
  • the substrates of the semiconductor on insulator type are multilayer structures comprising a support substrate which is generally made of silicon, an electrically insulating layer arranged on the substrate, typically a layer of silicon oxide, and a semiconductor layer, called layer active, arranged on the insulating layer, in which electronic components are made, which is generally a silicon layer.
  • Such substrates are called “Semiconductor on Insulator” (acronym SeOI) in English, in particular “Silicon on Insulator” (SOI) when the semiconductor material is silicon.
  • SOI Silicon on Insulator
  • the oxide layer which is located between the support substrate and the active layer, is then called “buried”, and is called “BOX” for Buried OXide.
  • SOI substrates are widely used for the manufacture of radio frequency devices.
  • radio frequency components are produced in the active layer.
  • a recurring problem of SOI substrates for radio frequency applications is that electrical charges which are trapped in the BOX layer lead to an accumulation under this same layer, in the support substrate, of charges of opposite sign forming an electrically conductive plane.
  • the mobile charges are likely to interact strongly with the electromagnetic fields generated by the radiofrequency components of the active layer.
  • a strong drop in the resistivity of the support substrate is then observed, in a plane located directly under the BOX layer, even when the support substrate has a high electrical resistivity.
  • a charge trapping layer made of polycrystalline silicon.
  • the grain boundaries forming the crystal then constitute traps for the charge carriers, these being able to come from the trapping layer itself or from the underlying support substrate. In this way, the appearance of the conductive plane is prevented under the electrically insulating layer and the drop in resistivity of the support substrate.
  • the layer of polycrystalline silicon which is in contact with the support substrate which is made of monocrystalline silicon, tends to recrystallize under the effect of heat treatments applied to the substrate during its manufacture and the manufacture of the radio frequency components.
  • the support substrate in fact serves as a seed for recrystallization.
  • the recrystallization of the polycrystalline silicon layer by reducing the number of grains, also reduces the capacity of said layer to trap electrical charges.
  • An object of the invention is to propose a substrate of the semiconductor on insulator type making it possible to overcome the disadvantages mentioned above.
  • the invention aims to propose such a substrate making it possible to limit the interactions between the mobile charges in the substrate and the electromagnetic fields generated by the radio frequency components of the active layer.
  • the invention therefore aims to limit or even eliminate the phenomena of loss of coupling between the radiofrequency components and the substrate and of generation of undesirable harmonics.
  • the invention provides a semiconductor on insulator type substrate for radio frequency applications, comprising:
  • the substrate being mainly characterized in that it further comprises a layer of silicon carbide SiC arranged between the support substrate and the electrically insulating layer, which has a thickness of between 1 nm and 5 nm, the surface of the layer of silicon carbide SiC which is on the side of the electrically insulating layer being rough.
  • the presence of a rough SiC layer makes it possible to limit the drop in resistivity usually observed at the interface between the support substrate and the charge trapping layer, and to obtain a semiconductor-on-insulator type substrate having better radio frequency performance.
  • a thickness of between 1 nm and 5 nm for the rough SiC layer makes it possible to reproduce the level of roughness due to the level of roughness of the support substrate on which it rests, and thus to maximize the surface of this layer of SiC.
  • the proposed substrate has the following different characteristics taken alone or according to their technically possible combinations:
  • the monocrystalline layer is of the semiconductor type, that is to say that it comprises a semiconductor material
  • the monocrystalline layer is of the ferroelectric type, that is to say that it comprises a ferroelectric material.
  • the ferroelectric material is chosen from: LiTa0 3 , LiNb0 3 , LiAI0 3 , BaTi0 3 , PbZrTi0 3 , KNb0 3 , BaZr0 3 , CaTi0 3 , PbTi0 3 , KTa0 3 ;
  • the surface of the silicon carbide layer has a roughness greater than or equal to 10 nm RMS, preferably greater than or equal to 100 nm RMS;
  • the substrate further comprises a charge trapping layer of polycrystalline silicon arranged between the layer of silicon carbide and the electrically insulating layer;
  • the support substrate is monocrystalline
  • the electrically insulating layer is a layer of silicon oxide.
  • the invention also relates to a process for manufacturing a substrate of the semiconductor on insulator type for radiofrequency applications, mainly characterized in that it comprises the following steps:
  • the etching is said to be “selective” in that the silicon constituting the support substrate is not attacked uniformly over the entire free surface of the support substrate, but that privileged regions of this surface (corresponding to particular crystalline planes) are attacked faster than other regions. In this way, the roughening is controlled.
  • the configuration of the selective etching makes it possible to choose and adjust the desired depth of the cavities formed in the thickness of the support substrate from its free surface, and therefore to adjust the roughness expected from the surface of the layer of SiC formed subsequently.
  • the proposed substrate has the following different characteristics taken alone or according to their technically possible combinations:
  • the monocrystalline layer is of the semiconductor type, that is to say that it comprises a semiconductor material
  • the monocrystalline layer is of the ferroelectric type, that is to say that it comprises a ferroelectric material.
  • the ferroelectric material is chosen from: LiTa0 3 , LiNb0 3 , LiAI0 3 , BaTi0 3 , PbZrTi0 3 , KNb0 3 , BaZr0 3 , CaTi0 3 , PbTi0 3 , KTa0 3 ;
  • the roughening step comprises a selective etching along crystalline planes of the free surface of the support substrate
  • the roughening step includes:
  • the silicon carbide layer is formed by exposing said roughened surface to a precursor gas containing carbonaceous chemical species which causes a reaction of said carbonaceous chemical species with silicon of the support substrate;
  • the layer of silicon carbide on the roughened surface of the support substrate is formed by chemical vapor deposition
  • the method further comprises, before the transfer of the electrically insulating layer and of the monocrystalline layer, the deposition of a layer for trapping charges of polycrystalline silicon on the layer of silicon carbide;
  • the transfer step includes: the supply of a donor substrate covered with an electrically insulating layer,
  • FIG. 1 is a diagram illustrating an embodiment of a substrate of the semiconductor on insulator type for radiofrequency applications according to the invention
  • Figure 2A is a diagram of a silicon support substrate
  • FIG. 2B is a diagram illustrating a step of etching the support substrate of FIG. 1, according to a first embodiment
  • Figure 2C is a diagram illustrating a step of forming a layer of SiC on the etched surface of the substrate of Figure 2B, according to the first embodiment, to manufacture an intermediate substrate;
  • FIG. 3A is a diagram illustrating a step of nucleation of islands of silicon carbide on a support substrate, according to a second embodiment
  • FIG. 3B is a diagram illustrating a step of etching the substrate of FIG. 3A;
  • FIG. 3C is a diagram illustrating the growth of the SiC layer until a continuous layer of SiC is obtained
  • FIG. 4 is a diagram of a semiconductor on insulator type substrate for radiofrequency applications made from the intermediate substrate obtained by the first embodiment of the method illustrated in FIGS. 2A, 2B, and 2C;
  • FIG. 5 is a diagram of a semiconductor on insulator type substrate for radiofrequency applications made from the intermediate substrate obtained by the second embodiment of the method illustrated in FIGS. 3A, 3B, and 3C;
  • FIG. 6 is a graph representing the resistivity as a function of the thickness of the substrate in the case of a substrate of the semiconductor on insulator type comprising a layer of smooth SiC silicon carbide or a layer of rough SiC silicon carbide.
  • a first object of the invention relates to a semiconductor on insulator type substrate, known as an “SOI substrate”, for radio frequency applications.
  • FIG. 1 illustrates an embodiment of the SOI substrate according to the invention.
  • the SOI substrate under the reference 1, comprises a silicon support substrate 2, an electrically insulating layer 3 arranged on the support substrate, and a monocrystalline layer 4 arranged on the electrically insulating layer.
  • a silicon support substrate 2 an electrically insulating layer 3 arranged on the support substrate
  • a monocrystalline layer 4 arranged on the electrically insulating layer.
  • on is meant a relative position of the layers considering the substrate from its base (on the side of the support substrate) to its surface (on the side of the monocrystalline layer), but this term does not necessarily imply direct contact between the layers considered.
  • the support substrate 2 is preferably monocrystalline.
  • the electrically insulating layer 3 is preferably an oxide layer. Due to its positioning in the SOI substrate between the support substrate 2 and the monocrystalline layer 4, such an oxide layer is generally designated by the term "BOX" for Buried OXide (buried oxide) in English.
  • the electrically insulating layer is preferably a layer of silicon oxide.
  • the monocrystalline layer 4 is advantageously an active layer, that is to say a layer intended for producing radio frequency components as a function of the radio frequency application desired for the SOI substrate.
  • the monocrystalline layer is preferably of the semiconductor type. In a particularly preferred manner, it is a layer of monocrystalline silicon.
  • the SOI substrate 1 further comprises a layer 5 of silicon carbide (SiC), arranged between the support substrate 2 and the electrically insulating layer 3.
  • the layer 5 of SiC is in direct contact with the support substrate 2
  • the layer 5 of SiC is also in direct contact with the electrically insulating layer 3.
  • the silicon carbide is preferably polycrystalline.
  • the upper surface 6 of the SiC layer which is at the interface with the electrically insulating layer, is rough.
  • the upper surface of the SiC layer has cavities 7. These cavities have a size, that is to say a height (depending on the thickness of the layer) and a width (in a direction perpendicular to the height), which depends on the roughness value of the surface of the SiC layer.
  • the surface of a substrate is rough when it does not allow a good quality bonding (that is to say having a sufficiently high and uniform bonding energy on the contact interface with regard to the subsequent process steps) with another substrate, for example another semiconductor substrate, possibly covered with an oxide layer.
  • a surface is thus called rough when it has an RMS roughness of at least 6 Angstroms, that is to say 0.6 nanometers (nm).
  • the surface of the SiC layer preferably has a roughness greater than or equal to 10 nm RMS, and more preferably greater than or equal to 100 nm RMS.
  • the RMS roughness corresponds to the quadratic mean of all the ordinates of the roughness profile in the base length considered. Those skilled in the art know what the RMS roughness is and how to measure it. Also, these elements will not be described in detail in the present text.
  • the surface of the electrically insulating layer 3 which is in contact with the layer of SiC 5 has a profile complementary to that of the surface of said layer of SiC, as illustrated in FIG. 1. More specifically, the lower surface of the electrically insulating layer in contact with the SiC layer has a sawtooth profile whose shape of the teeth corresponds to the shape of the cavities of the SiC layer.
  • the SiC layer 5, which constitutes the interface between the support substrate 2 and the electrically insulating layer 3, is not smooth but on the contrary irregular, uneven, with cavities.
  • the irregular and uneven profile of the SiC layer makes it possible to increase the area of the upper surface of said SiC layer, that is to say the area of the interface between the SiC layer and the electrically layer insulating.
  • the SiC 5 layer has a function of trapping electrical charges in the SOI substrate.
  • the grain boundaries of the SiC layer forming the silicon carbide crystal are indeed traps for charge carriers.
  • the increase in the area of the interface between the support substrate and the electrically insulating layer therefore makes it possible to improve the trapping of the charges in the SOI substrate, compared with a layer for trapping the charges of the state of the polycrystalline silicon art (notably due to the absence of recrystallization during subsequent heat treatments), or to a layer of smooth silicon carbide (due to the larger area of the interface).
  • the SOI substrate 1 also comprises at least one charge trapping layer 8, which is different from the SiC layer.
  • a charge trapping layer which is known per se, is advantageously made of polycrystalline silicon.
  • the charge trapping layer 8 is arranged between the SiC layer 5 and the electrically insulating layer 3.
  • the combination of the charge trapping layer and the SiC layer further improves the trapping of the electric charges within the SOI substrate.
  • the SiC layer limits the recrystallization of the polysilicon from the charge trapping layer.
  • the SiC layer forms a barrier between the silicon of the support substrate 2 and the polysilicon grains of the charge trapping layer 8, thus preventing the polysilicon grains from recrystallizing according to the support substrate.
  • the method of the invention consists first of all, from the silicon support substrate, of roughening a free surface of said support substrate by selective etching. This makes it possible to form cavities in the free surface of the support substrate. A layer of silicon carbide SiC is then formed from the roughened surface.
  • the type of selective etching and the etching parameters are chosen and adjusted as a function of the desired depth of the cavities, and therefore of the roughness expected from the surface of the layer of SiC formed subsequently.
  • the roughening can advantageously be carried out according to two different embodiments which will now be described.
  • a support substrate 2 visible in FIG. 2A is first provided.
  • a free surface 9 of the support substrate is roughened by selective etching.
  • the substrate of FIG. 2B is then obtained.
  • Etching is said to be “selective” in that the silicon is not attacked uniformly over the entire surface of the substrate, but that privileged regions of the surface (corresponding to particular crystalline planes) are attacked more quickly than the others. regions.
  • Selective etching is preferably carried out dry.
  • Hydrochloric acid is particularly suitable for this purpose.
  • a layer of SiC 5 is then formed on the etched surface, as illustrated in FIG. 2C.
  • the etched surface 9 is exposed to a precursor gas containing carbonaceous chemical species.
  • the latter react with the silicon present in the support substrate, to form silicon carbide SiC.
  • the growth of the SiC layer therefore takes place from the roughened surface, in the thickness of the support substrate. Therefore, the free surface of the surface of the SiC layer (which was initially the surface of the silicon support substrate) remains rough.
  • the experimental parameters for the formation of the SiC layer are adjusted so as to form a thin layer of SiC, preferably of a lower thickness. or equal to 5 nm. It will also be preferred that the thickness of the SiC layer is greater than or equal to 1 nm. Given the temperature applied, the SiC layer advantageously has a polycrystalline structure.
  • the etching is preferably carried out at a temperature between 700 ° C and 1300 ° C, at atmospheric pressure or at a pressure below atmospheric pressure.
  • Hydrochloric acid HCl is preferably used in gaseous form for etching.
  • this is preferably carried out at a temperature between 700 ° C and 1300 ° C, at a pressure below atmospheric pressure.
  • precursor gas in particular propane or methane in hydrogen.
  • the reaction time is a function of the quantity of precursor gas; in fact, the reaction is self-limiting, that is to say that the carbonaceous gas reacts with the silicon on the surface of the support substrate and the reaction stops when there is no longer any silicon on the free surface.
  • the SiC layer is deposited on the etched surface by chemical vapor deposition, commonly called according to the English terminology "Chemical Vapor Deposition” and designated by the acronym CVD.
  • the SiC layer grows from the roughened surface, in a direction opposite to the support substrate.
  • This embodiment is less preferred because, the SiC layer being deposited at a lower temperature than in the previous embodiment, it has an amorphous structure.
  • the SiC layer is deposited in a substantially homogeneous manner over the entire etched surface, but this deposition does not have the effect of filling the cavities of the etched surface, so that the free surface of the SiC layer retains less in part the roughness of the underlying surface 9.
  • a charge trapping layer 8 of polycrystalline silicon is deposited on the SiC layer.
  • the stages of selective etching, of formation of the SiC layer and possibly of the charge trapping layer are carried out in the same epitaxy frame, which considerably simplifies the process.
  • said steps can be carried out using at least two different pieces of equipment.
  • a support substrate visible in FIG. 3A is first provided.
  • the free surface 9 of the support substrate is then roughened in two stages.
  • a first step comprises the nucleation (or germination) of islands of silicon carbide 10 on said upper surface.
  • the upper face 9 is first exposed to a precursor gas containing carbonaceous chemical species. The latter react with the silicon present in the support substrate, to form silicon carbide SiC.
  • the islets 10 are obtained by stopping the exposure to carbonaceous chemical species before the islets coalesce and form a continuous layer of SiC on the etched surface. At the end of this nucleation step, the SiC islets are separated from each other by 1 1 zones of silicon.
  • a selective etching of the support substrate is then carried out.
  • Etching is said to be “selective” in that only the silicon zones are etched, while the islands 10 of SiC are not.
  • the SiC islands play the role of a mask which protects the material of the underlying support substrate from etching.
  • Selective etching is preferably carried out dry. Hydrochloric acid is particularly suitable for this purpose.
  • the substrate of FIG. 3B is obtained.
  • Each island 10 comprises a portion of the support substrate covered with a layer of SiC, and is separated from the adjacent islands by the etched areas 12 of silicon, the islets and the etched areas together forming a rough surface of the support substrate.
  • the formation of the SiC layer (growth) is then continued until a continuous layer 5 of SiC is obtained, as illustrated in FIG. 3C.
  • the roughened surface 9 is exposed to a precursor gas containing carbonaceous chemical species.
  • the latter react with the silicon present in the support substrate, to form silicon carbide SiC.
  • the experimental parameters for the formation of the SiC layer such as the exposure time, the pressure, the reaction temperature, or even the nature of the precursor gas, and the flow of precursor gas are adjusted so as to form a thin layer.
  • of SiC preferably of a thickness less than or equal to 5 nm. It will also be preferred that the thickness of the SiC layer is greater than or equal to 1 nm.
  • the SiC layer is preferably formed at a temperature between 700 ° C and 1300 ° C, at a pressure below atmospheric pressure.
  • the reaction time is preferably of the order of a few minutes for temperatures in the preceding range from 700 ° C to 1300 ° C.
  • the flow ratio between carbonaceous gas and hydrogen influences the germination and growth rates and the final thickness of the SiC layer.
  • the SiC layer can be deposited on the surface roughened by CVD as described above for the first embodiment of the roughening.
  • a charge trapping layer 8 of polycrystalline silicon is deposited on the SiC layer.
  • the steps of nucleation of the SiC islets, of selective etching, of further formation of the SiC layer and possibly the formation of the charge trapping layer are carried out in the same epitaxy frame, this which greatly simplifies the process.
  • a bonding layer is formed on the SiC layer, then an electrically insulating layer 3 and a monocrystalline layer 4 are transferred to the bonding layer, so that the electrically insulating layer is at the interface with the bonding layer.
  • the bonding layer has a smooth surface suitable for ensuring good quality bonding.
  • the bonding layer ensures good adhesion of the electrically insulating layer 3 and of the monocrystalline layer 4 on the SiC layer 5. It may be a layer of silicon oxide, an adhesive layer, an adhesive, or any other suitable means for this purpose.
  • the transfer is carried out according to the Smart Cut TM method well known per se, the main steps of which are recalled below.
  • a first substrate is provided, called the receiving substrate, which comprises the support substrate 2, the layer of silicon carbide SiC 5, and the bonding layer.
  • the receiving substrate comprises a charge trapping layer 8 on the SiC layer, and the bonding layer is arranged on the charge trapping layer.
  • a second substrate is also provided, called the donor substrate.
  • a weakening zone is formed in the donor substrate, so as to delimit a monocrystalline layer 4.
  • the weakening zone is formed in the donor substrate at a predetermined depth which corresponds substantially to the thickness of the monocrystalline layer to be transferred.
  • the weakening zone is created by implantation of atoms and / or ions of hydrogen and / or helium in the donor substrate.
  • the donor substrate is then bonded to the recipient substrate.
  • An electrically insulating layer 3 is arranged between the support substrate 2 and the monocrystalline layer 4.
  • the electrically insulating layer 3 is on the receiving substrate, arranged on the SiC layer 5 or, when present, on the charge trapping layer 8.
  • the monocrystalline layer 4 is bonded to the electrically insulating layer 3 and is therefore at the bonding interface.
  • the electrically insulating layer 3 is on the donor substrate. Both the monocrystalline layer 4 and the electrically insulating layer 3 are bonded to the SiC layer via the bonding layer. The electrically insulating layer 3 is therefore located at the bonding interface.
  • the layer transfer process is not however limited to the Smart process
  • Cut TM thus, it could consist, for example, of sticking the donor substrate to the recipient substrate and then thinning the donor substrate by its face opposite to the recipient substrate until the desired thickness for the monocrystalline layer is obtained.
  • the SOI 1 substrates obtained after transfer according to the first embodiment and the second embodiment, are shown respectively in FIGS. 4 and 5.
  • the monocrystalline layer 4 comprises a ferroelectric material.
  • the ferroelectric material is advantageously chosen from: LiTa0 3 , LiNb0 3 , LiAI0 3 , BaTi0 3 , PbZrTi0 3 , KNb0 3 , BaZr0 3 , CaTi0 3 , PbTi0 3 or KTa0 3 .
  • the donor substrate of said monocrystalline layer can advantageously take the form of a circular wafer of standardized size, for example 150 mm or 200 mm in diameter.
  • This wafer may have been taken from an ingot of ferroelectric material, this taking having been carried out so as to form a donor substrate having a predetermined crystal orientation.
  • the donor substrate may include a layer of ferroelectric material joined to a support substrate.
  • the crystalline orientation of the monocrystalline layer of ferroelectric material to be transferred is chosen according to the intended application.
  • the LiNb0 3 material it is usual to choose an orientation around 128 ° XY.
  • the invention is in no way limited to a particular crystalline orientation.
  • the method comprises for example the introduction of species (ions and / or atoms) of hydrogen and / or helium into the donor substrate.
  • This introduction may for example correspond to an implantation of hydrogen, that is to say an ion bombardment of hydrogen from the flat face of the donor substrate.
  • the atoms or ions implanted are intended to form a weakening plane delimiting a first layer of ferroelectric material to be transferred and another part forming the rest of the substrate.
  • the nature, the dose of the implanted species and the type of the implanted species as well as the implantation energy are chosen according to the thickness of the layer to be transferred and the physico-chemical properties of the donor substrate.
  • a donor substrate of LiTa0 3 it will be possible particularly to choose to implant a dose of hydrogen of between 1 E16 and 5E17 at / cm 2 with an energy of between 30 and 300 keV to delimit a first layer of around 20 to 2000 nm thick.
  • a first substrate was manufactured by depositing a layer of SiC on a support substrate whose free surface is smooth, that is to say without carrying out a prior etching, then transfer of an electrically insulating layer and d 'a monocrystalline layer on the SiC layer.
  • the upper surface of the SiC layer, on the side of the electrically insulating layer, is therefore smooth.
  • a second substrate was manufactured according to one of the two embodiments of the manufacturing process described above.
  • This second substrate therefore comprises a support substrate, a layer of SiC whose top surface is rough, as well as an electrically insulating layer and a monocrystalline layer arranged on the layer of rough SiC.
  • the electrical resistivity of each of the two substrates is measured, for example by the four-point method.
  • FIG. 6 represents the evolution of the electrical resistivity R (in ohm. Cm) of the substrates as a function of their depth P (in pm) from the surface of the monocrystalline layer for the first substrate whose SiC layer is smooth (curve C1), and for the second substrate whose SiC layer is rough (curve C2).
  • the resistivity drops sharply from the free surface of the substrate to a depth slightly less than 1 ⁇ m which corresponds to the depth of the SiC layer, to reach a minimum value of approximately 5 Q.cm.

Abstract

The present invention relates to a substrate (1) of the semi-conductor-on-insulator type for radiofrequency applications, comprising: - a carrier substrate (2) of silicon, - an electrically insulating layer (3) which is arranged on the carrier substrate, - a monocrystalline layer (4) which is arranged on the electrically insulating layer, the substrate (1) mainly being characterised in that it further comprises a layer of silicon carbide SiC (5) which is arranged between the carrier substrate (2) and the electrically insulating layer (3), which has a thickness between 1 nm and 5 nm, the surface (6) of the layer of silicon carbide SiC which is at the side of the electrically insulating layer (3) being rough.

Description

SUBSTRAT DE TYPE SEMI-CONDUCTEUR SUR ISOLANT POUR DES SEMICONDUCTOR-ON-INSULATION SUBSTRATE FOR
APPLICATIONS RADIOFRÉQUENCES RADIO FREQUENCY APPLICATIONS
DOMAINE TECHNIQUE DE L'INVENTION TECHNICAL FIELD OF THE INVENTION
La présente invention concerne un substrat de type semi-conducteur sur isolant pour des applications radiofréquences. L’invention se rapporte également à un procédé de fabrication d’un tel substrat par transfert d’une couche d’un substrat donneur sur un substrat receveur. The present invention relates to a substrate of the semiconductor on insulator type for radio frequency applications. The invention also relates to a method of manufacturing such a substrate by transferring a layer of a donor substrate onto a recipient substrate.
ETAT DE LA TECHNIQUE STATE OF THE ART
Les substrats de type semi-conducteur sur isolant sont des structures multicouches comprenant un substrat support qui est généralement en silicium, une couche électriquement isolante agencée sur le substrat, typiquement une couche d’oxyde de silicium, et une couche semi-conductrice, dite couche active, agencée sur la couche isolante, dans laquelle sont réalisés des composants électroniques, qui est généralement une couche de silicium. The substrates of the semiconductor on insulator type are multilayer structures comprising a support substrate which is generally made of silicon, an electrically insulating layer arranged on the substrate, typically a layer of silicon oxide, and a semiconductor layer, called layer active, arranged on the insulating layer, in which electronic components are made, which is generally a silicon layer.
De tels substrats sont dits « Semiconductor on Insulator » (acronyme SeOI) en anglais, en particulier « Silicon on Insulator » (SOI) lorsque le matériau semi-conducteur est du silicium. Such substrates are called “Semiconductor on Insulator” (acronym SeOI) in English, in particular “Silicon on Insulator” (SOI) when the semiconductor material is silicon.
La couche d’oxyde, qui se trouve entre le substrat support et la couche active, est alors dite « enterrée », et est appelée « BOX » pour Buried OXide en anglais. The oxide layer, which is located between the support substrate and the active layer, is then called "buried", and is called "BOX" for Buried OXide.
Les substrats SOI sont largement utilisés pour la fabrication de dispositifs radiofréquences. Dans ce cas, des composants radiofréquences sont réalisés dans la couche active. SOI substrates are widely used for the manufacture of radio frequency devices. In this case, radio frequency components are produced in the active layer.
Un problème récurrent des substrats SOI pour applications radiofréquences est que des charges électriques qui sont piégées dans la couche de BOX conduisent à une accumulation sous cette même couche, dans le substrat support, de charges de signe opposé formant un plan électriquement conducteur. A recurring problem of SOI substrates for radio frequency applications is that electrical charges which are trapped in the BOX layer lead to an accumulation under this same layer, in the support substrate, of charges of opposite sign forming an electrically conductive plane.
Dans ce plan conducteur, les charges mobiles sont susceptibles d'interagir fortement avec les champs électromagnétiques générés par les composants radiofréquences de la couche active. On observe alors une forte chute de la résistivité du substrat support, dans un plan situé directement sous la couche de BOX, et ce même lorsque le substrat support présente une résistivité électrique élevée. In this conducting plane, the mobile charges are likely to interact strongly with the electromagnetic fields generated by the radiofrequency components of the active layer. A strong drop in the resistivity of the support substrate is then observed, in a plane located directly under the BOX layer, even when the support substrate has a high electrical resistivity.
Ceci aboutit à une consommation inutile d’une partie de l’énergie du signal par perte de couplage entre les composants radiofréquences et le substrat, et des interactions possibles entre les composants radiofréquences eux-mêmes par diaphonie (« crosstalk » selon la terminologie anglosaxonne). De plus, les porteurs de charges du substrat peuvent entraîner la génération d’harmoniques non voulues susceptibles d’interférer avec les signaux se propageant dans le dispositif radiofréquence et de dégrader leur qualité. This results in an unnecessary consumption of part of the signal energy by loss of coupling between the radiofrequency components and the substrate, and possible interactions between the radiofrequency components themselves by crosstalk ("crosstalk" according to English terminology) . In addition, the charge carriers of the substrate can cause the generation of unwanted harmonics capable of interfering with the signals propagating in the radiofrequency device and of degrading their quality.
Pour limiter ces phénomènes, il est connu d'insérer entre la couche de BOX et le substrat support, directement sous la couche de BOX, une couche de piégeage de charges, en silicium polycristallin. Les joints des grains formant le cristal constituent alors des pièges pour les porteurs de charges, ceux-ci pouvant provenir de la couche de piégeage elle-même ou du substrat support sous-jacent. De la sorte, on prévient l’apparition du plan conducteur sous la couche électriquement isolante et la chute de résistivité du substrat support. To limit these phenomena, it is known to insert between the BOX layer and the support substrate, directly under the BOX layer, a charge trapping layer, made of polycrystalline silicon. The grain boundaries forming the crystal then constitute traps for the charge carriers, these being able to come from the trapping layer itself or from the underlying support substrate. In this way, the appearance of the conductive plane is prevented under the electrically insulating layer and the drop in resistivity of the support substrate.
Cependant, l’efficacité d’une telle couche de piégeage de charge n’est pas toujours optimale, et les phénomènes de perte de couplage et de génération d’harmoniques non voulues peuvent néanmoins se produire. However, the efficiency of such a charge trapping layer is not always optimal, and phenomena of loss of coupling and generation of unwanted harmonics can nevertheless occur.
En particulier, la couche de silicium polycristallin, qui est au contact du substrat support qui est en silicium monocristallin, a tendance à recristalliser sous l’effet des traitements thermiques appliqués au substrat pendant sa fabrication et la fabrication des composants radiofréquences. Le substrat support sert en effet de germe à la recristallisation. Or, la recristallisation de la couche de silicium polycristallin, en réduisant le nombre de grains, réduit également la capacité de ladite couche à piéger des charges électriques. In particular, the layer of polycrystalline silicon, which is in contact with the support substrate which is made of monocrystalline silicon, tends to recrystallize under the effect of heat treatments applied to the substrate during its manufacture and the manufacture of the radio frequency components. The support substrate in fact serves as a seed for recrystallization. However, the recrystallization of the polycrystalline silicon layer, by reducing the number of grains, also reduces the capacity of said layer to trap electrical charges.
BREVE DESCRIPTION DE L'INVENTION BRIEF DESCRIPTION OF THE INVENTION
Un but de l’invention est de proposer un substrat de type semi-conducteur sur isolant permettant de surmonter les inconvénients mentionnés précédemment. An object of the invention is to propose a substrate of the semiconductor on insulator type making it possible to overcome the disadvantages mentioned above.
L’invention vise à proposer un tel substrat permettant de limiter les interactions entre les charges mobiles dans le substrat et les champs électromagnétiques générés par les composants radiofréquences de la couche active. The invention aims to propose such a substrate making it possible to limit the interactions between the mobile charges in the substrate and the electromagnetic fields generated by the radio frequency components of the active layer.
L’invention vise de ce fait à limiter voire à supprimer les phénomènes de perte de couplage entre les composants radiofréquences et le substrat et de génération d’harmoniques indésirables. The invention therefore aims to limit or even eliminate the phenomena of loss of coupling between the radiofrequency components and the substrate and of generation of undesirable harmonics.
A cette fin, l’invention propose un substrat de type semi-conducteur sur isolant pour des applications radiofréquences, comprenant : To this end, the invention provides a semiconductor on insulator type substrate for radio frequency applications, comprising:
un substrat support en silicium, a silicon support substrate,
une couche électriquement isolante agencée sur le substrat support, an electrically insulating layer arranged on the support substrate,
- une couche monocristalline agencée sur la couche électriquement isolante, le substrat étant principalement caractérisé en ce qu’il comprend en outre une couche de carbure de silicium SiC agencée entre le substrat support et la couche électriquement isolante, qui présente une épaisseur comprise entre 1 nm et 5 nm, la surface de la couche de carbure de silicium SiC qui est du côté de la couche électriquement isolante étant rugueuse. a monocrystalline layer arranged on the electrically insulating layer, the substrate being mainly characterized in that it further comprises a layer of silicon carbide SiC arranged between the support substrate and the electrically insulating layer, which has a thickness of between 1 nm and 5 nm, the surface of the layer of silicon carbide SiC which is on the side of the electrically insulating layer being rough.
La présence d’une couche de SiC rugueuse permet de limiter la chute de résistivité observée habituellement à l’interface entre le substrat support et la couche de piégeage de charges, et d’obtenir un substrat de type semi-conducteur sur isolant présentant de meilleures performances radiofréquences. The presence of a rough SiC layer makes it possible to limit the drop in resistivity usually observed at the interface between the support substrate and the charge trapping layer, and to obtain a semiconductor-on-insulator type substrate having better radio frequency performance.
Une épaisseur comprise entre 1 nm et 5 nm pour la couche de SiC rugueuse permet de reproduire le niveau de rugosité dû au niveau de rugosité du substrat support sur lequel elle repose, et ainsi de maximiser la surface de cette couche de SiC. A thickness of between 1 nm and 5 nm for the rough SiC layer makes it possible to reproduce the level of roughness due to the level of roughness of the support substrate on which it rests, and thus to maximize the surface of this layer of SiC.
Selon d’autres aspects, le substrat proposé présente les différentes caractéristiques suivantes prises seules ou selon leurs combinaisons techniquement possibles : According to other aspects, the proposed substrate has the following different characteristics taken alone or according to their technically possible combinations:
la couche monocristalline est de type semi-conducteur, c’est-à-dire qu’elle comprend un matériau semi-conducteur ; the monocrystalline layer is of the semiconductor type, that is to say that it comprises a semiconductor material;
la couche monocristalline est de type ferroélectrique, c’est-à-dire qu’elle comprend un matériau ferroélectrique. De préférence, le matériau ferroélectrique est choisi parmi : LiTa03, LiNb03, LiAI03, BaTi03, PbZrTi03, KNb03, BaZr03, CaTi03, PbTi03, KTa03 ; the monocrystalline layer is of the ferroelectric type, that is to say that it comprises a ferroelectric material. Preferably, the ferroelectric material is chosen from: LiTa0 3 , LiNb0 3 , LiAI0 3 , BaTi0 3 , PbZrTi0 3 , KNb0 3 , BaZr0 3 , CaTi0 3 , PbTi0 3 , KTa0 3 ;
la surface de la couche de carbure de silicium présente une rugosité supérieure ou égale à 10 nm RMS, de préférence supérieure ou égale à 100 nm RMS ; the surface of the silicon carbide layer has a roughness greater than or equal to 10 nm RMS, preferably greater than or equal to 100 nm RMS;
le substrat comprend en outre une couche de piégeage de charges en silicium polycristallin agencée entre la couche de carbure de silicium et la couche électriquement isolante ; the substrate further comprises a charge trapping layer of polycrystalline silicon arranged between the layer of silicon carbide and the electrically insulating layer;
le substrat support est monocristallin ; the support substrate is monocrystalline;
la couche électriquement isolante est une couche d’oxyde de silicium. the electrically insulating layer is a layer of silicon oxide.
L’invention se rapporte également à un procédé de fabrication d’un substrat de type semi-conducteur sur isolant pour des applications radiofréquences, principalement caractérisé en ce qu’il comprend les étapes suivantes : The invention also relates to a process for manufacturing a substrate of the semiconductor on insulator type for radiofrequency applications, mainly characterized in that it comprises the following steps:
fourniture d’un substrat support en silicium, supply of a silicon support substrate,
rugosification d’une surface libre du substrat support par gravure sélective, formation d’une couche de carbure de silicium sur la surface rugosifiée, la surface de la couche de carbure de silicium qui est du côté opposé au substrat support étant rugueuse, roughening of a free surface of the support substrate by selective etching, formation of a layer of silicon carbide on the roughened surface, the surface of the layer of silicon carbide which is on the side opposite to the support substrate being rough,
formation d’une couche de collage sur la couche de carbure de silicium, transfert d’une couche électriquement isolante et d’une couche monocristalline sur la couche de collage, la couche électriquement isolante étant à l’interface avec la couche de collage. La gravure est dite « sélective » en ce que le silicium constitutif du substrat support n’est pas attaqué de manière uniforme sur toute la surface libre du substrat support, mais que des régions privilégiées de cette surface (correspondant à des plans cristallins particuliers) sont attaquées plus rapidement que les autres régions. De cette manière, la rugosification est contrôlée. forming a bonding layer on the silicon carbide layer, transfer of an electrically insulating layer and a monocrystalline layer on the bonding layer, the electrically insulating layer being at the interface with the bonding layer. The etching is said to be “selective” in that the silicon constituting the support substrate is not attacked uniformly over the entire free surface of the support substrate, but that privileged regions of this surface (corresponding to particular crystalline planes) are attacked faster than other regions. In this way, the roughening is controlled.
Le paramétrage de la gravure sélective permet de choisir et d’ajuster la profondeur souhaitée des cavités formées dans l’épaisseur du substrat support depuis sa surface libre, et donc d’ajuster la rugosité attendue de la surface de la couche de SiC formée ultérieurement. The configuration of the selective etching makes it possible to choose and adjust the desired depth of the cavities formed in the thickness of the support substrate from its free surface, and therefore to adjust the roughness expected from the surface of the layer of SiC formed subsequently.
Selon d’autres aspects, le substrat proposé présente les différentes caractéristiques suivantes prises seules ou selon leurs combinaisons techniquement possibles : According to other aspects, the proposed substrate has the following different characteristics taken alone or according to their technically possible combinations:
la couche monocristalline est de type semi-conducteur, c’est-à-dire qu’elle comprend un matériau semi-conducteur ; the monocrystalline layer is of the semiconductor type, that is to say that it comprises a semiconductor material;
la couche monocristalline est de type ferroélectrique, c’est-à-dire qu’elle comprend un matériau ferroélectrique. De préférence, le matériau ferroélectrique est choisi parmi : LiTa03, LiNb03, LiAI03, BaTi03, PbZrTi03, KNb03, BaZr03, CaTi03, PbTi03, KTa03 ; the monocrystalline layer is of the ferroelectric type, that is to say that it comprises a ferroelectric material. Preferably, the ferroelectric material is chosen from: LiTa0 3 , LiNb0 3 , LiAI0 3 , BaTi0 3 , PbZrTi0 3 , KNb0 3 , BaZr0 3 , CaTi0 3 , PbTi0 3 , KTa0 3 ;
l’étape de rugosification comprend une gravure sélective selon des plans cristallins de la surface libre du substrat support ; the roughening step comprises a selective etching along crystalline planes of the free surface of the support substrate;
l’étape de rugosification comprend : the roughening step includes:
la nucléation d’îlots de carbure de silicium sur la surface libre du substrat support par exposition de ladite surface libre à un gaz précurseur contenant des espèces chimiques carbonées qui engendre une réaction desdites espèces chimiques carbonées avec du silicium du substrat support, la gravure sélective des zones de la surface libre du substrat support séparant les îlots. nucleation of islands of silicon carbide on the free surface of the support substrate by exposure of said free surface to a precursor gas containing carbonaceous chemical species which generates a reaction of said carbonaceous chemical species with silicon of the support substrate, the selective etching of the areas of the free surface of the support substrate separating the islands.
la gravure sélective est réalisée par voie sèche ; selective etching is carried out dry;
la gravure sélective par voie sèche est réalisée avec de l’acide chlorhydrique ; la couche de carbure de silicium est formée par exposition de ladite surface rugosifiée à un gaz précurseur contenant des espèces chimiques carbonées qui engendre une réaction desdites espèces chimiques carbonées avec du silicium du substrat support ; selective dry etching is carried out with hydrochloric acid; the silicon carbide layer is formed by exposing said roughened surface to a precursor gas containing carbonaceous chemical species which causes a reaction of said carbonaceous chemical species with silicon of the support substrate;
la couche de carbure de silicium sur la surface rugosifiée du substrat support est formée par dépôt chimique en phase vapeur ; the layer of silicon carbide on the roughened surface of the support substrate is formed by chemical vapor deposition;
le procédé comprend en outre, avant le transfert de la couche électriquement isolante et de la couche monocristalline, le dépôt d’une couche de piégeage de charges en silicium polycristallin sur la couche de carbure de silicium ; the method further comprises, before the transfer of the electrically insulating layer and of the monocrystalline layer, the deposition of a layer for trapping charges of polycrystalline silicon on the layer of silicon carbide;
l’étape de transfert comprend : la fourniture d’un substrat donneur recouvert d’une couche électriquement isolante, the transfer step includes: the supply of a donor substrate covered with an electrically insulating layer,
la formation d’une zone de fragilisation dans le substrat donneur, de sorte à délimiter une couche monocristalline, the formation of a weakening zone in the donor substrate, so as to delimit a monocrystalline layer,
- le collage du substrat donneur sur le substrat support par l’intermédiaire de la couche électriquement isolante et de la couche de collage, - the bonding of the donor substrate to the support substrate by means of the electrically insulating layer and the bonding layer,
le détachement du substrat donneur le long de la zone de fragilisation, de sorte à transférer la couche monocristalline sur le substrat support. DESCRIPTION DES FIGURES detaching the donor substrate along the embrittlement zone, so as to transfer the monocrystalline layer onto the support substrate. DESCRIPTION OF THE FIGURES
D’autres avantages et caractéristiques de l’invention apparaîtront à la lecture de la description suivante donnée à titre d’exemple illustratif et non limitatif, en référence aux figures annexées suivantes : Other advantages and characteristics of the invention will appear on reading the following description given by way of illustrative and nonlimiting example, with reference to the following appended figures:
la figure 1 est un schéma illustrant un mode de réalisation d’un substrat de type semi-conducteur sur isolant pour des applications radiofréquences selon l’invention ; la figure 2A est un schéma d’un substrat support en silicium ; FIG. 1 is a diagram illustrating an embodiment of a substrate of the semiconductor on insulator type for radiofrequency applications according to the invention; Figure 2A is a diagram of a silicon support substrate;
la figure 2B est un schéma illustrant une étape de gravure du substrat support de la figure 1 , selon un premier mode de réalisation ; FIG. 2B is a diagram illustrating a step of etching the support substrate of FIG. 1, according to a first embodiment;
la figure 2C est un schéma illustrant une étape de formation d’une couche de SiC sur la surface gravée du substrat de la figure 2B, selon le premier mode de réalisation, pour fabriquer un substrat intermédiaire ; Figure 2C is a diagram illustrating a step of forming a layer of SiC on the etched surface of the substrate of Figure 2B, according to the first embodiment, to manufacture an intermediate substrate;
la figure 3A est un schéma illustrant une étape de la nucléation d’îlots de carbure de silicium sur un substrat support, selon un deuxième mode de réalisation ; FIG. 3A is a diagram illustrating a step of nucleation of islands of silicon carbide on a support substrate, according to a second embodiment;
la figure 3B est un schéma illustrant une étape de gravure du substrat de la figure 3A ; FIG. 3B is a diagram illustrating a step of etching the substrate of FIG. 3A;
la figure 3C est un schéma illustrant la croissance de la couche de SiC jusqu’à l’obtention d’une couche continue de SiC ; FIG. 3C is a diagram illustrating the growth of the SiC layer until a continuous layer of SiC is obtained;
la figure 4 est un schéma d’un substrat de type semi-conducteur sur isolant pour des applications radiofréquences fabriqué à partir du substrat intermédiaire obtenu par le premier mode réalisation du procédé illustré sur les figures 2A, 2B, et 2C ; FIG. 4 is a diagram of a semiconductor on insulator type substrate for radiofrequency applications made from the intermediate substrate obtained by the first embodiment of the method illustrated in FIGS. 2A, 2B, and 2C;
la figure 5 est un schéma d’un substrat de type semi-conducteur sur isolant pour des applications radiofréquences fabriqué à partir du substrat intermédiaire obtenu par le deuxième mode réalisation du procédé illustré sur les figures 3A, 3B, et 3C ; FIG. 5 is a diagram of a semiconductor on insulator type substrate for radiofrequency applications made from the intermediate substrate obtained by the second embodiment of the method illustrated in FIGS. 3A, 3B, and 3C;
la figure 6 est un graphe représentant la résistivité en fonction de l’épaisseur de substrat dans le cas d’un substrat de type semi-conducteur sur isolant comprenant une couche de carbure de silicium SiC lisse ou une couche de carbure de silicium SiC rugueuse. DESCRIPTION DETAILLEE DE MODES DE REALISATION DE L’INVENTION FIG. 6 is a graph representing the resistivity as a function of the thickness of the substrate in the case of a substrate of the semiconductor on insulator type comprising a layer of smooth SiC silicon carbide or a layer of rough SiC silicon carbide. DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION
Un premier objet de l’invention concerne un substrat de type semi-conducteur sur isolant, dit « substrat SOI », pour des applications radiofréquences. A first object of the invention relates to a semiconductor on insulator type substrate, known as an “SOI substrate”, for radio frequency applications.
La figure 1 illustre un mode de réalisation du substrat SOI selon l’invention. FIG. 1 illustrates an embodiment of the SOI substrate according to the invention.
Le substrat SOI, sous la référence 1 , comprend un substrat support 2 en silicium, une couche électriquement isolante 3 agencée sur le substrat support, et une couche monocristalline 4 agencée sur la couche électriquement isolante. Par « sur » on désigne une position relative des couches en considérant le substrat de sa base (du côté du substrat support) vers sa surface (du côté de la couche monocristalline), mais ce terme n’implique pas nécessairement un contact direct entre les couches considérées. The SOI substrate, under the reference 1, comprises a silicon support substrate 2, an electrically insulating layer 3 arranged on the support substrate, and a monocrystalline layer 4 arranged on the electrically insulating layer. By “on” is meant a relative position of the layers considering the substrate from its base (on the side of the support substrate) to its surface (on the side of the monocrystalline layer), but this term does not necessarily imply direct contact between the layers considered.
Le substrat support 2 est de préférence monocristallin. The support substrate 2 is preferably monocrystalline.
La couche électriquement isolante 3 est de préférence une couche d’oxyde. Du fait de son positionnement dans le substrat SOI entre le substrat support 2 et la couche monocristalline 4, une telle couche d’oxyde est généralement désignée par le terme « BOX » pour Buried OXide (oxyde enterré) en anglais. La couche électriquement isolante est de préférence une couche d’oxyde de silicium. The electrically insulating layer 3 is preferably an oxide layer. Due to its positioning in the SOI substrate between the support substrate 2 and the monocrystalline layer 4, such an oxide layer is generally designated by the term "BOX" for Buried OXide (buried oxide) in English. The electrically insulating layer is preferably a layer of silicon oxide.
La couche monocristalline 4 est avantageusement une couche active, c’est-à-dire une couche destinée à la réalisation de composants radiofréquences en fonction de l’application radiofréquence souhaitée pour le substrat SOI. The monocrystalline layer 4 is advantageously an active layer, that is to say a layer intended for producing radio frequency components as a function of the radio frequency application desired for the SOI substrate.
La couche monocristalline est de préférence de type semi-conducteur. De manière particulièrement préférée, il s’agit d’une couche de silicium monocristallin. The monocrystalline layer is preferably of the semiconductor type. In a particularly preferred manner, it is a layer of monocrystalline silicon.
Selon l’invention, le substrat SOI 1 comprend en outre une couche 5 de carbure de silicium (SiC), agencée entre le substrat support 2 et la couche électriquement isolante 3. La couche 5 de SiC est en contact direct avec le substrat support 2. Dans le mode de réalisation de la figure 1 , la couche 5 de SiC est également en contact direct avec la couche électriquement isolante 3. According to the invention, the SOI substrate 1 further comprises a layer 5 of silicon carbide (SiC), arranged between the support substrate 2 and the electrically insulating layer 3. The layer 5 of SiC is in direct contact with the support substrate 2 In the embodiment of FIG. 1, the layer 5 of SiC is also in direct contact with the electrically insulating layer 3.
Le carbure de silicium est de préférence polycristallin. The silicon carbide is preferably polycrystalline.
La surface supérieure 6 de la couche de SiC, qui se trouve à l’interface avec la couche électriquement isolante, est rugueuse. Cela signifie que la surface supérieure de la couche de SiC présente des cavités 7. Ces cavités ont une taille, c’est-à-dire une hauteur (selon l’épaisseur de la couche) et une largeur (dans un sens perpendiculaire à la hauteur), qui dépend de la valeur de rugosité de la surface de la couche SiC. The upper surface 6 of the SiC layer, which is at the interface with the electrically insulating layer, is rough. This means that the upper surface of the SiC layer has cavities 7. These cavities have a size, that is to say a height (depending on the thickness of the layer) and a width (in a direction perpendicular to the height), which depends on the roughness value of the surface of the SiC layer.
Dans le domaine des semi-conducteurs, on considère que la surface d’un substrat est rugueuse lorsqu’elle ne permet pas un collage de bonne qualité (c’est-à-dire présentant une énergie de collage suffisamment élevée et uniforme sur l’interface de contact au regard des étapes de procédé ultérieures) avec un autre substrat, par exemple un autre substrat semi-conducteur, éventuellement recouvert d’une couche d’oxyde. De manière générale, une surface est ainsi dite rugueuse lorsqu’elle présente une rugosité RMS d’au moins 6 Angstroms, c’est-à-dire 0,6 nanomètres (nm). In the field of semiconductors, it is considered that the surface of a substrate is rough when it does not allow a good quality bonding (that is to say having a sufficiently high and uniform bonding energy on the contact interface with regard to the subsequent process steps) with another substrate, for example another semiconductor substrate, possibly covered with an oxide layer. In general, a surface is thus called rough when it has an RMS roughness of at least 6 Angstroms, that is to say 0.6 nanometers (nm).
Selon l’invention, la surface de la couche de SiC présente de préférence une rugosité supérieure ou égale à 10 nm RMS, et de manière davantage préférée supérieure ou égale à 100 nm RMS. La rugosité RMS correspond à la moyenne quadratique de toutes les ordonnées du profil de rugosité dans la longueur de base considérée. L’homme du métier sait à quoi correspond la rugosité RMS et comment la mesurer. Aussi, ces éléments ne seront pas décrits en détail dans le présent texte. According to the invention, the surface of the SiC layer preferably has a roughness greater than or equal to 10 nm RMS, and more preferably greater than or equal to 100 nm RMS. The RMS roughness corresponds to the quadratic mean of all the ordinates of the roughness profile in the base length considered. Those skilled in the art know what the RMS roughness is and how to measure it. Also, these elements will not be described in detail in the present text.
Sur la figure 1 , la surface 6 de la couche de SiC est représentée schématiquement avec un profil en dent de scie. In Figure 1, the surface 6 of the SiC layer is shown schematically with a sawtooth profile.
La surface de la couche électriquement isolante 3 qui se trouve au contact de la couche de SiC 5 présente un profil complémentaire de celui de la surface de ladite couche de SiC, comme l’illustre la figure 1. Plus précisément, la surface inférieure de la couche électriquement isolante au contact de la couche SiC présente un profil en dent de scie dont la forme des dents correspond à la forme des cavités de la couche de SiC. The surface of the electrically insulating layer 3 which is in contact with the layer of SiC 5 has a profile complementary to that of the surface of said layer of SiC, as illustrated in FIG. 1. More specifically, the lower surface of the electrically insulating layer in contact with the SiC layer has a sawtooth profile whose shape of the teeth corresponds to the shape of the cavities of the SiC layer.
Dès lors, la couche de SiC 5, qui constitue l’interface entre le substrat support 2 et la couche électriquement isolante 3, n’est pas lisse mais au contraire irrégulière, accidentée, avec des cavités. Consequently, the SiC layer 5, which constitutes the interface between the support substrate 2 and the electrically insulating layer 3, is not smooth but on the contrary irregular, uneven, with cavities.
Le profil irrégulier et accidenté de la couche de SiC permet d’augmenter l’aire de la surface supérieure de ladite couche de SiC, c’est-à-dire l’aire de l’interface entre la couche de SiC et la couche électriquement isolante. The irregular and uneven profile of the SiC layer makes it possible to increase the area of the upper surface of said SiC layer, that is to say the area of the interface between the SiC layer and the electrically layer insulating.
La couche de SiC 5 a une fonction de piégeage des charges électriques dans le substrat SOI. Les joints des grains de la couche de SiC formant le cristal de carbure de silicium constituent en effet des pièges pour les porteurs de charges. The SiC 5 layer has a function of trapping electrical charges in the SOI substrate. The grain boundaries of the SiC layer forming the silicon carbide crystal are indeed traps for charge carriers.
L’augmentation de l’aire de l’interface entre le substrat support et la couche électriquement isolante permet dès lors d’améliorer le piégeage des charges dans le substrat SOI, comparativement à une couche de piégeage des charges de l’état de l’art en silicium polycristallin (notamment du fait de l’absence de recristallisation lors des traitements thermiques ultérieurs), ou à une couche de carbure de silicium lisse (du fait de l’aire plus grande de l’interface). The increase in the area of the interface between the support substrate and the electrically insulating layer therefore makes it possible to improve the trapping of the charges in the SOI substrate, compared with a layer for trapping the charges of the state of the polycrystalline silicon art (notably due to the absence of recrystallization during subsequent heat treatments), or to a layer of smooth silicon carbide (due to the larger area of the interface).
Selon un deuxième mode de réalisation illustré sur la figure 4, le substrat SOI 1 comprend également au moins une couche de piégeage de charges 8, qui est différente de la couche de SiC. Une telle couche de piégeage de charges, qui est connue en soi, est avantageusement en silicium polycristallin. According to a second embodiment illustrated in FIG. 4, the SOI substrate 1 also comprises at least one charge trapping layer 8, which is different from the SiC layer. Such a charge trapping layer, which is known per se, is advantageously made of polycrystalline silicon.
La couche de piégeage de charges 8 est agencée entre la couche de SiC 5 et la couche électriquement isolante 3. La combinaison de la couche de piégeage de charges et de la couche de SiC améliore encore le piégeage des charges électriques au sein du substrat SOI. En particulier, la couche de SiC limite la recristallisation du polysilicium de la couche de piégeage de charges. En effet, la couche de SiC forme une barrière entre le silicium du substrat support 2 et les grains du polysilicium de la couche de piégeage de charges 8, évitant ainsi que les grains de polysilicium ne recristallisent suivant le substrat support. The charge trapping layer 8 is arranged between the SiC layer 5 and the electrically insulating layer 3. The combination of the charge trapping layer and the SiC layer further improves the trapping of the electric charges within the SOI substrate. In particular, the SiC layer limits the recrystallization of the polysilicon from the charge trapping layer. Indeed, the SiC layer forms a barrier between the silicon of the support substrate 2 and the polysilicon grains of the charge trapping layer 8, thus preventing the polysilicon grains from recrystallizing according to the support substrate.
Un procédé de fabrication d’un substrat SOI tel que présenté précédemment va maintenant être décrit. A method of manufacturing an SOI substrate as presented above will now be described.
Le procédé de l’invention consiste d’abord, à partir du substrat support en silicium, à rugosifier une surface libre dudit substrat support par gravure sélective. Ceci permet de former des cavités dans la surface libre du substrat support. On forme ensuite une couche de carbure de silicium SiC à partir de la surface rugosifiée. The method of the invention consists first of all, from the silicon support substrate, of roughening a free surface of said support substrate by selective etching. This makes it possible to form cavities in the free surface of the support substrate. A layer of silicon carbide SiC is then formed from the roughened surface.
Le type de gravure sélective ainsi que les paramètres de gravure sont choisis et ajustés en fonction de la profondeur souhaitée des cavités, et donc de la rugosité attendue de la surface de la couche de SiC formée ultérieurement. The type of selective etching and the etching parameters are chosen and adjusted as a function of the desired depth of the cavities, and therefore of the roughness expected from the surface of the layer of SiC formed subsequently.
La rugosification peut avantageusement être réalisée selon deux modes de réalisation différents qui vont maintenant être décrits. The roughening can advantageously be carried out according to two different embodiments which will now be described.
Selon un premier mode de réalisation de la rugosification, en référence aux figures 2A, 2B, et 2C, on fournit d’abord un substrat support 2 visible sur la figure 2A. According to a first embodiment of the roughening, with reference to FIGS. 2A, 2B, and 2C, a support substrate 2 visible in FIG. 2A is first provided.
On procède à la rugosification d’une surface libre 9 du substrat support, par gravure sélective. On obtient alors le substrat de la figure 2B. A free surface 9 of the support substrate is roughened by selective etching. The substrate of FIG. 2B is then obtained.
La gravure est dite « sélective » en ce que le silicium n’est pas attaqué de manière uniforme sur toute la surface du substrat, mais que des régions privilégiées de la surface (correspondant à des plans cristallins particuliers) sont attaquées plus rapidement que les autres régions. Etching is said to be “selective” in that the silicon is not attacked uniformly over the entire surface of the substrate, but that privileged regions of the surface (corresponding to particular crystalline planes) are attacked more quickly than the others. regions.
La gravure sélective est de préférence réalisée par voie sèche. L’acide chlorhydrique est tout particulièrement adapté à cet effet. Selective etching is preferably carried out dry. Hydrochloric acid is particularly suitable for this purpose.
On forme ensuite une couche de SiC 5 sur la surface gravée, comme illustré sur la figure 2C. A layer of SiC 5 is then formed on the etched surface, as illustrated in FIG. 2C.
Pour ce faire, selon un premier mode de réalisation, la surface gravée 9 est exposée à un gaz précurseur contenant des espèces chimiques carbonées. Ces dernières réagissent avec le silicium présent dans le substrat support, pour former du carbure de silicium SiC. La croissance de la couche de SiC se fait donc à partir de la surface rugosifiée, dans l’épaisseur du substrat support. De ce fait, la surface libre de la surface de la couche de SiC (qui était initialement la surface du substrat support de silicium) reste rugueuse. To do this, according to a first embodiment, the etched surface 9 is exposed to a precursor gas containing carbonaceous chemical species. The latter react with the silicon present in the support substrate, to form silicon carbide SiC. The growth of the SiC layer therefore takes place from the roughened surface, in the thickness of the support substrate. Therefore, the free surface of the surface of the SiC layer (which was initially the surface of the silicon support substrate) remains rough.
Les paramètres expérimentaux pour la formation de la couche SiC, tels que le temps d’exposition, la température réactionnelle, ou encore la nature du gaz précurseur, sont ajustés de manière à former une fine couche de SiC, de préférence d’une épaisseur inférieure ou égale à 5 nm. On préférera également que l’épaisseur de la couche de SiC soit supérieure ou égale à 1 nm. Compte tenu de la température appliquée, la couche de SiC présente avantageusement une structure polycristalline. The experimental parameters for the formation of the SiC layer, such as the exposure time, the reaction temperature, or even the nature of the precursor gas, are adjusted so as to form a thin layer of SiC, preferably of a lower thickness. or equal to 5 nm. It will also be preferred that the thickness of the SiC layer is greater than or equal to 1 nm. Given the temperature applied, the SiC layer advantageously has a polycrystalline structure.
La gravure est de préférence réalisée à une température comprise entre 700°C et 1300°C, à pression atmosphérique ou à une pression inférieure à la pression atmosphérique. On utilise de préférence l’acide chlorhydrique HCl sous forme gazeuse pour la gravure. The etching is preferably carried out at a temperature between 700 ° C and 1300 ° C, at atmospheric pressure or at a pressure below atmospheric pressure. Hydrochloric acid HCl is preferably used in gaseous form for etching.
Concernant la formation de la couche de SiC, celle-ci est de préférence réalisée à une température comprise entre 700°C et 1300°C, à une pression inférieure à la pression atmosphérique. On peut utiliser comme gaz précurseur notamment du propane ou du méthane dans de l’hydrogène. Le temps de la réaction est fonction de la quantité de gaz précurseur ; en effet, la réaction est auto-limitante c’est-à-dire que le gaz carboné réagit avec le silicium en surface du substrat support et la réaction s’arrête lorsqu’il n’y a plus de silicium en surface libre. Regarding the formation of the SiC layer, this is preferably carried out at a temperature between 700 ° C and 1300 ° C, at a pressure below atmospheric pressure. One can use as precursor gas in particular propane or methane in hydrogen. The reaction time is a function of the quantity of precursor gas; in fact, the reaction is self-limiting, that is to say that the carbonaceous gas reacts with the silicon on the surface of the support substrate and the reaction stops when there is no longer any silicon on the free surface.
Alternativement, selon un deuxième mode de réalisation, la couche de SiC est déposée sur la surface gravée par dépôt chimique en phase vapeur, communément appelé selon la terminologie anglaise « Chemical Vapor Déposition » et désigné sous l’acronyme CVD. La croissance de la couche de SiC se fait à partir de la surface rugosifiée, dans une direction opposée au substrat support. Ce mode de réalisation est moins préféré car, la couche de SiC étant déposée à une température plus basse que dans le précédent mode de réalisation, elle présente une structure amorphe. La couche de SiC est déposée de manière sensiblement homogène sur l’ensemble de la surface gravée, mais ce dépôt n’a pas pour effet de combler les cavités de la surface gravée, de sorte que la surface libre de la couche de SiC conserve au moins en partie la rugosité de la surface 9 sous-jacente. Alternatively, according to a second embodiment, the SiC layer is deposited on the etched surface by chemical vapor deposition, commonly called according to the English terminology "Chemical Vapor Deposition" and designated by the acronym CVD. The SiC layer grows from the roughened surface, in a direction opposite to the support substrate. This embodiment is less preferred because, the SiC layer being deposited at a lower temperature than in the previous embodiment, it has an amorphous structure. The SiC layer is deposited in a substantially homogeneous manner over the entire etched surface, but this deposition does not have the effect of filling the cavities of the etched surface, so that the free surface of the SiC layer retains less in part the roughness of the underlying surface 9.
Optionnellement, on dépose une couche de piégeage de charges 8 en silicium polycristallin sur la couche de SiC. Optionally, a charge trapping layer 8 of polycrystalline silicon is deposited on the SiC layer.
De manière particulièrement avantageuse, les étapes de gravure sélective, de formation de la couche de SiC et éventuellement de la couche de piégeage de charges sont réalisées dans un même bâti d’épitaxie, ce qui simplifie considérablement le procédé. De manière alternative, lesdites étapes peuvent être réalisées au moyen d’au moins deux équipements différents. In a particularly advantageous manner, the stages of selective etching, of formation of the SiC layer and possibly of the charge trapping layer are carried out in the same epitaxy frame, which considerably simplifies the process. Alternatively, said steps can be carried out using at least two different pieces of equipment.
On ne réalise pas d’opération de lissage ou planarisation de la couche de SiC formée. Un polissage mécano-chimique (CMP, acronyme du terme anglo-saxon « chemical-mechanical polishing ») par exemple, serait d’ailleurs impossible à réaliser du fait de la faible épaisseur de la couche de SiC. There is no smoothing or planarization operation of the SiC layer formed. A chemical mechanical polishing (CMP, acronym of the English term "chemical-mechanical polishing") for example, would be impossible to achieve due to the thinness of the SiC layer.
Selon un deuxième mode de réalisation de la rugosification, en référence aux figures 3A, 3B, et 3C, on fournit d’abord un substrat support visible sur la figure 3A. On procède alors à la rugosification de la surface libre 9 du substrat support, en deux étapes. Une première étape comprend la nucléation (ou germination) d’îlots de carbure de silicium 10 sur ladite surface supérieure. Pour ce faire, on expose d’abord la face supérieure 9 à un gaz précurseur contenant des espèces chimiques carbonées. Ces dernières réagissent avec le silicium présent dans le substrat support, pour former du carbure de silicium SiC. According to a second embodiment of the roughening, with reference to FIGS. 3A, 3B, and 3C, a support substrate visible in FIG. 3A is first provided. The free surface 9 of the support substrate is then roughened in two stages. A first step comprises the nucleation (or germination) of islands of silicon carbide 10 on said upper surface. To do this, the upper face 9 is first exposed to a precursor gas containing carbonaceous chemical species. The latter react with the silicon present in the support substrate, to form silicon carbide SiC.
Les îlots 10 sont obtenus en stoppant l’exposition aux espèces chimiques carbonées avant que les îlots ne coalescent et forment une couche de SiC continue sur la surface gravée. A l’issue de cette étape de nucléation, les îlots de SiC sont séparés les uns des autres par des zones 1 1 de silicium. The islets 10 are obtained by stopping the exposure to carbonaceous chemical species before the islets coalesce and form a continuous layer of SiC on the etched surface. At the end of this nucleation step, the SiC islets are separated from each other by 1 1 zones of silicon.
Dans une seconde étape du procédé de rugosification, on effectue ensuite une gravure sélective du substrat support. La gravure est dite « sélective » en ce que seules les zones de silicium sont gravées, tandis que les îlots 10 de SiC ne le sont pas. Les îlots de SiC jouent en effet le rôle d’un masque qui protège le matériau du substrat support sous-jacent de la gravure. La gravure sélective est de préférence réalisée par voie sèche. L’acide chlorhydrique est tout particulièrement adapté à cet effet. In a second step of the roughening process, a selective etching of the support substrate is then carried out. Etching is said to be “selective” in that only the silicon zones are etched, while the islands 10 of SiC are not. The SiC islands play the role of a mask which protects the material of the underlying support substrate from etching. Selective etching is preferably carried out dry. Hydrochloric acid is particularly suitable for this purpose.
Après gravure, on obtient le substrat de la figure 3B. After etching, the substrate of FIG. 3B is obtained.
Chaque îlot 10 comprend une portion du substrat support recouverte d’une couche de SiC, et est séparé des îlots adjacents par les zones 12 de silicium gravées, les îlots et les zones gravées formant ensemble une surface rugueuse du substrat support. Each island 10 comprises a portion of the support substrate covered with a layer of SiC, and is separated from the adjacent islands by the etched areas 12 of silicon, the islets and the etched areas together forming a rough surface of the support substrate.
On poursuit ensuite la formation de la couche de SiC (croissance) jusqu’à l’obtention d’une couche continue 5 de SiC, comme illustré sur la figure 3C. The formation of the SiC layer (growth) is then continued until a continuous layer 5 of SiC is obtained, as illustrated in FIG. 3C.
Pour ce faire, selon un premier mode de réalisation, la surface rugosifiée 9 est exposée à un gaz précurseur contenant des espèces chimiques carbonées. Ces dernières réagissent avec le silicium présent dans le substrat support, pour former du carbure de silicium SiC. To do this, according to a first embodiment, the roughened surface 9 is exposed to a precursor gas containing carbonaceous chemical species. The latter react with the silicon present in the support substrate, to form silicon carbide SiC.
Les paramètres expérimentaux pour la formation de la couche de SiC, tels que le temps d’exposition, la pression, la température réactionnelle, ou encore la nature du gaz précurseur, et le débit de gaz précurseur sont ajustés de manière à former une fine couche de SiC, de préférence d’une épaisseur inférieure ou égale à 5 nm. On préférera également que l’épaisseur de la couche de SiC soit supérieure ou égale à 1 nm. The experimental parameters for the formation of the SiC layer, such as the exposure time, the pressure, the reaction temperature, or even the nature of the precursor gas, and the flow of precursor gas are adjusted so as to form a thin layer. of SiC, preferably of a thickness less than or equal to 5 nm. It will also be preferred that the thickness of the SiC layer is greater than or equal to 1 nm.
La formation de la couche de SiC est de préférence réalisée à une température comprise entre 700°C et 1300°C, à une pression inférieure à la pression atmosphérique. Le temps de réaction est de préférence de l’ordre de quelques minutes pour des températures comprises dans la gamme précédente de 700°C à 1300°C. Le ratio de débit entre le gaz carboné et l’hydrogène influe sur les vitesses de germination et de croissance et sur l’épaisseur finale de la couche de SiC. Alternativement, la couche de SiC peut être déposée sur la surface rugosifiée par CVD comme décrit plus haut pour le premier mode de réalisation de la rugosification. The SiC layer is preferably formed at a temperature between 700 ° C and 1300 ° C, at a pressure below atmospheric pressure. The reaction time is preferably of the order of a few minutes for temperatures in the preceding range from 700 ° C to 1300 ° C. The flow ratio between carbonaceous gas and hydrogen influences the germination and growth rates and the final thickness of the SiC layer. Alternatively, the SiC layer can be deposited on the surface roughened by CVD as described above for the first embodiment of the roughening.
Optionnellement, on dépose une couche de piégeage de charges 8 en silicium polycristallin sur la couche de SiC. Optionally, a charge trapping layer 8 of polycrystalline silicon is deposited on the SiC layer.
De manière particulièrement avantageuse, les étapes de nucléation des îlots de SiC, de gravure sélective, de poursuite de la formation de la couche de SiC et éventuellement la formation de la couche de piégeage de charges sont réalisées dans un même bâti d’épitaxie, ce qui simplifie considérablement le procédé. In a particularly advantageous manner, the steps of nucleation of the SiC islets, of selective etching, of further formation of the SiC layer and possibly the formation of the charge trapping layer are carried out in the same epitaxy frame, this which greatly simplifies the process.
Quel que soit le mode de réalisation, après rugosification de la surface libre 9 du substrat support, on forme une couche de collage sur la couche de SiC, puis on transfère une couche électriquement isolante 3 et une couche monocristalline 4 sur la couche de collage, de sorte que la couche électriquement isolante se trouve à l’interface avec la couche de collage. Contrairement à la couche de SiC, la couche de collage présente une surface lisse adaptée pour assurer un collage de bonne qualité. Whatever the embodiment, after roughening of the free surface 9 of the support substrate, a bonding layer is formed on the SiC layer, then an electrically insulating layer 3 and a monocrystalline layer 4 are transferred to the bonding layer, so that the electrically insulating layer is at the interface with the bonding layer. Unlike the SiC layer, the bonding layer has a smooth surface suitable for ensuring good quality bonding.
La couche de collage permet d’assurer une bonne adhésion de la couche électriquement isolante 3 et de la couche monocristalline 4 sur la couche SiC 5. Il peut s’agir d’une couche d’oxyde de silicium, d’une couche adhésive, d’une colle, ou de tout autre moyen adapté à cet effet. The bonding layer ensures good adhesion of the electrically insulating layer 3 and of the monocrystalline layer 4 on the SiC layer 5. It may be a layer of silicon oxide, an adhesive layer, an adhesive, or any other suitable means for this purpose.
Selon un mode de réalisation préféré, le transfert est réalisé selon le procédé Smart Cut™ bien connu en soi, dont les principales étapes sont rappelées ci-après. According to a preferred embodiment, the transfer is carried out according to the Smart Cut ™ method well known per se, the main steps of which are recalled below.
On fournit un premier substrat, dit substrat receveur, qui comprend le substrat support 2, la couche de carbure de silicium SiC 5, et la couche de collage. Optionnellement, le substrat receveur comprend une couche de piégeage de charges 8 sur la couche de SiC, et la couche de collage est agencée sur la couche de piégeage de charges. On fournit également un second substrat, dit substrat donneur. A first substrate is provided, called the receiving substrate, which comprises the support substrate 2, the layer of silicon carbide SiC 5, and the bonding layer. Optionally, the receiving substrate comprises a charge trapping layer 8 on the SiC layer, and the bonding layer is arranged on the charge trapping layer. A second substrate is also provided, called the donor substrate.
On forme une zone de fragilisation dans le substrat donneur, de sorte à délimiter une couche monocristalline 4. La zone de fragilisation est formée dans le substrat donneur à une profondeur prédéterminée qui correspond sensiblement à l’épaisseur de la couche monocristalline à transférer. A weakening zone is formed in the donor substrate, so as to delimit a monocrystalline layer 4. The weakening zone is formed in the donor substrate at a predetermined depth which corresponds substantially to the thickness of the monocrystalline layer to be transferred.
De préférence, la zone de fragilisation est créée par implantation d’atomes et/ou d’ions d’hydrogène et/ou d’hélium dans le substrat donneur. Preferably, the weakening zone is created by implantation of atoms and / or ions of hydrogen and / or helium in the donor substrate.
On colle ensuite le substrat donneur sur le substrat receveur. The donor substrate is then bonded to the recipient substrate.
Une couche électriquement isolante 3 est agencée entre le substrat support 2 et la couche monocristalline 4. An electrically insulating layer 3 is arranged between the support substrate 2 and the monocrystalline layer 4.
Selon un premier mode de réalisation, la couche électriquement isolante 3 est sur le substrat receveur, agencée sur la couche SiC 5 ou, lorsque présente, sur la couche de piégeage de charges 8. La couche monocristalline 4 est collée sur la couche électriquement isolante 3 et se trouve donc à l’interface de collage. Selon un deuxième mode de réalisation, la couche électriquement isolante 3 est sur le substrat donneur. A la fois la couche monocristalline 4 et la couche électriquement isolante 3 sont collées sur la couche de SiC par l’intermédiaire de la couche de collage. La couche électriquement isolante 3 se trouve donc à l’interface de collage. According to a first embodiment, the electrically insulating layer 3 is on the receiving substrate, arranged on the SiC layer 5 or, when present, on the charge trapping layer 8. The monocrystalline layer 4 is bonded to the electrically insulating layer 3 and is therefore at the bonding interface. According to a second embodiment, the electrically insulating layer 3 is on the donor substrate. Both the monocrystalline layer 4 and the electrically insulating layer 3 are bonded to the SiC layer via the bonding layer. The electrically insulating layer 3 is therefore located at the bonding interface.
Le procédé de transfert de couche n’est cependant pas limité au procédé Smart The layer transfer process is not however limited to the Smart process
Cut™ ; ainsi, il pourra consister par exemple à coller le substrat donneur sur le substrat receveur puis à amincir le substrat donneur par sa face opposée au substrat receveur jusqu’à l’obtention de l’épaisseur souhaitée pour la couche monocristalline. Cut ™; thus, it could consist, for example, of sticking the donor substrate to the recipient substrate and then thinning the donor substrate by its face opposite to the recipient substrate until the desired thickness for the monocrystalline layer is obtained.
Les substrats SOI 1 obtenus après transfert selon le premier mode de réalisation et le deuxième mode de réalisation, sont représentés respectivement sur les figures 4 et 5. The SOI 1 substrates obtained after transfer according to the first embodiment and the second embodiment, are shown respectively in FIGS. 4 and 5.
Selon un mode de réalisation, la couche monocristalline 4 comprend un matériau ferroélectrique. According to one embodiment, the monocrystalline layer 4 comprises a ferroelectric material.
Le matériau ferroélectrique est avantageusement choisi parmi : LiTa03, LiNb03, LiAI03, BaTi03, PbZrTi03, KNb03, BaZr03, CaTi03, PbTi03 ou de KTa03. The ferroelectric material is advantageously chosen from: LiTa0 3 , LiNb0 3 , LiAI0 3 , BaTi0 3 , PbZrTi0 3 , KNb0 3 , BaZr0 3 , CaTi0 3 , PbTi0 3 or KTa0 3 .
Le substrat donneur de ladite couche monocristalline peut avantageusement prendre la forme d'une plaquette, circulaire, de dimension normalisée, par exemple de 150 mm ou 200 mm de diamètre. L’invention n'est cependant nullement limitée à ces dimensions ou à cette forme. Cette plaquette peut avoir été prélevée d'un lingot de matériau ferroélectrique, ce prélèvement ayant été réalisé de manière à former un substrat donneur présentant une orientation cristalline prédéterminée. De manière alternative, le substrat donneur peut comprendre une couche de matériau ferroélectrique assemblée à un substrat support. The donor substrate of said monocrystalline layer can advantageously take the form of a circular wafer of standardized size, for example 150 mm or 200 mm in diameter. The invention is however not limited to these dimensions or this shape. This wafer may have been taken from an ingot of ferroelectric material, this taking having been carried out so as to form a donor substrate having a predetermined crystal orientation. Alternatively, the donor substrate may include a layer of ferroelectric material joined to a support substrate.
L'orientation cristalline de la couche monocristalline de matériau ferroélectrique à transférer est choisie en fonction de l'application visée. Ainsi, en ce qui concerne le matériau LiTa03, il est usuel de choisir une orientation comprise entre 30° et 60°XY, ou entre 40° et 50°XY, en particulier dans le cas où l'on souhaite exploiter les propriétés de la couche mince pour former un filtre SAW (« Surface Acoustic Wave » en anglais). En ce qui concerne le matériau LiNb03 il est usuel de choisir une orientation autour de 128° XY. Mais l'invention n’est nullement limitée à une orientation cristalline particulière. The crystalline orientation of the monocrystalline layer of ferroelectric material to be transferred is chosen according to the intended application. Thus, with regard to the LiTa0 3 material, it is usual to choose an orientation of between 30 ° and 60 ° XY, or between 40 ° and 50 ° XY, in particular in the case where it is wished to exploit the properties of the thin layer to form a SAW filter (“Surface Acoustic Wave” in English). As regards the LiNb0 3 material, it is usual to choose an orientation around 128 ° XY. However, the invention is in no way limited to a particular crystalline orientation.
Quelle que soit l’orientation cristalline du matériau ferroélectrique de la couche monocristalline 4, le procédé comprend par exemple l'introduction d'espèces (ions et/ou atomes) d'hydrogène et/ou d'hélium dans le substrat donneur. Cette introduction peut par exemple correspondre à une implantation d'hydrogène, c’est-à-dire un bombardement ionique d'hydrogène de la face plane du substrat donneur. Whatever the crystalline orientation of the ferroelectric material of the monocrystalline layer 4, the method comprises for example the introduction of species (ions and / or atoms) of hydrogen and / or helium into the donor substrate. This introduction may for example correspond to an implantation of hydrogen, that is to say an ion bombardment of hydrogen from the flat face of the donor substrate.
De façon connue en soi, les atomes ou ions implantés ont pour but de former un plan de fragilisation délimitant une première couche de matériau ferroélectrique à transférer et une autre partie formant le reste du substrat. La nature, la dose des espèces implantées et le type des espèces implantées ainsi que l'énergie d'implantation sont choisies en fonction de l'épaisseur de la couche à transférer et des propriétés physico chimiques du substrat donneur. Dans le cas d'un substrat donneur en LiTa03, on pourra tout particulièrement choisir d'implanter une dose d’hydrogène comprise entre 1 E16 et 5E17 at/cm2 avec une énergie comprise entre 30 et 300 keV pour délimiter une première couche de l'ordre de 20 à 2000 nm d’épaisseur. In a manner known per se, the atoms or ions implanted are intended to form a weakening plane delimiting a first layer of ferroelectric material to be transferred and another part forming the rest of the substrate. The nature, the dose of the implanted species and the type of the implanted species as well as the implantation energy are chosen according to the thickness of the layer to be transferred and the physico-chemical properties of the donor substrate. In the case of a donor substrate of LiTa0 3 , it will be possible particularly to choose to implant a dose of hydrogen of between 1 E16 and 5E17 at / cm 2 with an energy of between 30 and 300 keV to delimit a first layer of around 20 to 2000 nm thick.
EXEMPLE : mesure de la résistivité électrique EXAMPLE: measurement of electrical resistivity
On fournit initialement deux substrats. Two substrates are initially provided.
Un premier substrat a été fabriqué par dépôt d’une couche de SiC sur un substrat support dont la surface libre est lisse, c’est-à-dire sans réalisation d’une gravure préalable, puis transfert d’une couche électriquement isolante et d’une couche monocristalline sur la couche de SiC. La surface supérieure de la couche de SiC, du côté de la couche électriquement isolante, est donc lisse. A first substrate was manufactured by depositing a layer of SiC on a support substrate whose free surface is smooth, that is to say without carrying out a prior etching, then transfer of an electrically insulating layer and d 'a monocrystalline layer on the SiC layer. The upper surface of the SiC layer, on the side of the electrically insulating layer, is therefore smooth.
Un deuxième substrat a été fabriqué selon l’un des deux modes de réalisation du procédé de fabrication décrits précédemment. Ce deuxième substrat comprend donc un substrat support, une couche de SiC dont la surface supérieure est rugueuse, ainsi qu’une couche électriquement isolante et une couche monocristalline agencées sur la couche de SiC rugueuse. A second substrate was manufactured according to one of the two embodiments of the manufacturing process described above. This second substrate therefore comprises a support substrate, a layer of SiC whose top surface is rough, as well as an electrically insulating layer and a monocrystalline layer arranged on the layer of rough SiC.
On mesure la résistivité électrique de chacun des deux substrats, par exemple par la méthode des quatre pointes. The electrical resistivity of each of the two substrates is measured, for example by the four-point method.
La figure 6 représente l’évolution de la résistivité électrique R (en ohm. cm) des substrats en fonction de leur profondeur P (en pm) à partir de la surface de la couche monocristalline pour le premier substrat dont la couche de SiC est lisse (courbe C1 ), et pour le deuxième substrat dont la couche de SiC est rugueuse (courbe C2). FIG. 6 represents the evolution of the electrical resistivity R (in ohm. Cm) of the substrates as a function of their depth P (in pm) from the surface of the monocrystalline layer for the first substrate whose SiC layer is smooth (curve C1), and for the second substrate whose SiC layer is rough (curve C2).
Concernant la courbe C1 , la résistivité chute fortement depuis la surface libre du substrat jusqu’à une profondeur légèrement inférieure à 1 pm qui correspond à la profondeur de la couche de SiC, pour atteindre une valeur minimale d’environ 5 Q.cm. Regarding the curve C1, the resistivity drops sharply from the free surface of the substrate to a depth slightly less than 1 μm which corresponds to the depth of the SiC layer, to reach a minimum value of approximately 5 Q.cm.
Concernant la courbe C2, la résistivité chute beaucoup moins que pour la courbe 1 , depuis la surface libre du substrat jusqu’à une profondeur légèrement inférieure à 1 pm, pour atteindre une valeur minimale d’environ 90 Q.cm. Concerning curve C2, the resistivity drops much less than for curve 1, from the free surface of the substrate to a depth slightly less than 1 pm, to reach a minimum value of around 90 Q.cm.
Ces courbes montrent que la couche de SiC rugueuse permet de limiter l’effet de l’interface entre le substrat support et la couche de piégeage. Plus la chute de résistivité à l’interface est importante, plus cette chute a un impact négatif sur les performances globales de piégeage de la couche de SiC. These curves show that the rough SiC layer makes it possible to limit the effect of the interface between the support substrate and the trapping layer. The greater the drop in resistivity at the interface, the more this drop has a negative impact on the overall trapping performance of the SiC layer.

Claims

REVENDICATIONS
1. Substrat (1 ) de type semi-conducteur sur isolant pour des applications 1. Substrate (1) of semiconductor type on insulator for applications
radiofréquences, comprenant : radio frequencies, including:
- un substrat support (2) en silicium, - a silicon support substrate (2),
- une couche électriquement isolante (3) agencée sur le substrat support, - an electrically insulating layer (3) arranged on the support substrate,
- une couche monocristalline (4) agencée sur la couche électriquement isolante, - a monocrystalline layer (4) arranged on the electrically insulating layer,
le substrat (1 ) étant caractérisé en ce qu’il comprend en outre une couche de carbure de silicium SiC (5) agencée entre le substrat support (2) et la couche électriquement isolante (3), qui présente une épaisseur comprise entre 1 nm et 5 nm, la surface (6) de la couche de carbure de silicium SiC qui est du côté de la couche électriquement isolante (3) étant rugueuse. the substrate (1) being characterized in that it further comprises a layer of silicon carbide SiC (5) arranged between the support substrate (2) and the electrically insulating layer (3), which has a thickness of between 1 nm and 5 nm, the surface (6) of the layer of silicon carbide SiC which is on the side of the electrically insulating layer (3) being rough.
2. Substrat selon la revendication 1 , dans lequel la couche monocristalline (4) est de type semi-conducteur. 2. The substrate according to claim 1, in which the monocrystalline layer (4) is of the semiconductor type.
3. Substrat selon la revendication 1 , dans lequel la couche monocristalline (4) comprend un matériau ferroélectrique. 3. The substrate according to claim 1, wherein the monocrystalline layer (4) comprises a ferroelectric material.
4. Substrat selon la revendication 3, dans lequel le matériau ferroélectrique est choisi parmi : LiTa03, LiNb03, LiAI03, BaTi03, PbZrTi03, KNb03, BaZr03, CaTi03, PbTi03, KTa03. 4. Substrate according to claim 3, in which the ferroelectric material is chosen from: LiTa0 3 , LiNb0 3 , LiAI0 3 , BaTi0 3 , PbZrTi0 3 , KNb0 3 , BaZr0 3 , CaTi0 3 , PbTi0 3 , KTa0 3 .
5. Substrat selon l’une des revendications précédentes, dans lequel ladite surface (6) de la couche de carbure de silicium (5) présente une rugosité supérieure ou égale à 10 nm RMS, de préférence supérieure ou égale à 100 nm RMS. 5. Substrate according to one of the preceding claims, in which said surface (6) of the silicon carbide layer (5) has a roughness greater than or equal to 10 nm RMS, preferably greater than or equal to 100 nm RMS.
6. Substrat selon l’une des revendications précédentes, comprenant en outre une couche de piégeage de charges (8) en silicium polycristallin agencée entre la couche de carbure de silicium (5) et la couche électriquement isolante (3). 6. Substrate according to one of the preceding claims, further comprising a charge trapping layer (8) of polycrystalline silicon arranged between the layer of silicon carbide (5) and the electrically insulating layer (3).
7. Substrat selon l’une des revendications précédentes, dans lequel le substrat support (1 ) est monocristallin. 7. Substrate according to one of the preceding claims, in which the support substrate (1) is monocrystalline.
8. Substrat selon l’une des revendications précédentes, dans lequel la couche électriquement isolante (3) est une couche d’oxyde de silicium. 8. Substrate according to one of the preceding claims, in which the electrically insulating layer (3) is a layer of silicon oxide.
9. Procédé de fabrication d’un substrat (1 ) de type semi-conducteur sur isolant pour des applications radiofréquences, caractérisé en ce qu’il comprend les étapes suivantes : 9. Method of manufacturing a substrate (1) of semiconductor on insulator type for radiofrequency applications, characterized in that it comprises the following steps:
- fourniture d’un substrat support (2) en silicium, - supply of a silicon support substrate (2),
- rugosification d’une surface libre (9) du substrat support (2) par gravure sélective, - roughening of a free surface (9) of the support substrate (2) by selective etching,
- formation d’une couche de carbure de silicium (5) sur la surface rugosifiée (9), la surface de la couche de carbure de silicium qui est du côté opposé au substrat support (2) étant rugueuse, - formation of a layer of silicon carbide (5) on the roughened surface (9), the surface of the layer of silicon carbide which is on the side opposite to the support substrate (2) being rough,
- formation d’une couche de collage sur la surface rugueuse de la couche de carbure de silicium (5), - formation of a bonding layer on the rough surface of the silicon carbide layer (5),
- transfert d’une couche électriquement isolante (3) et d’une couche monocristalline (4) sur la couche de collage, la couche électriquement isolante (3) étant à l’interface avec la couche de collage. - transfer of an electrically insulating layer (3) and a monocrystalline layer (4) onto the bonding layer, the electrically insulating layer (3) being at the interface with the bonding layer.
10. Procédé de fabrication selon la revendication 9, dans lequel la couche monocristalline (4) est de type semi-conducteur. 10. The manufacturing method according to claim 9, wherein the monocrystalline layer (4) is of the semiconductor type.
1 1. Procédé de fabrication selon la revendication 9, dans lequel la couche monocristalline (4) comprend un matériau ferroélectrique. 1 1. The manufacturing method according to claim 9, wherein the monocrystalline layer (4) comprises a ferroelectric material.
12. Procédé de fabrication selon la revendication 1 1 , dans lequel le matériau ferroélectrique est choisi parmi : LiTa03, LiNb03, LiAI03, BaTi03, PbZrTi03,12. The manufacturing method according to claim 1 1, in which the ferroelectric material is chosen from: LiTa0 3 , LiNb0 3 , LiAI0 3 , BaTi0 3 , PbZrTi0 3 ,
KNb03, BaZr03, CaTi03, PbTi03, KTa03. KNb0 3 , BaZr0 3 , CaTi0 3 , PbTi0 3 , KTa0 3 .
13. Procédé de fabrication selon l’une des revendications 9 à 12, dans lequel l’étape de rugosification comprend une gravure sélective selon des plans cristallins de la surface libre (9) du substrat support (2). 13. The manufacturing method according to one of claims 9 to 12, wherein the roughening step comprises selective etching along crystalline planes of the free surface (9) of the support substrate (2).
14. Procédé de fabrication selon l’une des revendications 9 à 12, dans lequel l’étape de rugosification comprend : 14. The manufacturing method according to one of claims 9 to 12, in which the roughening step comprises:
- la nucléation d’îlots (10) de carbure de silicium sur la surface libre (9) du substrat support (2) par exposition de ladite surface libre à un gaz précurseur contenant des espèces chimiques carbonées qui engendre une réaction desdites espèces chimiques carbonées avec du silicium du substrat support - nucleation of islands (10) of silicon carbide on the free surface (9) of the support substrate (2) by exposure of said free surface to a precursor gas containing carbonaceous chemical species which generates a reaction of said carbonaceous chemical species with support substrate silicon
(1 ), (1),
- la gravure sélective des zones (11 ) de la surface libre du substrat support séparant les îlots. - selective etching of the areas (11) of the free surface of the support substrate separating the islands.
15. Procédé de fabrication selon la revendication 13 ou la revendication 14, dans lequel la gravure sélective est réalisée par voie sèche. 15. The manufacturing method according to claim 13 or claim 14, wherein the selective etching is carried out dry.
16. Procédé de fabrication selon la revendication 15, dans lequel la gravure sélective par voie sèche est réalisée avec de l’acide chlorhydrique. 16. The manufacturing method according to claim 15, wherein the selective dry etching is carried out with hydrochloric acid.
17. Procédé de fabrication selon l’une des revendications 9 à 16, dans lequel la couche de carbure de silicium (5) est formée par exposition de ladite surface rugosifiée à un gaz précurseur contenant des espèces chimiques carbonées qui engendre une réaction desdites espèces chimiques carbonées avec du silicium du substrat support (2). 17. The manufacturing method according to one of claims 9 to 16, wherein the silicon carbide layer (5) is formed by exposure of said roughened surface to a precursor gas containing carbonaceous chemical species which generates a reaction of said chemical species carbonaceous with silicon of the support substrate (2).
18. Procédé de fabrication selon l’une des revendications 9 à 17, dans lequel la couche de carbure de silicium (5) sur la surface rugosifiée (9) du substrat support est formée par dépôt chimique en phase vapeur. 18. The manufacturing method according to one of claims 9 to 17, wherein the layer of silicon carbide (5) on the roughened surface (9) of the support substrate is formed by chemical vapor deposition.
19. Procédé de fabrication selon l’une des revendications 9 à 18, comprenant en outre, avant le transfert de la couche électriquement isolante (3) et de la couche monocristalline (4), le dépôt d’une couche de piégeage de charges (8) en silicium polycristallin sur la couche de carbure de silicium (5). 19. Manufacturing process according to one of claims 9 to 18, further comprising, before the transfer of the electrically insulating layer (3) and the monocrystalline layer (4), the deposition of a charge trapping layer ( 8) in polycrystalline silicon on the layer of silicon carbide (5).
20. Procédé selon l’une des revendications 9 à 18, dans lequel l’étape de 20. Method according to one of claims 9 to 18, wherein the step of
transfert comprend : transfer includes:
- la fourniture d’un substrat donneur recouvert d’une couche électriquement isolante (3), - the supply of a donor substrate covered with an electrically insulating layer (3),
- la formation d’une zone de fragilisation dans le substrat donneur, de sorte à délimiter une couche monocristalline (4), - the formation of a weakening zone in the donor substrate, so as to delimit a monocrystalline layer (4),
- le collage du substrat donneur sur le substrat support (2) par l’intermédiaire de la couche électriquement isolante (3) et de la couche de collage, - the bonding of the donor substrate to the support substrate (2) via the electrically insulating layer (3) and the bonding layer,
- le détachement du substrat donneur le long de la zone de fragilisation, de sorte à transférer la couche monocristalline (4) sur le substrat support (2). - detachment of the donor substrate along the embrittlement zone, so as to transfer the monocrystalline layer (4) onto the support substrate (2).
EP19848883.5A 2018-12-21 2019-12-19 Substrate of the semi-conductor-on-insulator type for radiofrequency applications Pending EP3900029A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1873888A FR3091011B1 (en) 2018-12-21 2018-12-21 SEMICONDUCTOR SUBSTRATE ON INSULATION FOR RADIO FREQUENCY APPLICATIONS
PCT/FR2019/053192 WO2020128354A1 (en) 2018-12-21 2019-12-19 Substrate of the semi-conductor-on-insulator type for radiofrequency applications

Publications (1)

Publication Number Publication Date
EP3900029A1 true EP3900029A1 (en) 2021-10-27

Family

ID=67185145

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19848883.5A Pending EP3900029A1 (en) 2018-12-21 2019-12-19 Substrate of the semi-conductor-on-insulator type for radiofrequency applications

Country Status (8)

Country Link
US (1) US20220076991A1 (en)
EP (1) EP3900029A1 (en)
JP (1) JP7342330B2 (en)
KR (1) KR20210105403A (en)
CN (1) CN113196461A (en)
FR (1) FR3091011B1 (en)
SG (1) SG11202105731RA (en)
WO (1) WO2020128354A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3104318B1 (en) * 2019-12-05 2023-03-03 Soitec Silicon On Insulator METHOD FOR FORMING A HIGH STRENGTH HANDLING SUPPORT FOR COMPOSITE SUBSTRATE
FR3116151A1 (en) * 2020-11-10 2022-05-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives METHOD FOR FORMING A USEFUL SUBSTRATE TRAPPING STRUCTURE
CN117750868A (en) * 2024-02-20 2024-03-22 北京青禾晶元半导体科技有限责任公司 Composite piezoelectric substrate and preparation method thereof

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5264387A (en) * 1992-10-27 1993-11-23 International Business Machines Corporation Method of forming uniformly thin, isolated silicon mesas on an insulating substrate
US20090152684A1 (en) * 2007-12-18 2009-06-18 Li-Peng Wang Manufacture-friendly buffer layer for ferroelectric media
JP5942948B2 (en) 2013-09-17 2016-06-29 信越半導体株式会社 Manufacturing method of SOI wafer and bonded SOI wafer
US9711521B2 (en) * 2015-08-31 2017-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Substrate fabrication method to improve RF (radio frequency) device performance
EP3144958B1 (en) * 2015-09-17 2021-03-17 Soitec Structure for radiofrequency applications and process for manufacturing such a structure
US9831115B2 (en) * 2016-02-19 2017-11-28 Sunedison Semiconductor Limited (Uen201334164H) Process flow for manufacturing semiconductor on insulator structures in parallel
WO2017142849A1 (en) * 2016-02-19 2017-08-24 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a buried high resistivity layer
FR3048306B1 (en) 2016-02-26 2018-03-16 Soitec SUPPORT FOR A SEMICONDUCTOR STRUCTURE

Also Published As

Publication number Publication date
US20220076991A1 (en) 2022-03-10
WO2020128354A1 (en) 2020-06-25
CN113196461A (en) 2021-07-30
SG11202105731RA (en) 2021-07-29
KR20210105403A (en) 2021-08-26
FR3091011B1 (en) 2022-08-05
JP2022510822A (en) 2022-01-28
JP7342330B2 (en) 2023-09-12
FR3091011A1 (en) 2020-06-26

Similar Documents

Publication Publication Date Title
EP1008169B1 (en) Producing microstructures or nanostructures on a support
EP3900029A1 (en) Substrate of the semi-conductor-on-insulator type for radiofrequency applications
EP0801419A1 (en) Process of making a thin semiconductor film comprising electronic devices
EP3577683B1 (en) Structure for a radio frequency application
WO2007020351A1 (en) Method of transferring a thin film onto a support
EP1938362A1 (en) Method for making a thin-film element
FR2973159A1 (en) METHOD FOR MANUFACTURING A BASE SUBSTRATE FOR A SEMICONDUCTOR TYPE SUBSTRATE ON INSULATION
FR2845523A1 (en) METHOD FOR MAKING A SUBSTRATE BY TRANSFERRING A DONOR WAFER HAVING FOREIGN SPECIES, AND ASSOCIATED DONOR WAFER
WO2020008116A1 (en) Substrate for an integrated radiofrequency device, and process for manufacturing same
EP1829100A1 (en) Method for transferring a circuit to a grounding plane
FR2896338A1 (en) Production of monocrystalline material on a dielectric material, comprises forming a partially crystalline first layer, and forming an amorphous/partially crystalline second layer of first material on the partially crystalline first layer
FR2946478A1 (en) RESONATOR WITH VOLUME WAVES.
FR3117668A1 (en) IMPROVED RF SUBSTRATE STRUCTURE AND METHOD OF MAKING
EP1337683B1 (en) Method for automatic organisation of microstructures or nanostructures and related device obtained
WO2021008742A1 (en) Method for manufacturing a structure comprising a thin layer transferred onto a support provided with a charge-trapping layer
EP0085607A2 (en) Process for the simultaneous production of hyperfrequency diodes having an incorported encapsulation and diodes made by said process
WO2021140300A1 (en) Method for manufacturing a semiconductor-on-insulator structure for radiofrequency applications
WO2020136343A1 (en) Semiconductor structure for digital and radiofrequency applications
FR3104318A1 (en) METHOD FOR FORMING A HIGH STRENGTH HANDLING SUPPORT FOR COMPOSITE SUBSTRATE
EP2259304A1 (en) Manufacturing method of one level of a tridimensional integrated circuits by tridimensional sequential integration
WO2020144438A1 (en) Process for producing a receiver substrate for a semiconductor-on-insulator structure for radiofrequency applications and process for producing such a structure
WO2021234277A1 (en) Method for manufacturing a semiconductor-on-insulator substrate for radiofrequency applications
FR3118828A1 (en) Process for direct bonding of substrates
FR3027451A1 (en) SUBSTRATE AND METHOD FOR MANUFACTURING SUBSTRATE
WO2024084179A1 (en) Process for manufacturing a piezoelectric layer on a substrate

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: UNKNOWN

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20210707

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

DAV Request for validation of the european patent (deleted)
DAX Request for extension of the european patent (deleted)