JP5942948B2 - Manufacturing method of SOI wafer and bonded SOI wafer - Google Patents

Description

  The present invention relates to an SOI wafer manufacturing method and a bonded SOI wafer.

  As an SOI wafer for RF (Radio Frequency) devices, it has been dealt with by increasing the resistivity of the base wafer. However, it has become necessary to cope with higher frequencies in order to cope with further increase in speed, and it has become impossible to cope only with the use of conventional high-resistance wafers.

  Therefore, as a countermeasure, it has been proposed to add a layer (carrier trap layer) having an effect of eliminating generated carriers directly under the buried oxide film layer (BOX layer) of the SOI wafer, which is generated in the high resistance wafer. It has become necessary to form a high-resistance polycrystalline silicon layer on the base wafer for recombination of carriers.

Patent Document 1 describes that a polycrystalline silicon layer or an amorphous silicon layer as a carrier trap layer is formed at the interface between a BOX layer and a base wafer.
On the other hand, Patent Document 2 also describes that a polycrystalline layer as a carrier trap layer is formed at the interface between the BOX layer and the base wafer. Further, in order to prevent recrystallization of the polycrystalline silicon layer, The heat treatment temperature after the formation of the polycrystalline silicon layer is limited.
Patent Document 3 does not describe the formation of a polycrystalline silicon layer or an amorphous silicon layer as a carrier trap layer, but increases the surface roughness of the base wafer surface to be bonded to the bond wafer. By doing so, it is described that the same effect as the carrier trap layer is obtained.

Special table 2007-507093 Special table 2013-513234 gazette JP 2010-278160 A

As described above, it is necessary to form a carrier trap layer under the BOX layer of the SOI wafer in order to manufacture a device corresponding to a higher frequency.
However, when a normal polycrystalline silicon layer is deposited to form a carrier trap layer, the polycrystalline silicon layer is annealed and single-crystallized depending on the thermal history during the SOI wafer manufacturing process or device manufacturing process, and the effect as a carrier trap layer is obtained. There was a problem that it decreased.
Therefore, it is necessary to prevent the single crystallization from proceeding even if the heat treatment is performed after the polycrystalline silicon layer is deposited. In other words, a polycrystalline silicon layer or an amorphous silicon layer is deposited so that the cost is low and the effect does not proceed even if the heat treatment process of the SOI wafer manufacturing process or the heat treatment process of the device manufacturing process does not proceed. There is a need.
However, none of the above Patent Documents 1-3 discloses or suggests a technique for preventing the single crystallization from proceeding even if the heat treatment is performed after the deposition of the polycrystalline silicon layer.

  The present invention has been made in view of the above-described problems, and a polycrystalline silicon layer or an amorphous material is used so that single crystallization does not proceed even through a heat treatment step of an SOI wafer manufacturing step or a heat treatment step of a device manufacturing step. An object of the present invention is to provide an SOI wafer manufacturing method capable of depositing a quality silicon layer.

  In order to achieve the above object, the present invention is a method of manufacturing a bonded SOI wafer by bonding a bond wafer made of silicon single crystal and a base wafer through an insulating film, and includes at least the base Forming a polycrystalline silicon layer or an amorphous silicon layer on the bonding surface side of the wafer, at least one of the surface of the polycrystalline silicon layer or the amorphous silicon layer, and the bonding surface of the bond wafer; The step of forming the insulating film, the step of bonding the base wafer and the bond wafer through the insulating film, and the step of forming a SOI layer by thinning the bonded bond wafer, The base wafer has a resistivity of 100 Ω · cm or more, and the polycrystalline silicon layer or the amorphous silicon layer Surface roughness of the forming surface (RMS) to provide a method for manufacturing an SOI wafer, comprising the use of more than 2 nm.

  With such a method for manufacturing an SOI wafer, a polycrystalline silicon layer or an amorphous silicon layer is deposited so that the single crystallization does not proceed even through the heat treatment process of the SOI wafer manufacturing process and the heat treatment process of the device manufacturing process. Therefore, it is possible to suppress the polycrystalline silicon layer from being single-crystallized by heat treatment and reducing the effect as a carrier trap layer.

At this time, it is preferable to use the base wafer having a surface roughness of 10 nm or less on the surface on which the polycrystalline silicon layer or the amorphous silicon layer is formed.
With such a surface roughness, it is possible to suppress a load from being applied to the step of polishing the polycrystalline silicon layer or the amorphous silicon layer for performing good bonding with the bond wafer.

At this time, as the base wafer, a separation wafer derived when a bonded SOI wafer is produced by an ion implantation separation method is used, and the polycrystalline silicon layer or the amorphous silicon layer is formed on the separation surface of the separation wafer. It is preferable.
Thus, by using a release wafer as a base wafer, the surface roughness of one surface of the base wafer can be made desired, and a flattening process such as polishing is not performed on the release surface of the release wafer. It can be used as it is as a base wafer.

At this time, it is preferable that the surface of the base wafer on which the polycrystalline silicon layer or the amorphous silicon layer is formed is an etched surface on which wet etching or dry etching is performed.
In this way, the surface roughness of the surface on which the polycrystalline silicon layer or the amorphous silicon layer of the base wafer is formed can be made desired.

At this time, the step of forming the SOI layer by thinning the bond wafer is preferably performed by an ion implantation separation method.
By the ion implantation separation method, the SOI layer can be formed by suitably thinning the bond wafer.

  Further, the present invention is a bonded SOI wafer in which a polycrystalline layer or an amorphous layer, an insulating film, and an SOI layer are sequentially formed on a base wafer made of a silicon single crystal, and the base wafer includes: The resistivity is 100 Ω · cm or more, the surface roughness (RMS) of the interface between the base wafer and the polycrystalline layer or the amorphous layer is 2 nm or more, and the polycrystalline layer or the amorphous layer A bonded SOI wafer is characterized in that the ratio of the <111> component in the sum of the orientation components of <220>, <311>, and <111> is 40% or less.

  With such a bonded SOI wafer, it is possible to suppress the polycrystalline silicon layer or the amorphous silicon layer from being single-crystallized by heat treatment and reducing the effect as a carrier trap layer, and a higher frequency. It is possible to make an SOI wafer compatible with RF devices.

At this time, the surface roughness of the interface between the base wafer and the polycrystalline layer or the amorphous layer is preferably 10 nm or less.
With such a surface roughness, it is possible to suppress a load from being applied to the step of polishing the polycrystalline silicon layer or the amorphous silicon layer for performing good bonding with the bond wafer.

  As described above, according to the present invention, as the base wafer, an SOI substrate having a high resistance and a surface roughness of a surface on which a polycrystalline silicon layer or an amorphous silicon layer is formed is 2 nm or more. Since the polycrystalline silicon layer or the amorphous silicon layer can be deposited so that the single crystallization does not proceed even through the heat treatment process of the wafer manufacturing process and the heat treatment process of the device manufacturing process, the polycrystalline silicon layer or the amorphous silicon layer can be deposited. It can be suppressed that the crystalline silicon layer is monocrystallized by heat treatment and the effect as the carrier trap layer is reduced. As a result, an SOI wafer for an RF device that can cope with a high frequency can be manufactured.

It is a flowchart which shows the manufacturing method of the SOI wafer of this invention. It is a flowchart which shows the manufacturing method of the SOI wafer of this invention at the time of using an ion implantation peeling method. It is a figure which shows the relationship between <111> content rate and resistivity of a polycrystalline silicon layer. It is a figure which shows the relationship between the surface roughness (RMS) of a base wafer, and the <111> content rate of a polycrystalline silicon layer. It is a figure which shows the relationship between the surface roughness (RMS) of a base wafer, and the resistivity of a polycrystalline silicon layer.

Hereinafter, the present invention will be described in detail as an example of an embodiment with reference to the drawings, but the present invention is not limited thereto.
As described above, in order to fabricate a device corresponding to a higher frequency, it is necessary to form a carrier trap layer under the BOX layer of the SOI wafer. When the trap layer is formed, there is a problem that the polycrystalline silicon layer is annealed and single-crystallized due to the thermal history during the SOI wafer manufacturing process or the device manufacturing process, and the effect as the carrier trap layer is reduced.

Therefore, the inventors can deposit a polycrystalline silicon layer or an amorphous silicon layer so that single crystallization does not proceed even if a heat treatment process of an SOI wafer manufacturing process or a heat treatment process of a device manufacturing process is performed. We intensively studied how to manufacture wafers.
In particular, the inventors have considered the crystallization mechanism of a polycrystalline silicon layer or an amorphous silicon layer.
When a polycrystalline silicon layer (or amorphous silicon layer) is grown on a base wafer having a mirror polished surface at a general product level and heat treatment is applied, single crystallization of the polycrystalline silicon occurs as follows.
When heat treatment is performed, a hole is opened in a part of the natural oxide film at the interface between the polycrystalline silicon layer and the base wafer at around 1000 ° C., so that the polycrystalline silicon contacts the surface of the base wafer, and twins grow from that part. . Some crystal defects remain on the plane of the twin crystal, but the other part grows into a single crystal. At high temperatures, holes open in many places and the same thing happens. As the heat treatment proceeds, further single crystallization occurs. The reason why single crystallization is likely to occur is that the underlying base wafer has a single orientation even when such many twins grow.

On the other hand, if the surface has many locally different orientations exposed, a hole is opened in the natural oxide film at the interface due to heat treatment, and even if single crystallization occurs, various orientations coexist. Many crystal defects remain.
Specifically, a wafer that does not have a single orientation when the surface is viewed locally (that is, the surface roughness is large) is used as a base wafer, and a polycrystalline silicon layer or an amorphous silicon layer is formed on the surface. If grown, single crystallization can be suppressed by the subsequent heat treatment, so that the effect as a carrier trap layer is sustained.

  Based on the above knowledge, heat treatment process and device of SOI wafer manufacturing process by using surface roughness of the surface on which the polycrystalline silicon layer or amorphous silicon layer is formed as 2 nm or more as the base wafer. Since the polycrystalline silicon layer or the amorphous silicon layer can be deposited so that the single crystallization does not proceed even through the heat treatment process of the manufacturing process, the polycrystalline silicon layer or the amorphous silicon layer is converted into a single crystal by the heat treatment. It has been found that the effect as a carrier trap layer can be prevented from being reduced, and the present invention has been made.

Hereinafter, an SOI wafer manufacturing method of the present invention will be described with reference to FIG.
First, as shown in FIG. 1A, a bond wafer 10 and a base wafer 11 each made of a silicon single crystal are prepared. At this time, the base wafer 11 has a resistivity of 100 Ω · cm or more and a surface roughness (RMS) of a surface on which a polycrystalline silicon layer or an amorphous silicon layer is formed is 2 nm or more. If the surface roughness (RMS) is 2 nm or more, single crystallization by heat treatment such as an SOI wafer manufacturing process can be sufficiently suppressed, and thereby the effect as a carrier trap layer can be maintained. Moreover, if the resistivity of the base wafer 11 is 100 Ω · cm or more, it can be suitably used for manufacturing a high-frequency device, and the upper limit is not particularly limited, but is preferably 1000 Ω · cm or more, preferably 3000 Ω · cm. The above is particularly preferable.

  Further, the upper limit of the surface roughness (RMS) of the surface on which the polycrystalline silicon layer or the amorphous silicon layer of the base wafer 11 is formed is not particularly limited, but the deposited polycrystalline silicon is increased as the surface roughness is increased. Since the surface roughness of the layer also increases, a load is applied to the polishing step for satisfactorily bonding to the bond wafer (that is, the polishing time is increased). Therefore, the surface roughness of the base wafer is preferably 10 nm or less.

In addition, since the surface roughness of the peeling surface of the peeling wafer derived when producing the bonded SOI wafer by the ion implantation peeling method described later is 2 nm or more and 10 nm or less, this peeling wafer can be used as the base wafer 11. it can. This is efficient because the peeled wafer can be used as it is without performing a flattening process such as polishing on the peeled surface for regeneration.
However, since a portion that has not been peeled off by the ion implantation layer remains as a step in the peripheral portion (1 to 2 mm) of the peeled wafer, it is preferable to perform processing (polishing or etching) for removing only that portion.

  In addition, as a wafer having a surface roughness (RMS) of 2 nm or more on the surface of the base wafer on which the polycrystalline silicon layer or the amorphous silicon layer is formed, a wafer having an etched surface subjected to wet etching or dry etching is used. You can also. As such a wafer, it is preferable to use a CW wafer (chemical etching wafer) obtained before mirror polishing when producing a mirror polished wafer, but wet etching or dry etching is applied again to the wafer after mirror polishing. It can also be made.

Next, as shown in FIG. 1B, a polycrystalline silicon layer 12 is formed on the surface having a surface roughness (RMS) of the base wafer 11 of 2 nm or more. Note that an amorphous silicon layer can be used instead of the polycrystalline silicon layer. The amorphous silicon layer can be easily formed by lowering the temperature for depositing the polycrystalline silicon layer (for example, about 400 ° C.).
Similar to the polycrystalline silicon layer, the amorphous silicon layer is also monocrystallized by the thermal history during the SOI wafer manufacturing process or the device manufacturing process, and the effect as a carrier trap layer is reduced. If the surface roughness (RMS) of the surface for forming the film is 2 nm or more, single crystallization can be suppressed and the effect as the carrier trap layer can be maintained.

  Next, as shown in FIG. 1C, an insulating film (for example, an oxide film) 13 to be a buried oxide film layer 16 is grown on the bond wafer 10 by, for example, thermal oxidation or CVD. Alternatively, the oxide film 13 formed at this time may be formed on the polycrystalline silicon layer 12 of the base wafer 11 or may be formed on both wafers.

  Next, as shown in FIG. 1D, a bond wafer in which an oxide film 13 is formed so that the surface on which the polycrystalline silicon layer 12 is in contact with the base wafer 11 on which the polycrystalline silicon layer 12 is formed. Adhere to 10 and stick together. At this time, it is preferable that the surface of the polycrystalline silicon layer 12 is slightly polished to increase the flatness and then bonded.

  Then, as shown in FIG. 1E, the bonded bond wafer 10 is thinned, and a polysilicon layer 12, a buried oxide film layer 16, and an SOI layer 15 are formed on the base wafer 11. A laminated wafer 14 is produced.

  Thus, if the surface roughness (RMS) of the surface on which the polycrystalline silicon layer 12 or the amorphous silicon layer 12 of the base wafer 11 is formed is 2 nm or more, single crystallization is performed by heat treatment such as an SOI wafer manufacturing process. A bonded wafer 14 that can be sufficiently suppressed and thereby can maintain the effect as a carrier trap layer can be manufactured.

  Next, a method for manufacturing an SOI wafer according to the present invention when the ion implantation separation method is used will be described with reference to FIG.

The processes in FIGS. 2A and 2B are the same as the processes in FIGS. 1A and 1B. After the step of FIG. 2B, as shown in FIG. 2C, an insulating film (for example, an oxide film) 13 to be a buried oxide film layer 16 is grown on the bond wafer 10 by, for example, thermal oxidation or CVD. Let Alternatively, the oxide film 13 formed at this time may be formed on the polycrystalline silicon layer 12 of the base wafer 11 or may be formed on both wafers.
Thereafter, at least one kind of gas ions of hydrogen ions and rare gas ions is implanted from above the oxide film 13 by an ion implanter to form an ion implantation layer 17 in the bond wafer 10. At this time, the ion implantation acceleration voltage is selected so that the target thickness of the SOI layer 15 can be obtained.

  Next, as shown in FIG. 2D, the base wafer 11 on which the polycrystalline silicon layer 12 is formed is divided into the surface of the base wafer 11 on which the polycrystalline silicon layer 12 is formed and the implantation surface of the bond wafer 10. In contact with the bond wafer 10 on which the oxide film 13 is formed, the wafers are bonded together. At this time, it is preferable that the surface of the polycrystalline silicon layer 12 is slightly polished to increase the flatness and then bonded.

  Then, as shown in FIG. 2E, a heat treatment for generating a microbubble layer on the ion implantation layer 17 is applied to the wafer, peeled off at the microbubble layer, and embedded in the oxide film layer on the base wafer 11. A bonded wafer 14 on which 16 and the SOI layer 15 are formed is manufactured. At this time, the release wafer 18 having the release surface 19 is derived.

  Thus, even when the ion implantation delamination method is used, single crystallization due to heat treatment such as an SOI wafer manufacturing process can be sufficiently suppressed as in the manufacturing method shown in FIG. The bonded wafer 14 which can maintain the effect as a layer can be manufactured.

  The SOI bonded wafer manufactured by the manufacturing method described above has a configuration in which a polycrystalline layer or an amorphous layer, an insulating film, and an SOI layer are sequentially formed on a base wafer made of silicon single crystal. The base wafer has a resistivity of 100 Ω · cm or more, and the surface roughness (RMS) of the interface between the base wafer and the polycrystalline layer or the amorphous layer is 2 nm or more. The ratio of the <111> component in the sum of the orientation components of <220>, <311>, and <111> in the amorphous layer is 40% or less.

  With such an SOI bonded wafer, it is possible to suppress the polycrystalline silicon layer or the amorphous silicon layer from being single-crystallized by the heat treatment and reducing the effect as the carrier trap layer, and a higher frequency. It is possible to make an SOI wafer compatible with RF devices.

  EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these.

(Example 1-4)
As a base wafer, a plurality of exfoliated wafers (silicon single crystal wafer, diameter 300 mm, crystal orientation <100>, resistivity 1000 Ω · cm) prepared when a bonded SOI wafer is manufactured by an ion implantation exfoliation method are prepared and exfoliated. Base wafers having various surface roughness surfaces were prepared by changing the polishing amount of the surface.
In addition, the surface roughness of the base wafer of each Example shall be described in Table 1.

Polycrystalline silicon was grown to 4.5 μm on these base wafers by a low pressure CVD method at 650 ° C. Thereafter, the surface of the polycrystalline silicon layer was flattened by polishing with a polishing allowance of 0.5 μm. This wafer was used as a base wafer.
On the other hand, a bond wafer (silicon single crystal wafer, diameter 300 mm, crystal orientation <100>, resistivity 10 Ω · cm) is prepared, and a 200 nm silicon oxide film that becomes a BOX layer (buried oxide film layer) is thermally oxidized on the surface. Then, hydrogen ions (H + ions) were ion-implanted through the oxide film at an acceleration energy of 50 keV and a dose of 5 × 10 ¹⁶ / cm ² .

Thereafter, the oxide film surface on the ion-implanted side of the bond wafer is bonded to the surface of the polycrystalline silicon layer of the base wafer, a peeling heat treatment is performed at 500 ° C. for 30 minutes, and the bonded SOI wafer is peeled off by peeling at the ion-implanted layer. Produced.
Thereafter, sacrificial oxidation treatment (900 ° C. oxide film thickness 200 nm), CMP (polishing allowance 80 nm), sacrificial oxidation treatment (950 ° C. oxide film thickness 100 nm) are sequentially performed, and a bonded SOI wafer having an SOI layer having a thickness of 80 nm is obtained. did.

(Comparative Example 1-5)
A bonded SOI wafer was produced in the same manner as in Example 1-4. However, the surface roughness of the base wafer of each comparative example was described in Table 2.

For each of the SOI wafers of Example 1-4 and Comparative Example 1-5, the SOI layer and the BOX layer were removed, and the resistivity and crystal orientation of the carrier trap layer (polycrystalline silicon layer) were measured. Note that the resistivity and orientation were measured immediately after deposition of the polycrystalline silicon layer (before bonding), and this was used as a reference.
The resistivity was measured by a spreading resistance measurement method (SR method: Spreading Resistance method).

Further, the orientation of the polycrystalline silicon layer is measured using an X-ray diffractometer, and the <111> component occupies the sum of the peak values of the signals of the respective orientation components <220>, <311>, and <111>. The ratio of the peak value of the signal was calculated and used as an index of the progress of single crystallization.
That is, as shown in FIG. 3, an increase in the ratio (content ratio) of the <111> component of the polycrystalline silicon layer means that the single crystallization of the polycrystalline silicon layer proceeds. Further, as the monocrystallization progresses, the resistivity of the polycrystalline silicon layer also decreases.

FIG. 4 shows the relationship between the local surface roughness (1 μm square RMS) of the base wafer and the content of the <111> component of the polycrystalline silicon layer (immediately after deposition and the state of the final SOI wafer).
As can be seen from FIG. 4, the ratio (content ratio) of the <111> component of the polycrystalline silicon layer immediately after the deposition of the polycrystalline silicon layer was a small value of about 10 to 30%. In the state of the final SOI wafer that has undergone the heat treatment step in the process, the content of the <111> component increases as the surface roughness of the base wafer decreases, and the surface roughness is 1 nm or less (Comparative Example 1-5) Then it exceeded 40%.

  On the other hand, in the condition (Example 1-4) where the surface roughness is 2 nm or more, even in the state of the final SOI wafer that has undergone the heat treatment step in the SOI wafer manufacturing step, the content of the <111> component of the polycrystalline silicon layer is It is 40% or less, indicating that the progress of crystallization of the polycrystalline silicon layer can be suppressed.

FIG. 5 shows the relationship between the local surface roughness of the base wafer (1 μm square RMS) and the resistivity of the polycrystalline silicon layer (immediately after deposition and the state of the final SOI wafer).
As can be seen from FIG. 5, the resistivity of the polycrystalline silicon layer was all about 5000 Ω · cm immediately after the deposition of the polycrystalline silicon layer, but the surface of the final SOI wafer after the heat treatment process in the SOI wafer manufacturing process Under the condition where the roughness was 1 nm or less (Comparative Example 1-5), as a result of the progress of single crystallization, the roughness was reduced to 3000 to 1000 Ω · cm.

On the other hand, under the condition where the surface roughness is 2 nm or more (Example 1-4), the resistivity of the polycrystalline silicon layer is about 5000 Ω · cm even in the state of the final SOI wafer that has undergone the heat treatment process during the SOI wafer manufacturing process. It can be seen that the progress of crystallization of the polycrystalline silicon layer can be suppressed without changing.
4 and 5, if the local surface roughness (RMS) of the base wafer is set to 2 nm or more, the single crystallization of the polycrystalline silicon layer due to the heat treatment such as the SOI wafer manufacturing process can be sufficiently suppressed. I understand. If the single crystallization of the polycrystalline silicon layer is suppressed, the effect of the polycrystalline silicon layer as a carrier trap layer can be maintained.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

10 ... Bond wafer, 11 ... Base wafer,
12 ... polycrystalline silicon layer (amorphous silicon layer), 13 ... insulating film (oxide film),
14 ... bonded wafer, 15 ... SOI layer,
16 ... buried oxide film layer (BOX layer), 17 ... ion implantation layer,
18 ... peeling wafer, 19 ... peeling surface.

Claims (7)

Both are methods for producing a bonded SOI wafer by laminating a bond wafer made of a silicon single crystal and a base wafer via an insulating film,
at least,
Forming a polycrystalline silicon layer or an amorphous silicon layer on the bonding surface side of the base wafer;
Forming the insulating film on at least one of the surface of the polycrystalline silicon layer or the amorphous silicon layer and the bonding surface of the bond wafer;
Bonding the base wafer and the bond wafer through the insulating film;
Forming a SOI layer by thinning the bonded bond wafer,
The base wafer has a resistivity of 100 Ω · cm or more and a surface roughness (RMS) of the surface on which the polycrystalline silicon layer or the amorphous silicon layer is formed is 2 nm or more. Manufacturing method of SOI wafer.   2. The method for manufacturing an SOI wafer according to claim 1, wherein a surface roughness of a surface on which the polycrystalline silicon layer or the amorphous silicon layer is formed is 10 nm or less as the base wafer.   As the base wafer, a separation wafer derived when a bonded SOI wafer is produced by an ion implantation separation method is used, and the polycrystalline silicon layer or the amorphous silicon layer is formed on the separation surface of the separation wafer. A method for manufacturing an SOI wafer according to claim 1 or 2.   3. The surface of the base wafer on which the polycrystalline silicon layer or the amorphous silicon layer is formed is an etched surface on which wet etching or dry etching is performed. Manufacturing method of SOI wafer.   5. The method for manufacturing an SOI wafer according to claim 1, wherein the step of forming the SOI layer by thinning the bond wafer is performed by an ion implantation separation method. A bonded SOI wafer in which a polycrystalline layer or an amorphous layer, an insulating film, and an SOI layer are sequentially formed on a base wafer made of silicon single crystal,
The base wafer has a resistivity of 100 Ω · cm or more,
The surface roughness (RMS) of the interface between the base wafer and the polycrystalline layer or the amorphous layer is 2 nm or more,
A bonded SOI wafer, wherein a ratio of a <111> component in a sum of orientation components of <220>, <311>, and <111> of the polycrystalline layer or the amorphous layer is 40% or less .   The bonded SOI wafer according to claim 6, wherein a surface roughness of an interface between the base wafer and the polycrystalline layer or the amorphous layer is 10 nm or less.

Images