JP6111678B2 - Manufacturing method of GeOI wafer - Google Patents

Description

  The present invention relates to a method for manufacturing a GeOI wafer.

  A germanium (Ge) single crystal has higher electron / hole mobility than a silicon (Si) single crystal, and GeOI (Germanium On Insulator) is considered to be useful as a next-generation CMOS substrate. Conventionally, a number of methods have been proposed as a method for producing GeOI.

  The first known method uses an ion implantation delamination method and uses layer transfer from a donor wafer made of germanium single crystal (Patent Document 1). The oxidized surface of the handle wafer (support substrate) made of silicon single crystal is bonded to the donor wafer. The donor wafer and handle wafer are then separated (peeled) along the heel interface so that a thin layer of Ge remains on the silicon oxide. However, it is necessary to process the surface roughness of the transferred Ge layer by CMP (chemical mechanical polishing), and it is difficult to form a Ge layer with good film thickness uniformity.

The second known method is to epitaxially grow a SiGe graded layer on a silicon donor wafer and to epitaxially grow a Ge layer on the SiGe graded layer (Patent Document 2). Next, the Ge layer or the SiGe / Ge layer is transferred onto the handle wafer by ion implantation separation. However, the threading dislocation density of the Ge layer grown on the SiGe graded layer is about 10 ⁶ to 10 ⁸ cm ^−2, which is a factor that degrades the performance of the device. Further, since the Ge layer is exposed from the transferred SiGe / Ge layer, it is difficult to selectively etch only the SiGe graded transfer layer having a high Ge content.

  A third known method is a method of starting a GeGeOI substrate and producing a GeOI wafer by an oxidation concentration method of a Ge layer (Patent Document 3). However, in this method, since it is necessary to raise the temperature at the time of oxidative concentration, high density defects are formed.

JP-A-5-211128 JP 2008-141206 A JP-A-2005-142217

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for producing a GeOI wafer having a Ge layer having a uniform in-plane film thickness and having less surface roughness and crystal defects.

The present invention has been made to solve the above problems,
A Ge layer is epitaxially grown on the SOI layer surface of an SOI wafer in which a buried oxide film layer (BOX layer) and an SOI layer are sequentially formed on a silicon single crystal wafer,
Forming an ion implantation layer in the silicon single crystal wafer by implanting at least one of hydrogen ions or rare gas ions through the Ge layer;
The surface of the Ge layer and the surface of the handle wafer are adhered and bonded together via an insulating film, and then peeled off by the ion implantation layer, whereby the insulating film, the Ge layer, A bonded wafer having a structure in which an SOI layer, the buried oxide film layer, and a part of the silicon single crystal wafer are sequentially laminated is manufactured.
Thereafter, the insulating layer and the Ge layer are sequentially formed on the handle wafer by sequentially removing a part of the silicon single crystal wafer, the buried oxide layer, and the SOI layer to expose the Ge layer. Provided is a method for manufacturing a GeOI wafer, characterized by producing a stacked GeOI wafer.

  In the present invention, an ion implantation layer is formed inside a silicon single crystal wafer (base wafer) of an SOI wafer through a Ge layer, and the Ge layer has no cleavage plane (peeling surface). It is not necessary to process the surface roughness by CMP (Chemical Mechanical Polishing), and a GeOI wafer having a Ge layer with good film thickness uniformity can be manufactured. Also, if an ultra-thin SOI wafer (SOI film thickness ≦ 20 nm) with a thin film thickness and a good film thickness distribution is used, the removal of the final Si layer can be reduced, and the Si layer can be removed. It is possible to suppress the deterioration of the surface roughness of the Ge layer and the deterioration of the film thickness uniformity.

  At this time, part of the silicon single crystal wafer is removed by alkali etching or CMP (chemical mechanical polishing), the buried oxide film layer is removed by an HF-containing solution, and the SOI layer is removed by an etching solution. It is preferable to carry out either etching liquid, CMP or sacrificial oxidation treatment.

  In this way, the multilayer film (Si / BOX / SOI layer) on the Ge layer can be satisfactorily peeled, and a GeOI wafer can be produced effectively leaving only the Ge layer.

  Further, at this time, the thickness of the SOI layer is preferably 10 nm or less.

  By using such an ultra-thin SOI layer, the time required for polishing to remove the SOI layer is extremely short, so that the machining allowance in polishing is small and a GeOI having a uniform Ge layer thickness A wafer can be reliably manufactured. Also, by using such an ultra-thin SOI layer, the time required for etching can be made extremely short, so that a GeOI wafer with less surface roughness of the Ge layer can be reliably manufactured. These effects can be increased as the SOI layer is made thinner.

  Further, in this case, the handle wafer is a silicon single crystal wafer, a silicon oxide film as the insulating film is formed on the surface of the silicon single crystal wafer, and the surface of the silicon oxide film and the surface of the Ge layer are bonded together. It is preferable.

  In this way, a GeOI wafer having a uniform Ge layer can be effectively manufactured.

  As described above, according to the present invention, a GeOI wafer having a Ge layer with a uniform in-plane film thickness and less surface roughness and crystal defects can be produced. As a result, it is possible to speed up the device and reduce power consumption.

It is a flowchart which shows an example of the manufacturing method of the GeOI wafer of this invention.

As a result of intensive studies to achieve the above object, the present inventors
A Ge layer is epitaxially grown on the SOI layer surface of an SOI wafer in which a buried oxide film layer (BOX layer) and an SOI layer are sequentially formed on a silicon single crystal wafer,
Forming an ion implantation layer in the silicon single crystal wafer by implanting at least one of hydrogen ions or rare gas ions through the Ge layer;
The surface of the Ge layer and the surface of the handle wafer are adhered and bonded together via an insulating film, and then peeled off by the ion implantation layer, whereby the insulating film, the Ge layer, A bonded wafer having a structure in which an SOI layer, the buried oxide film layer, and a part of the silicon single crystal wafer are sequentially laminated is manufactured.
Thereafter, the insulating layer and the Ge layer are sequentially formed on the handle wafer by sequentially removing a part of the silicon single crystal wafer, the buried oxide layer, and the SOI layer to expose the Ge layer. A method for producing a GeOI wafer characterized by producing a stacked GeOI wafer can produce a GeOI wafer having a Ge layer having a uniform in-plane film thickness and a small surface roughness and crystal defects. The headline and the present invention were completed.

Hereinafter, the method for producing a GeOI wafer of the present invention will be described in detail with reference to FIG. 1, but the present invention is not limited thereto.
First, an SOI wafer (SOI layer 3 / BOX layer 2 / base wafer 1) is used as a donor wafer on which a Ge layer is formed, and a Ge layer 4 is epitaxially grown on the surface of the SOI layer 3 (FIG. 1A).
At this time, if an ultra-thin SOI wafer having a thin film thickness and a good film thickness distribution (SOI film thickness ≦ 20 nm, particularly 10 nm or less) is used, the allowance for removal of the Si layer at the final stage can be reduced. This is advantageous because it can be reduced and the deterioration of the surface roughness and film thickness uniformity of the Ge layer accompanying the removal of the Si layer can be suppressed. Here, a case where an ultra-thin SOI wafer is used will be described as an example.

Note that when the thickness of the Ge layer epitaxially grown on the surface of the SOI layer is increased, misfit dislocations due to the difference in lattice constant between Si and Ge become prominent, so the thickness of the Ge layer is set to 20 nm or less. The thickness is preferably 10 nm or less.
A silicon single crystal wafer is used as the semiconductor single crystal substrate used as the base wafer of the SOI wafer.

Next, ions are implanted through the Ge layer 4 to form an ion implanted layer 5 inside the base wafer 1 (FIG. 1B). At this time, the ion implantation depth is set to a depth at which the base wafer 1 of the SOI wafer is peeled off.
Such an ion implantation layer is formed by ion implantation of at least one kind of gas ions of hydrogen ions or rare gas ions. Here, a case where hydrogen ions are implanted (hydrogen ion implanted layer 5) will be described as an example.

  As described above, in the present invention, since the ion implantation layer is not formed in the Ge layer 4, the cleavage plane (peeling surface) is not formed in the Ge layer 4. For this reason, it is not necessary to process the surface roughness of the Ge layer 4 due to peeling by chemical mechanical polishing (CMP), and a GeOI wafer having a Ge layer with a uniform film thickness can be manufactured.

Next, the handle wafer 6 is separately thermally oxidized to form an insulating film (silicon oxide film) 7 on the surface of the handle wafer 6 (FIG. 1C).
A silicon single crystal wafer is preferably used as the semiconductor single crystal substrate used as the handle wafer. Here, a case where a silicon single crystal wafer is used will be described.

  Next, for example, at a room temperature of 20 to 30 ° C., the Ge layer 4 and the surface of the handle wafer 6 are bonded together via an insulating film (silicon oxide film) 7 to produce a bonded wafer (FIG. 1D). . In this case, the bonding strength can be improved by performing surface activation processing such as plasma processing on at least one bonding surface of the Ge layer 4 and the handle wafer 6 before bonding.

  Next, the bonded wafer is annealed at a low temperature (FIG. 1E), is subjected to a peeling process, and is peeled off by the hydrogen ion implantation layer 5 to thereby form an insulating film (silicon oxide film) 7 on the handle wafer 6. The Si / BOX / SOI / Ge layer is transferred to the substrate (FIG. 1F).

Next, the outermost Si after peeling (a part of the base wafer 1 of the SOI wafer) is removed (FIG. 1G). At this time, if etching such as alkali etching or CMP is used, etching or CMP can be stopped at the SiO ₂ layer (BOX layer 2 of the SOI wafer) by utilizing a decrease in etching rate or polishing rate. It is preferable because only the Si layer can be removed.

Next, the SiO ₂ layer (BOX layer 2 of the SOI wafer) is removed (FIG. 1H). The removal method is not particularly limited. However, when etching is performed, it is preferable to use an HF-containing solution that easily etches the SiO ₂ layer and hardly etches the Si layer (the SOI layer 3 of the SOI wafer) as the etching solution. Although the HF-containing solution is used as the etching solution here, the etching may be performed with HF-containing water vapor.

Finally, the Si layer (SOI layer 3 of the SOI wafer) is removed (FIG. 1I). Examples of the removal method include an etching solution, a selective etching solution, CMP, or sacrificial oxidation treatment. An etching solution for etching the Si layer such as an SC1 solution (mixed aqueous solution of NH ₄ OH and H ₂ O ₂ ), or an Si layer is used. The Ge layer may be easily etched and the Ge layer may be thinned with a selective etchant that is difficult to etch, or the Si layer may be removed by CMP or thermally oxidized to change the entire Si layer to a SiO ₂ layer, The Ge layer 4 can be left by etching away the SiO ₂ layer.

  At this time, in the present invention, since the SOI layer is thinned to, for example, 20 nm or less, particularly 10 nm or less, the machining allowance that needs to be removed by etching or polishing can be reduced to 20 nm or less. Therefore, the SOI layer can be removed with almost no polishing and etching of the exposed Ge layer surface. Therefore, the surface of the exposed Ge layer does not deteriorate the roughness and is not a release surface, so there is no defect. Furthermore, the film thickness uniformity is maintained well because it is not removed by polishing with a lot of removal.

  EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these.

Example 1
As a donor wafer, prepare a substrate obtained by epitaxially growing a Ge layer on a SOI / BOX layer = 10 nm / 145 nm SOI wafer and implanting hydrogen ions so that the implantation depth is in the bulk of the base wafer of the SOI wafer. The energy was 50 keV and the dose was 5 × 10 ¹⁶ cm ⁻² (5e16 cm ⁻² ). On the other hand, as a handle wafer, a substrate in which a 150 nm oxide film (silicon oxide film) is formed on a Si single crystal wafer is prepared, and plasma processing is performed on the donor wafer and the handle wafer before bonding, and then bonding is performed. went.

  The bonded wafer was peeled off at 500 ° C. for 30 minutes in an Ar atmosphere to transfer the Si / BOX / SOI / Ge layer onto the silicon oxide film on the handle wafer.

Thereafter, the uppermost Si layer (a part of the base wafer of the SOI wafer) was removed using CMP to leave a BOX / SOI / Ge layer. Thereafter, the SiO ₂ layer (BOX layer of the SOI wafer) was removed with an HF-containing aqueous solution, and the SOI / Ge layer was left. Thereafter, as a method for removing the Si layer (SOI layer of the SOI wafer), the Si layer was removed by using CMP (removal allowance = 14 nm) to produce a GeOI wafer having a Ge layer thickness of 6 nm.

(Example 2)
After the SOI / Ge layer was left in the same manner as in Example 1, the Si layer (the SOI layer of the SOI wafer) was removed by etching with an SC1 solution (mixed aqueous solution of NH ₄ OH and H ₂ O ₂ ) (etching rate = 12 nm), a GeOI wafer having a Ge layer thickness of 8 nm was produced.

(Example 3)
After the SOI / Ge layer was left in the same manner as in Example 1, the SOI layer was oxidized by an 800 ° C. oxidation heat treatment not higher than the melting point of Ge (934.7 ° C.), and then the oxidized SOI layer was converted into an HF-containing aqueous solution. The GeOI wafer having a Ge layer thickness of 8 nm was prepared by etching.

(Comparative Example 1)
After forming a graded SiGe (graded SiGe (G-SiGe)) layer on a Si single crystal wafer, a substrate obtained by epitaxially growing the Ge layer is used as a donor wafer, and the Ge layer is peeled off by a Ge layer by an ion implantation peeling method, and then a Ge layer is obtained by CMP. Was thinned to form a GeOI wafer.

  Table 1 shows the results of measuring the film thickness uniformity, surface roughness, and defect density of the Ge layer (GeOI layer) after fabrication of the GeOI wafer in Examples 1 to 3 and Comparative Example 1.

  In Table 1, the film thickness of the GeOI layer was measured at 41 points in the plane using an ellipsometer, and the difference between the maximum film thickness and the minimum film thickness was evaluated as the film thickness range (Range). The thickness was evaluated by RMS (Root Mean Square) of 1 μm square using an AFM (atomic force microscope).

  The defect density of the GeOI layer was evaluated by immersing each GeOI wafer in an HF aqueous solution, observing pinholes formed in the underlying oxide film through the defects of the GeOI layer with an optical microscope, and measuring the density.

  As shown in Table 1, in Examples 1 to 3, compared with Comparative Example 1, the in-plane film thickness uniformity and defect density of the GeOI layer are remarkably good, the surface roughness is also good, and all are excellent in a good balance. I was able to get a good result.

  In the present invention, the above-described embodiment is an exemplification, and what has substantially the same configuration as the technical idea described in the claims of the present invention and exhibits the same function and effect is any Even within the technical scope of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Base wafer, 2 ... BOX layer, 3 ... SOI layer, 4 ... Ge layer,
5 ... Hydrogen ion implantation layer, 6 ... Handle wafer, 7 ... Insulating film (silicon oxide film).

Claims (2)

A Ge layer is epitaxially grown on the SOI layer surface of an SOI wafer in which a buried oxide film layer (BOX layer) and an SOI layer having a thickness of 10 nm or less are sequentially formed on a silicon single crystal wafer,
Forming an ion implantation layer in the silicon single crystal wafer by implanting at least one of hydrogen ions or rare gas ions through the Ge layer;
The surface of the Ge layer and the surface of the handle wafer are adhered and bonded together via an insulating film, and then peeled off by the ion implantation layer, whereby the insulating film, the Ge layer, A bonded wafer having a structure in which an SOI layer, the buried oxide film layer, and a part of the silicon single crystal wafer are sequentially laminated is manufactured.
Thereafter, the insulating layer and the Ge layer are sequentially formed on the handle wafer by sequentially removing a part of the silicon single crystal wafer, the buried oxide layer, and the SOI layer to expose the Ge layer. Make a stacked GeOI wafer ,
A part of the silicon single crystal wafer is removed by alkali etching or CMP (chemical mechanical polishing), the buried oxide layer is removed by a HF-containing solution, and the SOI layer is removed by an etching solution, a selective etching solution, A method for producing a GeOI wafer, which is performed by either CMP or sacrificial oxidation treatment . The handle wafer is a silicon single crystal wafer, a silicon oxide film as the insulating film is formed on the surface of the silicon single crystal wafer, and the surface of the silicon oxide film and the surface of the Ge layer are bonded to each other. The method for producing a GeOI wafer according to claim 1 .

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