EP2061084A1 - Rückwärtsleitender bipolarer Transistor mit isoliertem Gate und entsprechendes Herstellungsverfahren - Google Patents

Rückwärtsleitender bipolarer Transistor mit isoliertem Gate und entsprechendes Herstellungsverfahren Download PDF

Info

Publication number
EP2061084A1
EP2061084A1 EP07120665A EP07120665A EP2061084A1 EP 2061084 A1 EP2061084 A1 EP 2061084A1 EP 07120665 A EP07120665 A EP 07120665A EP 07120665 A EP07120665 A EP 07120665A EP 2061084 A1 EP2061084 A1 EP 2061084A1
Authority
EP
European Patent Office
Prior art keywords
layer
created
electrical contact
mask
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07120665A
Other languages
English (en)
French (fr)
Inventor
Munaf Rahimo
Jan Vobecky
Arnost Kopta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ABB Technology AG
Original Assignee
ABB Technology AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ABB Technology AG filed Critical ABB Technology AG
Priority to EP07120665A priority Critical patent/EP2061084A1/de
Priority to CN200880116904.3A priority patent/CN101861651B/zh
Priority to EP08849161.8A priority patent/EP2215659B1/de
Priority to JP2010533539A priority patent/JP5693962B2/ja
Priority to PCT/EP2008/065030 priority patent/WO2009062876A1/en
Publication of EP2061084A1 publication Critical patent/EP2061084A1/de
Priority to US12/778,751 priority patent/US8450777B2/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors

Definitions

  • the invention relates to the field of power electronics and more particularly to a method for manufacturing a reverse-conducting insulated gate bipolar transistor according to the preamble of claim 1 and to a reverse-conducting insulated gate bipolar transistor according to the preamble of claim 13.
  • a reverse-conducting insulated gate bipolar transistor (RC-IGBT) is described, which comprises within one wafer an insulated gate bipolar transistor with a built-in freewheeling diode.
  • a reverse-conducting insulated gate bipolar transistor 1 comprises a first layer 2 formed as an n type base layer with a first main side 21 and a second main side 22 opposite the first main side 21.
  • a second p type layer 3 is arranged on the first main side 21.
  • On the second layer 3 a third n type layer 4 with a higher doping than the first layer 2 is arranged on the first main side 21.
  • the third layer 4 is surrounded by the second layer 3 in such a way that in the central part of the second layer 3 no third layer 4 is arranged above the second layer 3.
  • a fifth electrically insulating layer 6 is arranged on the first main side 21 and covers the second layer 3 and the first layer 2 and partially covers the third layer 4.
  • An electrically conductive fourth layer 5 is completely embedded in the fifth layer 6. Above the central part of the second layer 3 no fourth or fifth layer 5, 6 is arranged.
  • a first electrical contact 10 is arranged on the first main side 21 and covers the fifth layer 6.
  • the first electrical contact 10 is in direct electrical contact to the second layer 3 and the third layer 4, but is electrically insulated from the fourth layer 5.
  • p type sixth layers 7 and n type seventh layers 8 are arranged alternately in a plane.
  • the seventh layers 8 have a higher doping than the first layer 2.
  • the seventh layers 8 are arranged directly below the second layer 3 and the first electrical contact 10 if seen in orthographic projection.
  • a second electrical contact 11 is arranged on the second main side 22 and it covers the sixth and seventh layers 7, 8 and is in direct electrical contact to them.
  • a freewheeling diode is formed between the second electrical contact 11, part of which forms a cathode electrode in the diode, the seventh layer 8, which forms a cathode region in the diode, the first layer 2, part of which forms a base layer in the diode, the second layer 3, part of which forms an anode region in the diode and the first electrical contact 10, which forms an anode in the diode.
  • An insulated gate bipolar transistor is formed between the second electrical contact 11, part of which forms a collector electrode in the IGBT, the sixth layer 7, which forms a collector region in the IGBT, the first layer 2, part of which forms a base layer, the second layer 3, part of which forms a p-base region in the IGBT, the third layer 4, which forms a source region in the IGBT and the first electrical contact 10, which forms an emitter electrode.
  • a channel is formed between the emitter electrode, the source region and the p-base region towards the n-base layer.
  • US 2005/0258493 shows a similar reverse-conducting IGBT, in this case with a trench gate structure. Below the trench gate electrode and the p-base region a recombination layer, which extends completely through the first layer in a plane parallel to the first main side, i.e. it is formed through the diode section as well as through the IGBT section.
  • This recombination layer is formed by uniform Helium irradiation.
  • JP 2007-103770 also shows a reverse-conducting IGBT.
  • the lifetime controlling is improved by introducing local recombination layers, which are arranged in the first layer in the diode section close to the second main side, i.e. in the area, in which the second layer is in direct contact to the anode and the cathode layer on the second main side.
  • the recombination layer is formed by a complex masking technique, in which a metal mask is introduced on the second side of the wafer after the finishing of the device on the first side (emitter side in the finalized device) and after creating the collector and cathode layer and the second electrical contact.
  • the mask has openings in the diode section, i.e.
  • the mask has to be aligned to the first electrical contact on the first side of the wafer, i.e with the side which lies opposite to the side where the mask is positioned. Only by such a positioning it can be assured that the recombination fields will be arranged in the diode section of the reverse-conducting IGBT in the first base layer between the cathode layer and the anode layer. Then the wafer is irradiated with a light ion beam. Thickness of the mask and/or energy of the beam are chosen in such a way that the ions only penetrate into the wafer in the diode section, i.e. in the part in which the collector layers are arranged. Afterwards, the mask is removed and the device is completed.
  • This object is achieved by a method for manufacturing a reverse-conducting insulated gate bipolar transistor according to claim 1 and by a reverse-conducting insulated gate bipolar transistor according to claim 13.
  • the inventive method for manufacturing a reverse-conducting insulated gate bipolar transistor comprises the following steps:
  • the reverse-conducting insulated gate bipolar transistor according to the invention comprises at least one ninth layer formed as a recombination layer, which is arranged within the second layer and/or below the second layer in the first layer.
  • the inventive method is also advantageous, because the mask is applied on the same side, on which the recombination layer shall be arranged and to which side the recombination layer shall be aligned, thus avoiding the necessity to position a mask on the second side and to align it to the position of the first electrical contact and the second and third layer on the other side, i.e. on the first side. Furthermore, the inventive method does not need a special mask at all, because the mask can be made of layers, which are part of to the RC-IGBT.
  • the inventive RC-IGBT does not need an alignment of the sixth layer, which forms the cathode layer in the diode, and still the advantages of the invention of improving the diode properties without deteriorating the IGBT properties can be maintained. Due to the self-alignment to the first opening the at least one ninth recombination layer can not be shifted in such a way that it would be located in the IGBT section of the RC-IGBT.
  • a first embodiment of an inventive reverse-conducting insulated gate bipolar transistor 1 is shown.
  • the RC-IGBT 1 comprises an n type first layer 2 with a first main side 21 and a second main side 22 opposite the first main side 21.
  • a p type second layer 3 is arranged on the first main side 21.
  • At least one n type third layer 4 is arranged on the first main side 21 and is surrounded by the second layer 3.
  • the at least one third layer 4 has a higher doping than the first layer 2.
  • a fifth electrically insulating layer 6 is arranged on the first main side 21 on top of the first, second, and third layer 2, 3, 4. It at least partially covers the at least one third layer 4, the second layer 3 and the first layer 2.
  • An electrically conductive fourth layer 5 is arranged on the first main side 21 electrically insulated from the at least one third layer 4, the second layer 3 and the first layer 2 by the fifth layer 6.
  • the fourth layer 5 is embedded in the fifth layer 6.
  • the fifth layer 6 comprises a first electrically insulating layer 61, preferably made of a silicon dioxide, and a second electrically insulating layer 62, preferably also made of a silicon dioxide, preferably of the same material as the first electrically insulating layer 61.
  • the second electrically insulating layer 62 covers the first electrically insulating layer 61.
  • the first electrically insulating layer 61 is arranged on top of the first main side 21.
  • a fourth layer 5, which forms a gate electrode is embedded, typically it is completely embedded.
  • the fourth layer 5 is separated from the first, second and third layer 2, 3, 4 by the first electrically insulated layer 61.
  • the fourth layer 5 is typically made of a heavily doped polysilicon or a metal like aluminum.
  • the at least one third layer 4, the fourth layer 5 and the fifth layer 6 are formed in such a way that a first opening 16 is created above the second layer 3.
  • the first opening 16 is surrounded by the at least one third layer 4, the fourth layer 5 and the fifth layer 6.
  • a first electrical contact 10 is arranged on the first main side 21 within the first opening 16. This first electrical contact 10 typically also covers the fifth layer 6, but is separated and thus electrically insulated from the fourth layer 5 by the second electrically insulating layer 62. It is in direct electrical contact to the second layer 3 and the third layer 4.
  • At least one p type sixth layer 7 and at least one n type seventh layer 8 are arranged on the second main side 22, the at least one sixth and seventh layers 7, 8 being arranged alternately in a plane.
  • the seventh layer 8 has a higher doping than the first layer 2.
  • the seventh layer 8 is arranged directly below the first opening 16, but the position of the seventh layer 8 could also be shifted to a side as shown in Fig. 11 . It is not necessary to have the seventh layer 8 aligned to the first opening 16 and, thus, to the first electrical contact 10.
  • a second electrical contact 11 is arranged on the second main side 22 and it is in direct electrical contact to the at least one sixth and seventh layers 7, 8.
  • a ninth recombination layer 12 which comprises a first recombination region 121, is arranged in a self-aligned manner to the first opening 16 within the second layer 3 or, as shown in Fig. 4 , within the first layer 2 below the second layer 3.
  • the first recombination region 121 is arranged within the first layer 2 in a depth of at maximum 10 ⁇ m below the junction between the second layer 3 and the first layer 2.
  • the ninth layer 12 is represented by the area of maximum recombination centers concentration within the ninth layer 12.
  • the depth of the ninth layer has to be understood as the depth of the maximum recombination centers concentration.
  • the ninth recombination layer 12 is arranged in a self-aligned manner to the first opening 16 within the second layer 3 and within the first layer 2 below the second layer 3, i.e. the ninth layer 12 extends in this case from a region within the second layer 3 to a region within the first layer 2.
  • the inventive RC-IGBT can also comprise more than one ninth layer, e.g. two ninth layers.
  • One of these ninth layers 12 could be arranged within the second layer 3 and a further ninth layer 12' within the first layer 2.
  • the at least one ninth layer 12, 12' comprises a first recombination region 121, which is arranged below the first opening 16, and at least one second recombination region 122, which is arranged below the fourth and fifth layer 5, 6, i.e. below the first mask 14.
  • the first recombination region 121 is arranged in a greater depth than the second recombination region 122 and the second recombination region 122 is arranged at maximum in a depth corresponding to the thickness of the second layer 3, in particular at maximum in a depth of 1 ⁇ m.
  • a tenth n doped layer 17, formed as an enhancement layer, is arranged between the second layer 3 and the first layer 2 for having lower on-state losses.
  • the tenth layer 17 separates the second layer 3 from the first layer 2 and it has higher doping than the first layer 2.
  • the inventive RC-IGBT may comprise a fourth layer 5', formed as trench gate electrode as shown in Fig. 9 .
  • the trench gate electrode 5' is arranged in the same plane as the second layer 3 and adjacent to the second layer 3, separated from each other by a first insulating layer 61, which also separates the fourth layer 5' from the first layer 2.
  • a second insulating layer 62 is arranged on top of the fourth layer formed as a trench gate electrode 5', thus insulating the fourth layer 5' from the first electrical contact 10.
  • the RC-IGBT 1 further comprises an n type eighth layer 9, which is arranged between the first layer 2 and the plane, in which the at least one sixth and seventh layers 7, 8 are arranged and which eighth layer 9 has a higher doping than the first layer 2 and a lower doping than the seventh layer 8.
  • the conductivity types are switched, i.e. all layers of the first conductivity type are p type (e.g. the first layer 2) and all layers of the second conductivity type are n type (e.g. the second layer 3).
  • a diode is formed between the first electrical contact 10, which forms an anode electrode in the diode, the second layer 3, part of which forms an anode layer, the first layer 2, part of which forms a base layer, the seventh layer 8, which forms a cathode layer, and the second electrical contact 11, which forms a cathode electrode.
  • an insulating bipolar transistor is formed between the first electrical contact 10, which forms an emitter electrode in the IGBT, the third layer 4, which forms a source region, the second layer 3, part of which forms a channel region, the first layer 2, part of which forms a base region, the sixth layer 7, which forms a collector layer and the second electrical contact 11, part of which forms a collector electrode.
  • the inventive reverse-conducting insulated gate bipolar transistor can for example be used in a converter.
  • the ninth layer 12 comprises a first recombination region 121, aligned to the first opening 16 and below the first opening 16, and second recombination region 122 below the first mask 14. As the second recombination regions 122 are located close to the first main side 21 this device can achieve the advantage of improved diode characteristics without deteriorating the IGBT characteristics.
  • the ions are being prevented from penetrating into the wafer 13 in the area around the first opening 16 by the first mask 14 so that the ninth layer 12 is merely formed in the wafer below the first opening 16.
  • the ninth layer 12 only comprises the first recombination region 121 arranged below the first opening 16.
  • the ions for creating the ninth recombination layer 12 are implanted before the creation of the first electrical contact 10, as shown in Fig. 5 .
  • the ions for creating the ninth layer 12 are implanted after the creation of the first electrical contact 10, as shown in Fig. 6 .
  • the first mask 14 further comprises the first electrical contact 10.
  • a second mask 15 is created before the creation of the first electrical contact 10 on top of the fifth layer 6, which has a second opening above the second layer 3, the second opening preferably corresponding to the first opening 16.
  • the first mask 14 further comprises the second mask 15.
  • the second mask 15 is preferably a resist mask, which is removed before finalizing the RC-IGBT.
  • Fig. 8 shows a second mask 15', which is created after the creation of the first electrical contact 10 on top of the first electrical contact 10.
  • This second mask 15' also has a second opening above the second layer 3, the second opening preferably corresponding to the first opening 16, but the second opening could also be wider, smaller or shifted compared to the first opening 16.
  • the first mask 14 further comprises the second mask 15'.
  • the second mask 15' is preferably a resist mask, which is removed before finalizing the RC-IGBT.
  • the second mask 15' is a metal mask, which can either be removed before finalizing the semiconductor device or which is retained in the finalized device. Also such a metal second mask 15' may be introduced before or after the creation of the first electrical contact 10.
  • ions for implantation hydrogen or Helium ions may be used.
  • the ions for implantation are phosphorous or boron ions.
  • the phosphorous or boron ions may in particular be multiple charged ions, e.g. double charged boron (B ++ ) or triple charged phosphorous (P +++ ).
  • the dose of the ions for implantation is preferably higher than 1 * 10 11 /cm 2 .
  • an anneal step is performed, in particular at a temperature of not more than 500 °C and in particular at a temperature between 150 °C and 450 °C to ensure that no doping effects take place in the p type second layer 3 and local lifetime is conserved.
  • the ninth layer 12 may be created within the second layer 3 or within the first layer 2 below the second layer 3. In another preferred embodiment, the ninth layer 12 is arranged within the second and first layer 2, 3, i.e. within an area, which extends from the second layer 3 to the first layer 2.
  • the inventive RC-IGBT comprises two or more ninth recombination layers 12, 12' one of these ninth layers 12 could be created by implantation of hydrogen or Helium ions and a further ninth recombination layer 12' could be created by implantation of phosphorous or boron ions.
  • the implantation steps could be performed at different stages of the device manufacturing, e. g. one implantation step before creation of the first electrical contact 10 and a further step after creation of the contact 10 or one implantation before and the other after introduction of a second mask 15, 15' so that a lot of possibilities arise for optimizing the location and properties of the recombination layers 12, 12'.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
EP07120665A 2007-11-14 2007-11-14 Rückwärtsleitender bipolarer Transistor mit isoliertem Gate und entsprechendes Herstellungsverfahren Withdrawn EP2061084A1 (de)

Priority Applications (6)

Application Number Priority Date Filing Date Title
EP07120665A EP2061084A1 (de) 2007-11-14 2007-11-14 Rückwärtsleitender bipolarer Transistor mit isoliertem Gate und entsprechendes Herstellungsverfahren
CN200880116904.3A CN101861651B (zh) 2007-11-14 2008-11-06 反向导通绝缘栅双极晶体管和对应制造方法
EP08849161.8A EP2215659B1 (de) 2007-11-14 2008-11-06 Rückwärtsleitender bipolarer transistor mit isoliertem gate und herstellungsverfahren dafür
JP2010533539A JP5693962B2 (ja) 2007-11-14 2008-11-06 逆導電絶縁ゲート・バイポーラ・トランジスタを製造するための方法
PCT/EP2008/065030 WO2009062876A1 (en) 2007-11-14 2008-11-06 Reverse-conducting insulated gate bipolar transistor and corresponding manufacturing method
US12/778,751 US8450777B2 (en) 2007-11-14 2010-05-12 Method for manufacturing a reverse-conducting insulated gate bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP07120665A EP2061084A1 (de) 2007-11-14 2007-11-14 Rückwärtsleitender bipolarer Transistor mit isoliertem Gate und entsprechendes Herstellungsverfahren

Publications (1)

Publication Number Publication Date
EP2061084A1 true EP2061084A1 (de) 2009-05-20

Family

ID=39322089

Family Applications (2)

Application Number Title Priority Date Filing Date
EP07120665A Withdrawn EP2061084A1 (de) 2007-11-14 2007-11-14 Rückwärtsleitender bipolarer Transistor mit isoliertem Gate und entsprechendes Herstellungsverfahren
EP08849161.8A Active EP2215659B1 (de) 2007-11-14 2008-11-06 Rückwärtsleitender bipolarer transistor mit isoliertem gate und herstellungsverfahren dafür

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP08849161.8A Active EP2215659B1 (de) 2007-11-14 2008-11-06 Rückwärtsleitender bipolarer transistor mit isoliertem gate und herstellungsverfahren dafür

Country Status (5)

Country Link
US (1) US8450777B2 (de)
EP (2) EP2061084A1 (de)
JP (1) JP5693962B2 (de)
CN (1) CN101861651B (de)
WO (1) WO2009062876A1 (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2713386A1 (de) * 2012-09-27 2014-04-02 STMicroelectronics S.r.l. Herstellungsverfahren für Halbleiter-Bauelemente, wie Super-Barriere SBR Gleichrichter
WO2015039274A1 (zh) * 2013-09-17 2015-03-26 江苏物联网研究发展中心 一种ti-igbt器件及其制造方法
US9159819B2 (en) 2014-02-20 2015-10-13 Infineon Technologies Ag Semiconductor device and RC-IGBT with zones directly adjoining a rear side electrode
WO2018172977A1 (en) * 2017-03-20 2018-09-27 Infineon Technologies Austria Ag Power semiconductor device

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100117117A1 (en) * 2008-11-10 2010-05-13 Infineon Technologies Ag Vertical IGBT Device
JP5686033B2 (ja) * 2011-04-27 2015-03-18 トヨタ自動車株式会社 半導体装置の製造方法
US20130341673A1 (en) * 2012-06-21 2013-12-26 Infineon Technologies Ag Reverse Conducting IGBT
CN103855203B (zh) * 2012-12-07 2018-06-01 中国科学院微电子研究所 一种逆导型绝缘栅双极晶体管结构及其制备方法
CN104425254A (zh) * 2013-08-30 2015-03-18 无锡华润上华半导体有限公司 一种igbt的制造方法
US9147727B2 (en) 2013-09-30 2015-09-29 Infineon Technologies Ag Semiconductor device and method for forming a semiconductor device
US9082629B2 (en) 2013-09-30 2015-07-14 Infineon Technologies Ag Semiconductor device and method for forming a semiconductor device
DE112014006733B4 (de) * 2014-06-11 2021-10-07 Hitachi, Ltd. Halbleitervorrichtung, Leistungsmodul, Leistungsumsetzer und Halbleitervorrichtungs-Herstellungsverfahren
JP6766885B2 (ja) 2016-12-08 2020-10-14 富士電機株式会社 半導体装置の製造方法
JP7325167B2 (ja) 2017-03-16 2023-08-14 富士電機株式会社 半導体装置の製造方法
JP7276407B2 (ja) * 2017-11-28 2023-05-18 富士電機株式会社 炭化珪素半導体装置
CN113544824A (zh) * 2019-09-05 2021-10-22 富士电机株式会社 半导体装置以及半导体装置的制造方法
GB2589543A (en) 2019-09-09 2021-06-09 Mqsemi Ag Method for forming a low injection P-type contact region and power semiconductor devices with the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4587713A (en) * 1984-02-22 1986-05-13 Rca Corporation Method for making vertical MOSFET with reduced bipolar effects
GB2241111A (en) * 1990-02-15 1991-08-21 Mitsubishi Electric Corp Transistors integrated with diodes
DE10261424B3 (de) * 2002-12-30 2004-07-01 Infineon Technologies Ag Verfahren zum Herstellen eines Emitters mit niedrigem Emitterwirkungsgrad
US20050017290A1 (en) * 2003-07-24 2005-01-27 Mitsubishi Denki Kabushiki Kaisha Insulated gate bipolar transistor with built-in freewheeling diode
US20070080407A1 (en) * 2005-10-06 2007-04-12 Sanken Electric Co., Ltd. Insulated gate bipolar transistor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3067687B2 (ja) * 1997-05-08 2000-07-17 富士電機株式会社 Ｉｇｂｔ駆動回路
CN1258210C (zh) * 2003-06-18 2006-05-31 北京工业大学 硅高速半导体开关器件制造方法
JP4791704B2 (ja) 2004-04-28 2011-10-12 三菱電機株式会社 逆導通型半導体素子とその製造方法
JP2007095997A (ja) * 2005-09-29 2007-04-12 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US7557386B2 (en) * 2006-03-30 2009-07-07 Infineon Technologies Austria Ag Reverse conducting IGBT with vertical carrier lifetime adjustment

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4587713A (en) * 1984-02-22 1986-05-13 Rca Corporation Method for making vertical MOSFET with reduced bipolar effects
GB2241111A (en) * 1990-02-15 1991-08-21 Mitsubishi Electric Corp Transistors integrated with diodes
DE10261424B3 (de) * 2002-12-30 2004-07-01 Infineon Technologies Ag Verfahren zum Herstellen eines Emitters mit niedrigem Emitterwirkungsgrad
US20050017290A1 (en) * 2003-07-24 2005-01-27 Mitsubishi Denki Kabushiki Kaisha Insulated gate bipolar transistor with built-in freewheeling diode
US20070080407A1 (en) * 2005-10-06 2007-04-12 Sanken Electric Co., Ltd. Insulated gate bipolar transistor
JP2007103770A (ja) * 2005-10-06 2007-04-19 Sanken Electric Co Ltd 絶縁ゲート型バイポーラトランジスタ

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2713386A1 (de) * 2012-09-27 2014-04-02 STMicroelectronics S.r.l. Herstellungsverfahren für Halbleiter-Bauelemente, wie Super-Barriere SBR Gleichrichter
US9018048B2 (en) 2012-09-27 2015-04-28 Stmicroelectronics S.R.L. Process for manufactuirng super-barrier rectifiers
WO2015039274A1 (zh) * 2013-09-17 2015-03-26 江苏物联网研究发展中心 一种ti-igbt器件及其制造方法
US9159819B2 (en) 2014-02-20 2015-10-13 Infineon Technologies Ag Semiconductor device and RC-IGBT with zones directly adjoining a rear side electrode
WO2018172977A1 (en) * 2017-03-20 2018-09-27 Infineon Technologies Austria Ag Power semiconductor device
CN108630665A (zh) * 2017-03-20 2018-10-09 英飞凌科技奥地利有限公司 功率半导体器件
CN108630665B (zh) * 2017-03-20 2021-11-09 英飞凌科技奥地利有限公司 功率半导体器件
US11843045B2 (en) 2017-03-20 2023-12-12 Infineon Technologies Austria Ag Power semiconductor device having overvoltage protection and method of manufacturing the same

Also Published As

Publication number Publication date
US20100270585A1 (en) 2010-10-28
EP2215659B1 (de) 2018-02-28
US8450777B2 (en) 2013-05-28
CN101861651A (zh) 2010-10-13
JP5693962B2 (ja) 2015-04-01
JP2011503889A (ja) 2011-01-27
WO2009062876A1 (en) 2009-05-22
EP2215659A1 (de) 2010-08-11
CN101861651B (zh) 2016-06-01

Similar Documents

Publication Publication Date Title
EP2215659B1 (de) Rückwärtsleitender bipolarer transistor mit isoliertem gate und herstellungsverfahren dafür
EP2223340B1 (de) Rückwärtsleitendes halbleiterbauelement und verfahren zur herstellung eines solchen rückwärtsleitenden halbleiterbauelements
EP2223341B1 (de) Verfahren zur herstellung eines rückwärtsleitenden halbleiterbauelements
US10651037B2 (en) Method for fabricating a doped zone in a semiconductor body
JPH08316479A (ja) 絶縁ゲート型半導体装置およびその製造方法
US7629665B2 (en) Semiconductor component with a channel stop zone
CN215527729U (zh) 功率器件
EP2234144B1 (de) Herstellungsverfahren für Leistungshalbleitervorrichtung
JP6681238B2 (ja) 半導体装置および半導体装置の製造方法
US7602025B2 (en) High voltage semiconductor device and method of manufacture thereof
US8324062B2 (en) Method for manufacturing a power semiconductor device
EP2602826A1 (de) Isolierte Gate-Leistungshalbleitervorrichtung und Verfahren zur Herstellung solch einer Vorrichtung
US11522047B2 (en) Non-punch-through reverse-conducting power semiconductor device and method for producing same
JP7364027B2 (ja) 半導体装置およびその製造方法
US12020935B2 (en) Method of manufacturing semiconductor device
US20230307532A1 (en) Semiconductor device and manufacturing method of semiconductor device
WO2023176887A1 (ja) 半導体装置および半導体装置の製造方法
JP5601816B2 (ja) 半導体装置の製造方法
JP2020115550A (ja) 半導体装置および半導体装置の製造方法
CN116799034A (zh) 半导体器件和半导体器件的制造方法
GB2589543A (en) Method for forming a low injection P-type contact region and power semiconductor devices with the same
JP2008277458A (ja) 高耐圧半導体装置およびその製造方法

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL BA HR MK RS

AKX Designation fees paid
REG Reference to a national code

Ref country code: DE

Ref legal event code: 8566

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20100126