GB2589543A - Method for forming a low injection P-type contact region and power semiconductor devices with the same - Google Patents

Method for forming a low injection P-type contact region and power semiconductor devices with the same Download PDF

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Publication number
GB2589543A
GB2589543A GB1912918.8A GB201912918A GB2589543A GB 2589543 A GB2589543 A GB 2589543A GB 201912918 A GB201912918 A GB 201912918A GB 2589543 A GB2589543 A GB 2589543A
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layer
main side
dopants
conductivity type
electrical contact
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GB201912918D0 (en
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Rahimo Munaf
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Mtal GmbH
MQSemi AG
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Mtal GmbH
MQSemi AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Abstract

Aluminium is used as a P-type dopant for a contact region 8, while boron is used to form a body region 9. Implanted Al ions will form a higher level of defects that will act as recombination centres leading to lower carrier lifetimes and hence will reduce the injection levels of this region. Due to the higher diffusion coefficient of Al ions compared to B ions in silicon a lower temperature budget is needed to achieve the required depth of the P-type contact region 8. Hence, annealing the Al implant at temperatures below 900C will provide enough activation levels and dopant depth to achieve simultaneously a good ohmic contact to the contact electrode 3, and N+ source 7 protection, while providing lower hole drainage injection levels. This concept can be used in bipolar and unipolar semiconductor devices alike, e.g. IGBTs and MOSFETs, and is particularly beneficial for reverse conducting type of devices such as RC-IGBTs.

Description

DESCRIPTION
METHOD FOR FORMING A LOW INJECTION P-TV PE CONTACT REGION AND
POWER SEMICONDUCTOR DEVICES WITH THE SAME
FIELD OF THE INVENTION
The invention relates to the field of power semiconductor devices, such as a method for manufacturing a bipolar semiconductor device and a design for a bipolar semiconductor device.
TECHNICAL BACKGROUND
For exemplification purposes, FIG. 1 shows a typical planar MOS cell cross section for an IGBT structure (100) which is also used in a MOSE ET (200) with a highly doped N-dope drain region (1) as shown i n see FIG. 2 and RC-IGBT (300) as shown in FIG. 3, where both additionally incorporate an anti-parallel diode in the same structure. The IGBT (100) includes a first layer (4) formed as an N-doped type base layer with a first main side (31) and a second main side (21) opposite the first main side (31). A second P-doped type layer (9) is arranged on the first main side (31). On the second layer (9), a third P-doped type layer (8) is arranged on the first main side (31) in such a way that the layer (9) completely surrounds it. Layer (8) forms what is called a P-type contact region in an IG BT. For a punch-through IGBT shown in FIG. 1, an N-type field stop buffer layer (5) is added on the second main side (21) which incorporates a P-type collector or anode layer (6) between the buffer layer (5) and the collector contact layer (2). A none punch-through IGBT is structured without the field stop buffer layer (5).
In addition, by processing the second main side (21), an integrated diode functionality can be provided for an IGBT. For example, U.S. Pat No. 8,435,863 and U.S. Pat No. 8,508,016 disclose a method of creating various reverse conducting bipolar semiconductor devices having a patterned structure on the second main side (21), at least one layer on the second main side having alternating dopant regions including at least one first region of the first conductivity N-type (1) and at least one second region of the second conductivity P-type (6) as shown in the RC-IGBT (300) in FIG. 3. For exemplification purposes, FIG. 4 shows a typical trench MOS cell cross section for an IGBT structure (400) which can also be used in MOSFETs and RC-IGBTs.
For both the planar and trench MOS cell design concepts, a highly doped P-type layer (8) referred to as a contact region is included in the MOS cell to provide two critical functions: (a) to ensure a good Ohmic contact to the emitter contact (3) and, (b) to protect the highly doped N-type source region (7) from injecting electrons during device turn-off which can lead to device failure. In prior art, the highly doped P-doped layer (8) and the lower P-doped layer (9) are obtained by implantation of Boron (B) ions. Boron ions provide faster diffusion with better controllability in Silicon wafers to achieve finer device features, and also it does not out-diffuse at the surface which provides high quality Ohmic contacts to overlaying metal layers. After implantation through a mask, the Boron ions are subsequently diffused and activated at high temperatures above 9006C. However, this process will provide full activation of the Boron dopants so that the P-doped layer (8) will increase the drainage levels of holes during IGBT conduction, resulting in higher on-state or conduction losses. In addition, for R C-IG BTs and MOSF ET s with an integrated anti-parallel diode, this highly doped P-type layer (8) leads to higher injection levels in diode mode, which will result in increased switching losses. Hence, it is important to provide an arrangement for the P-type doped layer (8) and P-type doped layer (9) which can provide simultaneously a good Ohmic contact and N-type source (7) protection with less impact on the hole drainage and diode mode i nject on levels.
To address the issue of optimizing the diode mode in RC-IGBTs, the U.S. Pat Na 8,450,777 describes prior art using implantation of Hydrogen or Helium ion, for example, or Phosphorous or Boron ions, for example on the first main side (31). The phosphorous or boron ions may be multiple charged ions, such as double charged boron (B++) or triple charged phosphorous (P+++), for example. Furthermore, the U.S. Pat Na 7,400,017 describes an RC-IGBT with a recombination layer formed through the diode section as well as through the IG BT section by uniform Helium irradiation. J P 2007-103770 also discloses an R C -IG BT The lifetime controlIing in di ode mode is improved by introducing I ocal recombination layers, which are arranged in the first layer in the diode section close to the second main side (21) through ion irradiation.
The above described prior art is complex and requires additional masks, high energy irradiation processes and additional thermal budgets which may impact the distribution of the layers inside the semiconductor device, and its overall performance. It is thus desirable to identify a simpler and more efficient method to form a P-type doped layer (8) which can provide simultaneously a good Ohmic contact and N-type source (7) protection with less impact on the hole drainage and diode mode inj ecti on levels and is applicable to all types of bipolar semiconductors (punch-through as well as non-punch-through, standard as well as reverse-conduct ng type).
o DISCLOSURE OF THE INVENTION
It may be an object of the present i nventi on to provide a novel concept for manufacturing a reverse conducting bipolar semi conductor using an innovative forming method of the highly doped P-type contact region which provides improved diode and IGBT performance and reduces the need for additional complex processes for providing recombination centre required for opti mi sing the integrated anti-parallel di ode behaviour.
These objects may be met by the subject matter of the independent claims. Embodiments of the invention are described with respect to the dependent c I ai ins.
An exemplary embodiment of the present disclosure provides a method of manufacturing an insulated gate bipolar transistor. The exemplary method can include the following steps: forming a first layer of a first conductivity type on a part of a wafer of the first conductivity type having a first main side and a second main side opposite the first main side; creat ng a second layer of second conductivity type and a fourth layer of the first conductivity type on the first main side, the fourth layer being surrounded by the second layer and forming a first opening above the second layer; creating a third layer of a second conductivity type with a different P-type doping species than the second layer on the first main side, the third layer being fully surrounded by the second layer, and the fourth layer not covering the central parts of the thi rd layer; creating a electrically insulating layer on the first main side, the electrically insulating layer partially covering the at least one of the first layer, the second layer, and the fourth layer; creating an electrically conductive layer on the first main side to be insulated from the wafer by the electrically insulating layer, forming an opening over the third layer and part of the fourth layer, creating an additional electrically insulating layer fully covering the at least the electrically conductive layer and the electrically insulating I ayer, and partially covering the fourth layer; creating a first electrical contact on the first main side, the first electrical contact being in direct contact with the third layer and the fourth layer within the first opening; creating at least one fifth layer of the first conductivity type and at least one sixth layer of the second conductivity type on the second main side, the at least one fifth and sixth layers being arranged successively at the bottom of the first layer; finally, creating a second electrical contact on the second main side to be in di rect electrical contact with the at least the sixth layer. For an RC-IGBT, the sixth layer of second conductivity type can be formed for example as an alternate pattern of oppositely doped regions, all in direct contact with the second electrical contact on the second main side, or by any other means known to rio create a shorted collector in an IGBT.
An exemplary embodiment provides an IG BT type device. The exemplary IG BT includes a fi a layer of a first conductivity type with a first main side and a second main side opposite the first main side, and a second layer of a second conductivity type arranged on the first main side. The exemplary IGBT also includes at least one third layer of a second conductivity type with a different P-type doping species than the second layer, completely surrounded by the second layer; a fourth layer of a first conductivity type arranged on the first main side and surrounded by the second layer, and an electrically insulating layer arranged on the first main side and partially covering the at least one fourth layer. In additi on, the exemplary IG BT includes an electrically conductive layer arranged on the first main side and being electrically insulated from the at least one first layer, the fourth layer and the second layer by the electrically insulating layer, in such a way that the electrically insulating layer does not cover the thi rd layer, and only partially covers the fourth layer. The exemplary IGBT also includes an additional electrically insulated layer arranged on the first side completely covering the electrically insulating and electrically conductive layers, and forming a first opening above the third layer and part of the fourth layer; and a first electrical contact arranged on the first main side in direct electrical contact with the third layer and the fourth layer within the first opening and at least one fifth layer of the first conductivity type and at least one sixth layer of the second conductivity type on the second side, the at least one fifth and sixth layers being arranged successively at the bottom of the first layer. The IGBT also includes a second electrical contact arranged on the second main side in direct electrical contact with the at least sixth layer. An exemplary RC-IGBT may differently replace the uniformly doped sixth layer with an alternate pattern of oppositely doped regions in direct contact with the second electrical contact on the second side, or with any other means known to those skilled in the field to form a shorted collector in an IG BT.
Further preferred embodiments of the inventive subject matter are disclosed in the dependent claims.
BRIEF DESCRIPTION OF THE DRAWINGS
The embodiments of the invention will be explained in more detail in the following text with reference to the attached drawings, in which: FIG. 1: shows the cross section of planar type IGBT device, where layer (8) can be formed with Boron ions according to prior art, or with A I umi ni um ions and according to the inventive step.
FIG. 2: shows the cross section of planar type M OS F E T device, where layer (8) can be formed with Boron ions according to prior art, or with Al umi ni urn ions and according to the inventive step.
FIG. 3: shows the cross section of planar type RC -IG BT device, where layer (8) can be formed with Boron ions according to prior art, or with Al umi ni um ions and according to the inventive step.
FIG. 4: shows the cross section of trench type IG BT device, where layer (8) can be formed with Boron ions according to prior art, or with A I umi ni um ions and according to the inventive step.
The reference symbols used in the figures and their meaning are summarized in the list of reference symbols. The drawings are only schematically and not to scale. Generally, alike or al i ke-functi oni ng parts are given the same reference symbols. The described embodiments are meant as examples and shall not confine the invention.
MODES FOR CARRYING OUT THE INVENTION
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as top," 'bottom" 'front" 'back," 'leading," "trailing," etc., is used with reference to the orientation of the Figure (s) being described. Because components of embodi ments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
Reference will now be made in detail to various embodiments, one or more examples of io which are illustrated in the figures. Each example is provided by way of explanation, and is not meant as a limitation of the invention. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment It is intended that the present invention includes such modifications and variations. The examples are described using specific language which should not be construed as I i miti ng the scope of the appending claims. The drawings are not scaled and are for illustrative purposes only. For clarity, the same elements or manufacturing steps have been designated by the same references in the different drawings if not stated otherwise.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, e. g., those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art However, should the present disclosure give a specific meaning to a term deviating from a meaning commonly understood by one of ordinary skill, this meaning is to be taken into account in the specific context this definition is given herein.
In this specification, N -doped is referred to as first conductivity type while P -doped is referred to as second conductivity type. Alternatively, the semiconductor devices can be formed with opposite doping relations so that the first conductivity type can be P -doped and the second conductivity type can be N -doped. Furthermore, some Figures ill ustrate relative doping concentrations by indicating or "+" next to the doping type. For example, "N-" means a doping concentration which is less than the doping concentration of an doping region while an ' N +" -doping region has a larger doping concentration than the N - -doping region. However, indicating the relative doping concentration does not mean that doping regions of the same relative doping concentration have to have the same absolute doping concentration unless otherwise stated. For example, two different N+ -doping regions can have different absolute doping concentrations. The same applies, for example, to an N+ -doping and a P+ -doping region.
Specific embodiments described in this specification pertain to, without being limited thereto, reverse conducting bipolar semiconductor devices.
It will be understood that when an element is referred to as being 'connected_ or 'coupled_ to another element, it can be directly connected or coupled to the other element or intervening elements may be present In contrast when an element is referred to as being directly connected" or "directly coupled_ to another element, there are no intervening elements present Other words used to describe the relationship between elements should be interpreted in a like fashion (e. g. 'between" versus 'directly between_, 'adjacent_ versus 'directly adjacent,_ etc.).
A method is disclosed for manufacturi ng a bi polar semiconductor device, which can have better electrical properties and provide better control compared to known bipolar punch-through and non-punch through semiconductor devices. A bipolar semiconductor device is also disclosed According to an exemplary embodiment Aluminium (Al) ions are used as the P-type dopants for the P++ doped contact layer (8), in combination with using Boron ions as dopants for forming the more critical channel layer (9) which defines the horizontal and/or vertical MOS channels. Since Al has nearly two and half time the atomic mass of a B atom, it will create a higher level of defects which can act as recombination centres for lowering the carrier lifetime, and hence reducing the injection levels of this layer in an R C-IG BT diode mode operation. Due to the higher diffusion coefficient of Al ions compared to B ions in Silicon, a lower temperature budget is needed to achieve the required depths of the P++ doped layer (8). Hence, annealing the A I i mpl ant at temperatures below 9006C will provide enough activation level sand dopant depths to simultaneously achi eve a good Ohmic contact and Ni-source protect on, while still providing lower hole drainage injection I evels.
Exemplary embodiments of the present disclosure also provide a method for manufacturing an Insulated Gate Bipolar transistor 100. In the exemplary method, the following steps may be performed: -starting with a lightly doped substrate of the first conductivity type which includes a first layer also called base layer (4), which has a first main side (31) (e.g. emitter side), and a second main side (21) (e.g. collector side) arranged opposite the first main side, - growing a layer of electrically insulating material (12) (e.g. gate oxide) on the substrate (4) facing the fi rst main side (31), - depositing a layer of electrically conductive material (10) (e.g. gate electrode) on top of the layer (12), -structuring the layers (10) and (12) and implanting fi rst dopants of second conductivity type into the base layer (4) from the direction of the first main side (31). Afterwards, the implanted dopants are diffused into the base layer (4) forming the second layer (9). The first dopants are preferably Boron ions. The first dopants are preferably implanted with an energy of 20-100 key and / or a dose of 5x1013 / cm2 to 2x1014 / cm2. The first dopants are driven into a maxi mum depth between 1 I m and 51 m in particular between 1 and 3 I m and in particular between 1 and 2 I m. T he first dopants are not only driven into the base layer (4) in a direction perpendicular to the surface, but they are spread out laterally under the gate electrode layer (10) and gate oxide (12), - implanting the second dopants of first conductivity type into the base layer (4) from the direction of the first main side (31), then diffusing the i mpl anted second dopants into the base layer (4) and forming the fourth layer (7). The second dopants are preferably zo Phosphorous or Arsenic, preferably Arsenic i ons. The second dopants are preferably i mpl anted with an energy of 80-160 key and / or a dose of 1x1015 / cm2 to 1016 /cm?. The second dopants are driven into a maxi mum depth between 0.5 I m and 1 I m. The second dopants are mainly driven into the base layer (4) in a direction perpendicular to the surface, but they are only slightly spread out laterally to form the critical source region under the gate oxi de (12), - growing or depositing the layer (13) of additional insulating material such as a low temperature oxide or LT 0; characterized in that the insulating oxi de layer thickness can range between 500nm to 1500nm, -creating an opening inlayer (13) using a mask, resulting in the contact opening area (14) on the fi rst mai n side (31), - afterwards, implanting the third dopants of second conductivity type through the contact opening (14) into the base layer (4). The third dopants are preferably Al ions. The diffusion of the dopants is done at temperatures below 9006C, and preferably below 8006C, or more preferably below 700EC forming the third layer (8). The third implants are preferably implanted with an energy above 50keV and/or a dose above 5x1014/cm2, preferably above 1015/cm2 and more preferably above 5x1015/cm2, - afterwards filling the contact opening (14) with metal to produce a direct electrical emitter contact (3) to the third layer (8) and the fourth layer (7), - thinning the base layer (4) from the second main side (21) if needed for low voltage power semiconductor devices, -implanting and diffusing first conductivity type dopants (eg. Hydrogen, Phosphorus ions) from the second main side (21) to form the fifth layer (5) which acts as a buffer layer in punch-through IG BTs. The fifth layer (5) has a doping concentration of, for example, at maximum 5x1017 atoms/cm3. The layer (5) can also be laser annealed in cases when the base layer (4) is made very thin. This layer can also be pre-diffused in the base layer (4) before any other processing steps are done, or can be omitted in non-punch-through semiconductor devices. In MOSFET type devices, the drain layer (1) of the first conductivity type can be also be very highly doped to provide a good Ohmic contact to the second side contact (2), - implanting and diffusing second conductivity type dopants from the second main side (21) to form the sixth layer (6) which acts as a col lector for the IG BT. For reverse conducting structures, additional first conductivity type dopants are introduced in layer (6) by various means (additional masks, etc) to produce collector shorts (1 and to enable the internal anti -parallel diode structure. Layer (6) can also be laser annealed in cases when the base layer (4) is made very thin. Layer (6) can be also omitted when the power semiconductor device structure is a uni polar MOS F ET-1 i ke device, - finally, a stack of metals is deposited on the second main side (21) to form the second electrical contact (2).
An enhancement layer or fourth dopants of lightly doped first conductivity type can also be implanted and diffused before the first dopants implant T he fourth dopants are i mpl anted and diffused into the base layer (4) from the first main side (31). The fourth dopants are preferably Phosphorous ions. The fourth dopants are preferably implanted with an energy of 20-100keV and/or a dose of 5x1012 / cm2 to 5x1013 / cm2. The fourth dopants are driven into a maximum depth between 2 1 m and 8 1 rn, in particular between 2 and 6 1 m and in pardcular between 2 and 4 I m. The fourth dopants are not only driven into the base layer (4) in a direction perpendicular to the surface, but they are spread out laterally in such a way that they surround the second layer (9).
An IG BT (100) is formed between the second electrical contact (2), part of which forms a collector electrode in the IG BT, the sixth layer (6), which forms a collector region in the IGBT, the first layer (4), part of which forms a base layer, the second and third layers (8) and (9), part of which form a P-type channel layer in the IGBT, the fourth layer (7), which forms a highly doped source region in the IGBT, and the first electrical contact (3), which forms an emitter electrode. During an on-state of the IGBT, a horizontal channel (15) is formed between the electrical contact (3), the layer (7) and layer (9).
An exemplary power semi conductor device is disclosed comprising: -a substrate with at least a two-layer structure with layers of a first and a second conductivity type, one of the layers being a first base layer (4) of the first conductivity type, with a first main side (31) (e.g., emitter side), on which a first electrical contact is arranged (3), and an opposite second main side (21) (e.g., col lector side), on which a second electrical contact is arranged (2), -a second layer (9) of the second conductivity type and a fourth layer of first conductivity type are arranged on the base layer (4) on the first main side (31); characterized in that layer (7) is completely surrounded by layer (9), -a third layer of second conductivity type (8) formed by different category of ions than the second layer (9); characterized in that the layer (8) is in direct electrical contact with the first side contact (3) through the contact opening area (14); characterized in that the layer (8) is deeper than layer (7), -a layer (12) and additional layer (13) of insulating materials, separating the electrical I y conductive layer (10) from the first contact (3) and the base layer (4); characterized in that an horizontal MOS channel (15) is formable on the first main side between the electrical contact (3), the layer (7), the layer (9) and the base layer (4), -a fifth layer (5) of first conductivity type (e.g. buffer layer) arranged on the base layer (4) towards the second main side (21), having higher doping concentration than the base layer (4). The fifth layer can also be omitted in non-punch-through semiconductor devices, -a sixth layer (6) of second conductivity type which can be also omitted in MOSFET like devices (200) as shown in FIG. 2, or can be formed as an alternate pattern of P/N doped regions in case of reverse conducting semiconductor devices (300) as shown in FIG. 3.
For another exemplary embodiment (400) shown in FIG. 4, the manufacturing method is identical to the one described previously, with the exception of an additional dry etch step needed to form the trench type structures in the base layer (4). Subsequently, al l other layers are formed by the processes specified above. An IGBT is formed between the second electrical contact (2), part of which forms a collector electrode in the IGBT, the sixth layer (6), which forms a collector region in the IGBT, the first layer (4), part of which forms a base layer, the second and third layers (8) and (9), part of which form a P-type contact and channel layers respectively in the IGBT, the fourth layer (7), which forms a highly doped source region in the IGBT, and the first electrical contact (3), which forms an emitter electrode. During an on-state of the IGBT, a vertical channel (16) is formable between the electrical contact (3), the layer (7) and the layer (9) towards the base layer (4).
The top side of the IGBT structure is indicated for exemplification purposes as a stripe type cell design, however it is understood that other features are also included in the embodiment such as the cells having any shape like a square, rectangular or a circle or any other regular or irregular shape.
In yet another embodiment, a method for manufacturing an Insulated Gate Bipolar transistor (100) is provided, and the following steps may be performed: -starting with a lightly doped substrate of the first conductivity type which includes a first layer also called base layer (4), which has a first main side (31) (e.g. emitter side), and a second main side (21) (e.g. collector side) arranged opposite the first main side, - growing a layer of electrically insulating material (12) (e.g. gate oxide) on the substrate (4) facing the first main side (31), -depositing a layer of electrically conductive material (10) (e.g. gate electrode) on top of the layer (12), - structuring the layers (10) and (12) with a mask, and implanting first dopants of second conductivity type into the base layer (4) from the direction of the first main side (31). Afterwards, the implanted dopants are diffused into the base layer (4) forming the second layer (9). The first dopants are preferably Boron ions. The first dopants are preferably implanted with an energy of 20-100 key and / or a dose of 5x1013 / cm2 to 2x1014 / cm2. The first dopants are driven into a maximum depth between 1 I m and Sim, in particular between 1 and 31 m and in particular between land 21 m. The first dopants are not only driven into the base layer (4) in a direction perpendicular to the surface, but they are spread out laterally under the gate electrode layer (10) and gate oxide (12), - implanting the second dopants of first conductivity type into the base layer (4) from the direction of the first main side (31), then diffusing the i mpl anted second dopants into the base layer (4) and forming the fourth layer (7). The second dopants are preferably Phosphorous or Arsenic, preferably Arsenic i ons. The second dopants are preferably i mpl anted with an energy of 80-160 key and / or a dose of 1x1015 1cm2 to 1016 / cm2. The second dopants are driven into a maxi mum depth between 0.5 I m and 1 I m. The second dopants are mainly driven into the base layer (4) in a direction perpendicular to the surface, but they are only slightly spread out laterally to form the critical source region under the gate oxi de (12), - afterwards, implanting the third dopants of second conductivity type into the base layer (4) from the direction of the first main side (31). The third dopants are preferably Al ions. The third implants are preferably i mpl anted with an energy above 50keV and/or a dose above 5x1014/cm?, preferably above 1015/cm2 and more preferably above 5x1015/cm2, - growing or depositing the layer (13) of insulating material such as a low temperature oxide or LT O. The insulating oxide layer thickness can range between 500nm to 1500nm During this step, the substrate is exposed at temperatures up to 10006C, and the third dopants are also diffused in the base layer (4), forming the third layer (8), -creating an opening inlayer (13) using a mask, resulting in the contact opening area (14) on the first main side (31), - afterwards filling the contact opening (14) with metal to produce a direct electrical emitter contact (3) to the third layer (8) and the fourth layer (7), -thinning the base layer (4) from the second main side (21) if needed for low voltage power semiconductor devices, -implanting and diffusing first conductivity type dopants (eg. Hydrogen, Phosphorus ions) from the second main side (21) to form the fifth layer (5) which acts as a buffer layer in punch-through IG BT s. The fifth layer (5) has a doping concentration of, for example, at maximum 1x1017 atoms/cm3. The layer (5) can also be laser annealed in cases when the base layer (4) is made very thin. This layer can al so be pre-diffused in the base layer (4) before any other processing steps are done, or can be omitted in non-punch-through semiconductor devices. In MOS F ET type devices (200), the drain layer (1) of the first conductivity type can be very highly doped to provide a good Ohmic contact to the second side contact (2), - implanting and diffusing second conductivity type dopants from the second main side (21) to form the ninth layer (6) which acts as a col I ector for the IG BT. For reverse conducting structures (300), additional first conductivity type dopants are introduced in layer (6) by various means (additional masks, etc) to produce collector shorts (1') and to enable the internal anti -parallel diode structure. Layer (6) can also be laser annealed in cases when the base layer (4) is made very thin. Layer (6) can be also omitted when the power semiconductor device structure is a uni polar M OS F ET -li ke device (200), -finally, a stack of metals is deposited on the second main side (21) to form the second electrical contact (2).
Reference list 1: MOSFET drain layer of first conductivity type RC-IGBT short layer of first conductivity type 2: second side metallization (electrical contact) 21: second main side 3: first side metallization (electrical contact) 31: fi rst mai n si de 4: first base layer of first conductivity type 5: fifth layer of first conductivity type 6: sixth layer of second conductivity type 7: fourth layer of first conductivity type 8: third layer of second conductivity type 9: second layer of second conductivity type 10, 11: gate electrodes from electrically conductive layers 12, 12-: insulating layers (gate oxides) in the semiconductor devices 13: insulation layer (low temperature oxide or LT 0) 14: contact mask opening 15: planar (horizontal) MOS channel 16: trench (vertical) MOS channel 100: planar MOS cell IGBT 200: planar MOS cell MOS F ET 300: planar MOS cell RC-IGBT 400: trench MOS cell IGBT

Claims (15)

  1. CLAIMSWhat is claimed is: 1. A semi conductor device comprising: a first layer of a first conductivity type with a first main side and a second main side opposite the first main side; a second layer of a second conductivity type arranged on the first main side; at least one third layer of the second conductivity type arrange on the first main side and surrounded by the second layer; characterized in that, the dopant species are different than the dopant of the second layer of the same second conductivity type; at least one fourth layer of first conductivity type arranged on the first main side and surrounded by the second layer; characterized in that the fourth layer does not completely cover the third layer; an electrically conductive layer arranged on the first main side and being electrically insulated from the at least fourth layer, the second layer and the first layer, by a layer of electrically insulating material, which is arranged on the first main side and partially covers the at least one fourth layer; characterized in that the electrically conductive layer forms a planar gate electrode; an additional electrically insulating layer covering the electrically conductive layer where the electrically conductive layer is embedded between the two separate electrical ly insulating I ayers; a first electrical contact arranged on the first main side in direct electrical contact with the third layer and the fourth layer within the contact opening; characterized in that, the first electrical contact is completely separated from the electrical ly conductive layer by the additional electrically insulating layer; at least one fifth layer of the first conductivity type, and at least one sixth layer of the second conductivity type, which are arranged on the second main side, the at least one fifth and sixth layers being arranged successively in a plane; a second electrical contact arranged on the second main side in direct electrical contact with the at least one sixth layer.
  2. 2. A method for manufacturing a semiconductor device according to claim 1, comprising the following steps: -starting with a lightly doped substrate of the first conductivity type which includes a first layer also cal led base layer, which has a first main side and a second mai n side arranged opposite the first main side; - growing a layer of electrically insulating material on the base layer facing the first main side; - depositing a layer of electrically conductive material on top of the sixth layer, - structuring the electrically insulating and electrically conductive layers, and i mplanfi ng first dopants of second conductivity type into the base layer from the direction of the first main side. Afterwards, diffusing the dopants and forming the second layer; -implanting the second dopants of first conductivity type into the base layer from the direction of the first main side, then diffusing the implanted second dopants into the base layer and forming the fourth layer; -growing or depositing the additional layer of insulating material such as a low temperature oxide or LT 0; characterized in that the insulating oxide layer thickness can 15 range between SOOnm to 1500nm; - creating an opening in the additional insulating layer using a mask, resulting in a contact opening area on the first main side; - implanting the third dopants of second conductivity type through the contact opening and into the base layer, characterized in that, the third dopants are of different species than the fi rst dopants; -filling the contact opening with metal to produce a direct electrical contact to the third layer and the fourth layer; - thinning the base layer from the second main side, if needed for low voltage power semi conductor devices; -implanting and diffusing first conductivity type dopants from the second main side to form the fifth layer which can be a buffer layer or field stop layer; characterized in that the fifth layer has a doping concentration higher than the base layer; -implanting and diffusing second conductivity type dopants from the second main side to form the sixth layer which acts as a collector for a bipolar semiconductor device; characterized in that the sixth layer can be omitted in an uni polar device; -depositing a suitable stack of metals on the second main side to form the second electrical contact.
  3. 3. A method for manufacturing a semi conductor device according to claim 1, comprising the following steps: -starting with a lightly doped substrate of the first conductivity type which includes a first layer also cal led base layer, which has a first main side and a second main side arranged opposite the first main side; - growing a layer of electrically insulating material on the base layer facing the first main side; -depositing a layer of electrically conductive material on top of the electrically insulating layer, -structuring the electrically conductive and electrically insulating I ayers, and i mpl anti ng first dopants of second conductivity type into the base layer from the direction of the first main si de. Afterwards, diffusing the dopants and formi ng the second layer; -implanting the second dopants of first conductivity type into the base layer from the direction of the fi rst main side, then diffusing the implanted second doparis into the base layer and forming the fourth layer - implanting the third dopants of second conductivity type into the base layer from the direction of the first main side; characterized in that, the third dopants are of different species than the first dopants; - growing or depositing the additional layer of electrically insulating material such as a low temperature oxide or L T 0; characterized in that the insulating oxi de layer thickness can range between 500nm to 1500nm, and due to the temperature of the process, simultaneously diffusing the third dopants to form a third layer; -creating an opening in the additional el ectri cal ly insulating layer using a mask, resulting in a contact opening area on the first main side; -filling the contact opening with metal to produce a direct electrical contact to the third layer and the fourth layer; - thinning the base layer from the second main side, if needed for low voltage power semi conductor devices; -i mpl anti ng and diffusing first conductivity type dopants from the second main side to form the fifth layer which can be a buffer layer or field stop layer; characterized in that the fifth layer has a doping concentration higher than the base layer; -implanting and diffusing second conductivity type dopants from the second main side to form the sixth layer which acts as a collector for a bipolar semiconductor device; characterized in that the sixth layer can be omitted in an uni polar device; -depositing a stack of suitable metals on the second main side to form the second electrical contact.
  4. 4. A method for manufacturing a semiconductor device according to claim 1 and either one of the claims 2 or 3, where the first dopants can be Boron ions, and the third dopants are defined to be A I umi ni um ions.
  5. 5. A method for manufacturing a semiconductor device according to claim 4, wherein the A lions are implanted with an energy above 50keV and a dose above 5x1014/c m2, preferably above 1015/cm2 and more preferably above 5x1015/cm2.
  6. 6. A method for manufacturing a semiconductor device according to claims 2 and 5, wherein the diffusion of the Al ion dopants is done at temperatures below 900K, and preferably below 8006C, or more preferably below 700K.
  7. 7. A method for manufacturing a semiconductor device according to claims 3 and 5, wherein the diffusion of the Al ion dopants is done at temperatures above 9004C, and preferably above 1000K.
  8. 8. A method for manufacturing a semiconductor device according to either one of the claims 2 or 3, wherein the fifth layer can also be formed by a laser anneal process.
  9. 9. A method for manufacturing a semiconductor device according to either one of the claims 2 or 3, wherein the fifth layer can also be pre-diffused in the substrate before the processing takes place.
  10. 10. A method for manufacturing a semiconductor device according to either one of the claims 2 or 3, wherein the sixth layer can also be formed by a laser anneal process.
  11. 11. A reverse-conducting insulated gate bipolar transistor according to claim 1, wherein the at least one sixth layer is formed as an alternating pattern of first and second conductivity type regions to create shorts for the diode part of the R C-IG BT.
  12. 12. A semi conductor device according to claim 1, comprising an electrically insulating layer formed as a trench gate electrode, which is arranged in the same plane and adjacent to the second layer, the trench gate electrode being electrically insulated from the first layer, second layer and fourth layer by the layer of electrically insulating material.
  13. 13. An unipolar semiconductor device according to claims 1 and 2 or 3, such that wherein all layers are identical, with the excepti on of the sixth layer which is completely omitted, wherein the fifth layer is highly doped and in direct contact with the second electrical contact such that an excel lent Ohmic contact is provided to the second electrical contact.
  14. 14. A semiconductor device according to claims 1, 12 or 13, comprising an active cell formed between two gate electrodes, wherein the third and fourth layers are electrically connected to the first electrical contact between two gate electrodes; and, wherein the transistor comprises a plurality of said active cel Is which are arranged di redly adjacent to each other; characterized in that the said active cel Is can be arranged in different patterns such as stripes, hexagons, or any other geometrical shape.
  15. 15. A converter with a semiconductor device according to any of the c I ai ms 1 thru 14.
GB1912918.8A 2019-09-09 2019-09-09 Method for forming a low injection P-type contact region and power semiconductor devices with the same Pending GB2589543A (en)

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