EP2041584B1 - High-speed signal testing system having oscilloscope functionality - Google Patents

High-speed signal testing system having oscilloscope functionality Download PDF

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Publication number
EP2041584B1
EP2041584B1 EP07799568A EP07799568A EP2041584B1 EP 2041584 B1 EP2041584 B1 EP 2041584B1 EP 07799568 A EP07799568 A EP 07799568A EP 07799568 A EP07799568 A EP 07799568A EP 2041584 B1 EP2041584 B1 EP 2041584B1
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EP
European Patent Office
Prior art keywords
signal
time
bit
clock signal
repeating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Not-in-force
Application number
EP07799568A
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German (de)
English (en)
French (fr)
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EP2041584A4 (en
EP2041584A2 (en
Inventor
Mohamed M. Hafed
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DFT Microsystems Inc
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DFT Microsystems Inc
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Publication date
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Publication of EP2041584A4 publication Critical patent/EP2041584A4/en
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Publication of EP2041584B1 publication Critical patent/EP2041584B1/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31932—Comparators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R13/00—Arrangements for displaying electric variables or waveforms
    • G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form

Definitions

  • the present invention relates generally to the measurement of high-speed digital data. More particularly, the present invention is directed to a high-speed signal testing system having oscilloscope functionality.
  • a logic analyzer or a bit-error-rate tester is used for pattern testing and an oscilloscope or jitter analyzer is used for eye diagram testing or jitter testing.
  • a logic analyzer or a bit-error-rate tester is used for pattern testing
  • an oscilloscope or jitter analyzer is used for eye diagram testing or jitter testing.
  • a test-related module or component can be placed on a system to perform the digital testing functions.
  • Many high-speed serial receivers now contain a pattern checker for the purpose of digital testing. Adding oscilloscope capability to this basic pattern checking capability is highly desired, but not trivial.
  • analog delay line circuitry is introduced that can delay a data signal or a clock signal, or both, by very small amounts (fraction of data pattern unit interval).
  • the delay line circuitry is area-consuming, bandwidth-limited, and difficult to calibrate. It becomes unmanageable when several test channels are required, as is the case in modem applications or applications in which the pattern tester is integrated within a system.
  • US 5,883,523 describes a circuit tester, which stimulates an analog circuit device under test (DUT) with a test signal and periodically digitizes a resulting DUT output signal to produce an output data sequence that may be analyzed to ascertain DUT operating characteristics.
  • the tester is powered by a switching power supply that induces periodic noise spikes in the DUT output signal.
  • the period of the switching power supply noise is made coherent with the digitization period. The phase of digitization is then adjusted so that the tester avoids digitizing the noise spikes in the DUT output signal.
  • EP 1 571 455 discloses a solution wherein a signal from a power supply line is caused to pass through a high pass filter, and a first signal is generated by adding a voltage-divided signal to the signal. In addition, a second signal obtained by adding the voltage-divided signal to an identification voltage is generated. A comparator outputs a comparison result of comparing a voltage of the first signal with a voltage of the second signal, and a counter counts up a count value when the voltage of the first signal is higher than that of the second signal. A sample hold circuit sample-holds the count value just before the counter is reset.
  • One aspect of the present invention is a system for testing a high-speed repeating data signal, comprising: a time-base generator responsive to a reference clock signal so as to generate a high-speed repeating signal; a one-bit voltage digitizer for digitizing the high-speed repeating data signal into a digitized signal as a function of the high-speed repeating signal; a digital comparator for comparing the digitized signal to a selected digital value and outputting comparator results as a function of the high-speed repeating signal; a bit-shift and frequency-divider block responsive to the high-speed repeating signal so as to produce a slowed clock signal; a sub-sampler for sub-sampling the comparator results as a function of the slowed clock signal so as to output sub-sampled results; a modulo N address counter for providing write addresses as a function of the high-speed repeating signal; and an accumulation memory for storing ones of the sub-sampled results as a function of the slowed clock signal and corresponding respective ones
  • oscilloscope circuitry that includes: a time-base generator responsive to a reference clock signal so as to generate a high-speed repeating signal; a one-bit voltage digitizer for digitizing the high-speed repeating data signal into a digitized signal as a function of the high-speed repeating signal; a reference pattern memory for storing a reference bit pattern having a length B; a selector for selecting between the reference bit pattern and a constant bit value so as to output a selected digital value; a digital comparator for comparing the digitized signal to the selected digital value and outputting comparator results as a function of the high-speed repeating signal; a bit-shift and frequency-divider block responsive to the high-speed repeating signal so as to produce a slowed clock signal, the bit shift and frequency divider block divides the high-speed repeating signal by B; a sub-sampler for sub-sampling the comparator results as a function of
  • Still another aspect of the present invention is a method of implementing an oscilloscope to analyze a high-speed data signal, comprising: digitizing the high-speed data signal into a one-bit digitized signal in response to a repeating time-base signal having a time-base span N; comparing the one-bit digitized signal to a constant bit value in response to the repeating time-base signal so as to generate comparator results; dividing the repeating time-base signal so as to create a slowed clock signal corresponding to high-speed data period; sub-sampling the comparator results in response to the slowed clock signal so as to output sub-sampled results; generating modulo N write addresses as a function of the repeating time-base signal; and storing ones of said sub-sampled results in a memory in response to the slowed clock signal and corresponding respective ones of the write addresses.
  • FIG. 1 shows a prior-art digital pattern tester 10 for testing logical integrity of an input signal 14 input into the tester.
  • tester 10 could be part of the design of a high-speed digital communications device (not shown), or it could be a standalone piece of equipment, such as a BERT or logic analyzer.
  • the front-end of tester 10 is a voltage comparator 18 that "slices" the voltage of incoming signal 14 and recovers a logical value from it.
  • the logical value is "1" when the input signal is larger than the voltage threshold of comparator 18 and "0" otherwise.
  • the logical value is then compared, bit for bit, to a reference pattern 26 stored in an onboard memory 30.
  • An error counter 34 keeps track of the number of mismatches between the logical values derived from input signal 14 on the one hand and the corresponding respective bits of reference pattern 26 on the other.
  • Digital comparator 22 is clocked by an onboard clock signal 38 that is centered at the middle of the data bit that is being compared. This minimizes the likelihood of a sampling error.
  • the centering operation either happens with delay lines (not shown) on the clock signal or with a phase tracking circuit (not shown), such as a clock-and-data recovery (CDR) circuit.
  • CDR clock-and-data recovery
  • a digital pattern alignment block (not shown) that shifts reference pattern 26 until the least amount of errors is observed.
  • reference clock 42 provided to tester 10 can be at a low frequency, with subsequent multiplication, typically using a phase-locked loop (PLL) multiplier 46, to the target high-speed frequency.
  • multiplication can increase a 100 MHz clock signal to a 5 GHz sampling signal.
  • FIG. 2 this figure shows an exemplary digital pattern testing system 200 that includes an oscilloscope feature that enables the capture of oscilloscope traces of transition or non-transition bits.
  • exemplary testing system 200 is based on the design of pattern tester 10 of FIG. 1 , the major components of which are located within the dashed outline 204. That is, like tester 10 of FIG. 1 , testing system 200 of FIG. 2 includes a front end voltage comparator 208, a reference pattern memory 212, a digital comparator 216, a frequency-scaling PLL multiplier 220, and an error counter 224. As can further be seen comparing FIGS.
  • input 228 of PLL multiplier 220 is preceded by a multiplexer 236 and other components as described below to provide a high-frequency time-base generator 240, which may be, for example, any one of the time-base generators described in U.S. Patent No. 7 681 091 filed on July 12,2007 , and titled "Signal Integrity Measurement Systems And Methods Using A Predominantly Digital Time-Base Generator,” for all that it discloses relative to time-base generators.
  • multiplexer 236 is responsive to a selection signal 244 that continually selects between two inputs, which in this case are two versions of an incoming reference clock signal 248, an undelayed version 248A and a coarsely delayed version 248B that is delayed using a coarse delay 252.
  • Coarse delay is defined as any delay that is substantially larger than the minimum delay that can be reliably constructed using conventional technology. Typically, such delay is equivalent to minimum bit period in a high speed communications device.
  • the selectable input signals to multiplexer 236 may be any two or more clock signals that are coarsely delayed relative to one another.
  • selection signal 244 comes from an onboard circulating memory 256 that is clocked by incoming reference clock 248.
  • the combination of PLL multiplier 220, multiplexer 236, coarse delay 252 to create the delayed version 248B of clock signal 248, selection signal 244, and onboard memory 256 driving the selection signal constitute a time-base generator 240 that replaces any analog delay lines that are required in a conventional system.
  • the digital logic down stream of voltage comparator 208 is modified, for example, as shown in FIG. 2 .
  • the reference pattern 260 can be replaced by a constant logical value, such as 0.
  • Selection between the oscilloscope mode and the bit-pattern testing mode can be facilitated, for example, by a multiplexer 264 that allows selection between the constant logical 0 signal and the output of reference pattern memory 212.
  • Digital comparator 216 can remain the same as digital comparator 22 of FIG. 1 for simplicity if desired.
  • error counter 224 may be bypassed and replaced by a sub-sampling flip-flop 268.
  • sub-sampling flip-flop 268 serves the function of locking onto a single bit in the high-speed pattern being tested.
  • sub-sampling flip-flop 268 is driven by a bit-shift and frequency-divider block 272 responsive to the output 276 of time-base generator 240.
  • the frequency division of bit-shift and frequency-divider block 272 is set to a value equal to the length B of pattern 260. If pattern 260 is a pseudo-random bit sequence (PRBS) having a pattern length B of 127 bits, the frequency divider value is 127.
  • PRBS pseudo-random bit sequence
  • FIG. 3 shows the operation of bit-shift and frequency-divider block 272 ( FIG. 2 ) for a pattern 260A having length B of 11.
  • sub-sampling flip flop 268 FIG. 2 ) only looks at the digital comparison result every 11 data beats, instead of every data beat. It only looks at the comparison result for a single bit in the whole repeating pattern 260A.
  • the output of the sub-sampled comparison operation may be accumulated in an accumulation memory 280 having an address counter 284 clocked by time-base generator 240.
  • address counter 284 clocked by time-base generator 240.
  • the importance of addressing using address counter 284 this way is described below. For now, its is noted that because division ratio of bit-shift and frequency-divider block 272 is equal to pattern length B in FIG. 2 , the accumulation results may arrive into accumulation memory 280 out of order, but if certain guidelines are followed, all locations in the memory will be covered (see below).
  • each time PLL multiplier 220 toggles its output 276 is slightly delayed.
  • every time voltage comparator 208 is clocked, it strobes the incoming bit stream of input signal 288 at a slightly different delay.
  • every time sub-sampling flip flop 268 is clocked with the slowed-down clock of bit-shift and frequency-divider block 272, it, too, corresponds to a slightly different delay.
  • time-base generator 240 is programmed to generate a constant ramp (see the '825 patent application for a description of programming a time-base generator), the output 276 of PLL multiplier 220 is constantly advanced or delayed by a fixed amount according to the ramp behavior.
  • accumulation memory 280 Each entry in accumulation memory 280 is designed to correspond to a single delay value out of PLL multiplier 220. Thus, and referring to FIG. 4 , at the termination of one complete sweep of the time-base ramp, accumulation memory 280 will contain a time-domain waveform 400 corresponding to whether or not the transition bit being zoomed onto is higher than the voltage threshold of voltage comparator 208 ( FIG. 2 ).
  • FIG. 5 illustrates the setting of the threshold voltage of voltage comparator 208 ( FIG. 2 ) to a fixed value VB and running time-base generator 240 for a bit 500 of interest of data pattern 260B.
  • the result is a sequence 504 of ones and zeros that may be stored in accumulation memory 280. Incrementing the threshold voltage of voltage comparator 208 and re-running time-base generator 240, another sequence of ones and zeros is generated, and it is added to the previous set.
  • thermometer code like the thermometer code 600 shown in FIG. 6 is obtained.
  • the values of the thermometer code are directly accumulated in accumulation memory 280. It should be noted that this operation is different from the operation of generating bit error rate (BER) contour plots. This operation is literally a digitization operation of a repetitive voltage transition. It does not represent an error count the way a BER does.
  • BER bit error rate
  • FIG. 7 shows an exemplary test pattern 260C ( FIG.
  • exemplary time delay values 700 outputted by the time-base generator 240 exemplary time delay values 700 outputted by the time-base generator 240, exemplary memory address values 704, and the order 708 in which the memory values are filled.
  • pattern 260C has a length B of 5 bits and a bit 712 of interest.
  • Time-base generator 240 ramps through its various delays in a duration equivalent to 8 bit-values.
  • all memory values 704 are eventually filled as long as the sufficient number of iterations of the PLL ramp and of the bit stream is sequenced. If the length of accumulation memory 280 is not selected properly, aliasing effects occur, and erroneous measurements are made.
  • the number of iterations of the time-base ramp or the bit pattern 260C corresponds to the least common multiple between the pattern length B and the time-base span N.
  • the least common multiple between 5 and 8 is 40. So, 8 iterations of pattern 260C (or 5 of the time-base ramp) are required.
  • FIG. 7 notice how, at the start 716A of the timing waveform 716 shown, as PLL multiplier 220 keeps toggling and ramping its output delay, it comes across the bit of interest 712 (transition of interest) twice. This means that voltage comparator 208 samples that particular bit 712 (transition) with a small delay at first, then with a large delay subsequently. In the next iteration 716B of the ramp timing waveform 716, PLL multiplier 220 comes across the same transition repetitively again, but each time it does so, it does it with a unique one of delay value 700.
  • Length B of bit pattern 260 can be much smaller (e.g. 5 in the example above) or much larger (e.g., thousands of bits).
  • FIG. 8A shows an example of an output plot 800 of example digital bit stream 804 as generated using the oscilloscope functionality of an oscilloscope-enabled testing system made in accordance with the present disclosure, such as digital pattern testing system 200 of FIG. 2 .
  • bit stream 804 shows slow rise time and significant voltage noise. These effects are examples of what is being tested using an oscilloscope-enabled testing system of the present disclosure.
  • FIG. 8B shows an example of plot 808 generated by an oscilloscope-enhanced testing system of the present disclosure, such as digital pattern testing system 200 of FIG. 2 , when the testing system is zoomed in onto a rising transition 812.
  • FIG. 8A shows an example of an output plot 800 of example digital bit stream 804 as generated using the oscilloscope functionality of an oscilloscope-enabled testing system made in accordance with the present disclosure, such as digital pattern testing system 200 of FIG. 2 .
  • FIG. 8C shows an example of plot 816 generated by an oscilloscope-enhanced testing system of the present disclosure, such as digital pattern testing system 200 of FIG. 2 , when the testing system is zoomed in onto a falling transition 820.
  • FIGS. 8D and 8E show, respectively, exemplary plots 824, 828 generated by an oscilloscope-enhanced testing system of the present disclosure, such as digital pattern testing system 200 of FIG. 2 , when the testing system is zoomed in onto constant high and constant low bit values 832, 836, respectively.
  • an oscilloscope-enabled testing system of the present disclosure has great utility in identifying problem areas in a digital bit stream.
  • data-dependent jitter can easily be extracted since, now, the average arrival time of each transition in a bit stream is made available.
  • FIG. 9 shows an example plot 900 containing an overlay of two rising transitions 904, 908 that exhibit data-dependent jitter.
  • transitions 904, 908 occur at different times.
  • histograms on particular edges can be extracted to learn about jitter parameters that are non-data-dependent.
  • all transition edges can be accumulated together to generate eye masks or eye diagrams.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
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US83079706P 2006-07-14 2006-07-14
US11/776,865 US7813297B2 (en) 2006-07-14 2007-07-12 High-speed signal testing system having oscilloscope functionality
PCT/US2007/073458 WO2008008952A2 (en) 2006-07-14 2007-07-13 High-speed signal testing system having oscilloscope functionality

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EP2041584A2 EP2041584A2 (en) 2009-04-01
EP2041584A4 EP2041584A4 (en) 2011-04-20
EP2041584B1 true EP2041584B1 (en) 2012-09-05

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CA (1) CA2657154A1 (zh)
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Also Published As

Publication number Publication date
EP2041584A4 (en) 2011-04-20
CA2657154A1 (en) 2008-01-17
WO2008008952A3 (en) 2008-08-28
WO2008008952A2 (en) 2008-01-17
US7813297B2 (en) 2010-10-12
JP2009544040A (ja) 2009-12-10
EP2041584A2 (en) 2009-04-01
US20080013456A1 (en) 2008-01-17

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