Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
  • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
  • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
  • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
  • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
  • H01L23/4985—Flexible insulating substrates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
  • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
  • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
  • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
  • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
  • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
  • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
  • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
  • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
  • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
  • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
  • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
  • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
  • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
  • H01L2225/1047—Details of electrical connections between containers
  • H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the present invention relates generally to stackable IC packages, and more particularly to stackable IC packages with top and bottom interconnect.
• Miniaturization in IC packaging and "System in Package” are driving forces for packaging solutions with stackable packages.
• Stackable packages are volumetrically efficient, consisting of two or more IC packages that are interconnected in a single component, a "chip-stack", which is mountable to a printed circuit board using the "footprint" typically used for a single package device, such as for instance a packaged IC.
• the IC packages must, in addition to being formed into a stack, be electrically interconnected to each other in a desired manner.
• One of the current solutions is the "Match-X" approach from the Fraunhofer Institute in Germany.
• Match-X Concept consists of the stacking of substrates, with electronic components, on top of each other with solder balls as interconnect between the different substrates.
• Match-X is discussed in an article titled, "Stackable System-On-Packages with Integrated Components," in the IEEE Transactions on Advanced Packaging, (Vol. 27, No. 2, May 2004) of Becker et al.
• US Patent No. 6,426,240 issued to Isaak on July 30, 2002 discloses a stackable flex circuit chip package including a flexible substrate having a conductive pattern disposed thereon.
• the flexible substrate supports a first side of an integrated circuit chip, wraps around opposite parallel edges of the integrated circuit chip, and is attached to at least a portion of a second side of the integrated circuit chip that is opposite the first side.
• the conductive pattern defines portions along both the first side and the second side of the integrated circuit, which are electrically connectable to another stackable IC package.
• the present invention has been found useful in the drive for miniaturization in integrated circuit packages and system-in-package in finding packaging solutions with stackable packages.
• a method of assembling a stackable IC package with top and bottom interconnect comprises providing a die comprising first and second opposing longitudinal sides, first and second major surfaces, and a plurality of contacts arrayed on the first major surface.
• a flexible substrate comprising a conductive pattern and having first and second end portions is provided.
• the plurality of contacts of the die is electrically coupled to the conductive pattern.
• the flexible substrate is folded along at least a known line relative to at least one of the longitudinal sides of the die to dispose at least one of the first and second end portions in a planar arrangement opposing a plane of the second major surface of the die and on a side thereof opposite the first major surface of the die for electrical connection to a second stackable IC package.
• a support material between the flexible substrate and the die for supporting the conductive pattern relative to the die is provided. By removing at least a portion of the flexible substrate, the conductive pattern is exposed.
• a stackable IC package that comprises a die having a first major surface and a second major surface joined by opposed pairs of longitudinal and lateral sides.
• a conductive pattern electrically couples to the first major surface of the die.
• the conductive pattern extends past the longitudinal sides of the die and folds back in a direction generally toward the die.
• the conductive pattern thereby defines a first portion which is approximately co-planar with the first major surface of the die and a second portion which is approximately co-planar with the second major surface of the die; the first and second portions each being electrically connectable to another stackable IC package.
• a support material fixedly supports the conductive pattern relative to the die, and supports the first and second portions of the conductive pattern in spaced, generally parallel relationship one to the other.
• the IC package comprises a die having a first major surface and a second major surface joined by opposed pairs of longitudinal and lateral sides; a distance between the first major surface and the second major surface defines a thickness of the die.
• a conductive pattern electrically couples to the first major surface of the die and has a thickness that is small relative to the thickness of the die.
• the conductive pattern extends past the longitudinal sides of the die and folds back in a direction generally toward the die; the conductive pattern thereby defines a first portion which is approximately co-planar with the first major surface of the die and a second portion which is approximately co-planar with the second major surface of the die.
• the first and second portions each are electrically connectable to another stackable IC package.
• a support material fixedly supports the conductive pattern relative to the die, for electrically isolating the conductive pattern and the surface of the die where the support material is disposed therebetween, and for supporting the first and second portions of the conductive pattern in a spaced, generally parallel relationship one to the other.
• FIG. 1 is a simplified flow diagram of a method of assembling a stackable IC package with top and bottom interconnect, according to an embodiment of the instant invention
• FIG. 2A is a top perspective view of a temporary substrate including a conductive pattern, for use in assembling a stackable IC package with top and bottom interconnect;
• FIG. 2B is a top perspective view of a die attached to the temporary substrate of FIG. 2A;
• FIG. 2C is a top perspective view showing the folded temporary substrate and die
• FIG. 2D is a top perspective view showing the folded temporary substrate filled with an epoxy support material
• FIG. 2E is a top perspective view showing a stackable IC package with top and bottom interconnect, subsequent to removal of the temporary substrate;
• FIG. 3 is a cross-sectional view of a stackable IC package with top and bottom interconnect, according to an embodiment of the instant invention.
• FIG. 4 is a cross-sectional view of a chip-stack assembled using stackable IC packages according to an embodiment of the instant invention.
• a die is provided at 10, the die having first and second opposing longitudinal sides, first and second opposing lateral sides, first and second major surfaces, and a plurality of contacts arrayed on the first major surface.
• a flexible substrate having a conductive pattern disposed along one side thereof, is provided at 15.
• the flexible substrate includes a sacrificial layer; in an example embodiment, the flexible substrate is an Al or Cu substrate.
• the die is mounted onto the temporary substrate and is electrically coupled to the conductive pattern via the plurality of contacts. Electrical coupling is achieved using techniques that are well known in the art, such as for instance.
• the interconnect can be made by wire bonding or ultrasonic flip-chip bonding.
• glue or glue film is also possible.
• the flexible substrate is folded along an imaginary line adjacent to each of the longitudinal sides of the die, to dispose the first and second end portions opposed to each other in a co-planar arrangement above the second major surface of the die for electrical connection to a second stackable IC package.
• a support material is provided between the flexible substrate and the die at 30.
• the support material is preferably an epoxy, which is cured and hardened for supporting the conductive pattern relative to the die.
• the flexible substrate is removed at 35 so as to expose the conductive pattern.
• the flexible substrate is folded along an imaginary line parallel to each of the longitudinal sides of the die, so as to facilitate manufacturing of the stackable IC packages.
• the conductive pattern is disposed along the one side of the flexible substrate so as to support folding of the flexible substrate along imaginary lines that are other than parallel to each of the longitudinal sides of the die.
• folding is accomplished in an automated manner using, for instance, a moulding machine as is known in the art.
• trim and form tools and the like may be used to shape the leads of semiconductor packages, such as DIL.
• the temporary substrate is folded in one direction only. Specifically, the temporary substrate is folded along an imaginary line adjacent to each of the longitudinal sides of the die. In another example embodiment, the temporary substrate is folded in two directions.
• the temporary substrate optionally is folded along an imaginary line adjacent and parallel to each of the longitudinal sides of the die or along an imaginary line adjacent and parallel to each of the lateral sides of the die.
• FIG. 2A shown is a top perspective view of a temporary substrate 200, including a conductive pattern 202, for use in assembling a stackable IC package with top and bottom interconnect.
• the temporary substrate 200 is fabricated using materials that support folding or bending of the temporary substrate without breakage.
• the flexible substrate 200 is an Al-Cu substrate.
• Opposite end portions of the temporary substrate 200 are identified in FIG. 2a using the reference numeral 204.
• the conductive pattern 202 is formed in a known manner. The thick ranges from about 3 ⁇ m to about 30 ⁇ m.
• the conductive pattern may be made by electroplating and can consist of a stack-like structure of l ⁇ m gold followed by 2 ⁇ m nickel and lO ⁇ m copper.
• FIG. 2B shown is a top perspective view of a die 206 that is attached to the temporary substrate 200 of FIG. 2 A.
• the die 206 includes first and second opposing longitudinal sides 208, first and second opposing lateral sides 210, a not illustrated first major surface and a second major surface 212, and a plurality of not illustrated contacts arrayed on the first major surface.
• the first major surface is the "lower surface” of the die 206 and the second major surface 212 is the "upper surface” of the die 206.
• the die 206 is electrically coupled to the conductive pattern 202 via the plurality of contacts, in a known manner.
• FIG. 2C shown is a top perspective view showing the folded temporary substrate 200 and die 206.
• the flexible substrate 200 is folded along an imaginary line 214 that is parallel to each of the opposite end portions 204 of the die 206, to dispose the opposite end portions 204 opposed to each other in a co-planar arrangement above the second major surface 212 of the die 206 in FIG. 2C.
• the opposite end portions 204 are disposed for electrical connection to a second stackable IC package.
• the flexible substrate 200 is folded along a not illustrated imaginary line that is not parallel to each of the opposite end portions 204 of the die 206. Referring now to FIG.
• FIG. 2D shown is a top perspective view showing the folded temporary substrate 200, with the opposite end portions 204 opposed to each other in a co- planar arrangement, filled with an epoxy support material 216.
• the epoxy support material 216 fills the voids between conductive tracks of the conductive pattern 202, and then is cured in a known manner.
• FIG. 2E shown is a top perspective view showing a stackable IC package 218 with top interconnects 220 and not illustrated bottom interconnects, subsequent to removal of the flexible substrate.
• the epoxy support material 216 supports the conductive pattern 202, including the top interconnects 220 and the bottom interconnects, relative to the die after the flexible substrate has been removed.
• the flexible substrate 200 is removed prior to stacking the stackable IC packages into a stack. Since the flexible substrate 200 is not required to carry the conductive pattern, the stackable IC package 218 as shown, in FIG. 2e supports a minimum stack size.
• FIG. 3 shown is a cross-sectional view of a stackable IC package with top and bottom interconnect, according to an embodiment of the instant invention.
• the epoxy support material 216 supports the conductive pattern 202, including the top interconnects 220 and the bottom interconnects 222, relative to the die 206.
• the epoxy support material 216 supports the top interconnects 220 adjacent to the longitudinal sides 208 of the die in a co-planar arrangement above the second major surface 212 of the die 206.
• FIG. 4 shown is a cross-sectional view of a chip-stack assembled using stackable IC packages according to an embodiment of the instant invention.
• the chip stack includes two or more than three stackable IC packages according to an embodiment of the instant invention.
• the top interconnects 220 of a first stackable IC package are electrically coupled to the bottom interconnects of an adjacent stackable IC package. Electrical coupling is achieved using any suitable procedure that is known in the art for this purpose. Some non- limiting examples include gluing, soldering or use of adhesive strips.
• each stackable IC package in the chip stack shown at FIG. 4 has the same function.
• each stackable IC package in the chip stack may have a different electrical function.
• the stackable IC package according to an embodiment of the instant invention, is used as a single package with on top "odd" components such as for instance a loudspeaker, coil, or microphone.
• a plurality of stackable IC package is assembled into a stack, wherein the stack acts as for instance, a system-in-package (SiP).
• SiP system-in-package
• wire bonding is possible since only the lateral ends of the flexible substrate are bent and folded.
• Other examples may include a chip with a microprocessor upon which through application of the present invention may have memory chips stacked thereon.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Wire Bonding (AREA)
• Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

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• 2006
  • 2006-06-16 EP EP06765775A patent/EP2036127A1/en not_active Withdrawn
  • 2006-06-16 JP JP2009514920A patent/JP2009540592A/ja active Pending
  • 2006-06-16 CN CN200680055010.9A patent/CN101467253A/zh active Pending
  • 2006-06-16 WO PCT/IB2006/051946 patent/WO2007148154A1/en active Application Filing

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