Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
  • G11C11/5642—Sensing or reading circuits; Data output circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/10—Programming or data input circuits
  • G11C16/12—Programming voltage switching circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/26—Sensing or reading circuits; Data output circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/30—Power supply circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
  • G11C2211/564—Miscellaneous aspects
  • G11C2211/565—Multilevel memory comprising elements in triple well structure
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising

Definitions

• the peripheral circuitry supplies the reference voltages to the bit line comparators sequentially.
• the reference values can all be available concurrently to a multiplexing circuit that supplies the different value, or the line supplying the reference values to the comparator can itself receive the various reference values in a time multiplexed manner.
• Figure 6 provides Table 1 of example operating voltages of the NAND memory cell array of Figures 2-5;
• select gate lines are electrically shorted together using one contact for each select gate, as in the STI embodiment the poly-1 layer is etched into isolated strips during the STI definition.
• poly 1 strips are also etched, leaving the polyl gates residing above select gate channels as isolated conductors.
• poly-2 layer will form a conducting line, connecting the individual poly-1 select gates to each other in order to form the select gate lines, which extend in a parallel direction to word lines.
• Figure 8 illustrates threshold voltage distributions for the memory cell array 1 when each floating gate storage element stores two bits of data, namely four data states, in each memory cell (M).
• the curve 33 represents a distribution of the threshold levels V T of the cells within the array 1 that are in the erased state (E data state), being negative threshold voltage levels.
• Threshold voltage distributions 34 and 35 of memory cells storing A and B user data, respectively, are shown to be between V V A and V V B and between V V B and Vyc- A curve 36 shows the distribution of cells that have been programmed to the C data state, being the highest threshold voltage level set more than 2V and less than 4.5V of the read pass voltage.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
• Read Only Memory (AREA)

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• 2006
  • 2006-12-21 KR KR1020087015402A patent/KR101357068B1/ko active IP Right Grant
  • 2006-12-21 EP EP06848820A patent/EP1966800A2/de not_active Withdrawn
  • 2006-12-21 JP JP2008548823A patent/JP4568365B2/ja not_active Expired - Fee Related
  • 2006-12-21 WO PCT/US2006/062513 patent/WO2007076451A2/en active Application Filing
  • 2006-12-28 TW TW095149528A patent/TWI323464B/zh not_active IP Right Cessation

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