Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
  • G11C11/5642—Sensing or reading circuits; Data output circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/10—Programming or data input circuits
  • G11C16/12—Programming voltage switching circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/26—Sensing or reading circuits; Data output circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/30—Power supply circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
  • G11C2211/564—Miscellaneous aspects
  • G11C2211/565—Multilevel memory comprising elements in triple well structure
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising

Definitions

• This invention relates generally to non- volatile memories and their operation, and, more specifically, to techniques for reading such memories.
• each floating gate storage element of a flash EEPROM array It is common in current commercial products for each floating gate storage element of a flash EEPROM array to store a single bit of data by operating in a binary mode, where two ranges of threshold levels of the floating gate transistors are defined as storage levels.
• the threshold levels of a floating gate transistor correspond to ranges of charge levels stored on their floating gates.
• the trend is to further increase the density of data storage of such memory arrays by storing more than one bit of data in each floating gate transistor. This is accomplished by defining more than two threshold levels as storage states for each floating gate transistor, four such states (2 bits of data per floating gate storage element) now being included in commercial products. More storage states, such as 8 or even 16 states per storage element, are contemplated.
• Each floating gate memory transistor has a certain total range (window) of threshold voltages in which it may practically be operated, and that range is divided into one range for each of the number of states plus margins between the states to allow for them to be clearly differentiated from one another.
• patent no. 5,930,167 describes methods of selectively programming portions of a multi-state memory as cache memory, in only two states or with a reduced margin, in order to shorten the time necessary to initially program the data. This data is later read and re -programmed into the memory in more than two states, or with an increased margin.
• a NOR array of one design has its memory cells connected between adjacent bit (column) lines and control gates connected to word (row) lines.
• the individual cells contain either one floating gate transistor, with or without a select transistor formed in series with it, or two floating gate transistors separated by a single select transistor. Examples of such arrays and their use in storage systems are given in the following U.S. patents and pending applications of SanDisk Corporation that are incorporated herein in their entirety by this reference: Patent Nos. 5,095,344, 5,172,338, 5,602,987, 5,663,901, 5,430,859, 5,657,332, 5,712,180, 5,890,192, and 6,151,248, and Serial Nos. 09/505,555, filed February 17, 2000, and 09/667,344, filed September 22, 2000.
• a NAND array of one design has a number of memory cells, such as 8, 16 or even 32, connected in series along each string formed between a bit line and a reference potential line through select transistors at either end.
• Word lines are connected with control gates of cells and are formed over different series strings. Relevant examples of such arrays and their operation are given in the following U.S. patents that are incorporated herein in their entirety by this reference: 5,570,315, 5,774,397 and 6,046,935.
• two bits of data often from different logical pages of incoming data are programmed into one of four states of the individual cells in two steps, first programming a cell into one state according to one bit of data and then, if the data makes it necessary, re-programming that cell into another one of its states according to the second bit of incoming data.
• performance can also be improved by speeding up the sensing process. Shortening sensing times will improve performance both during read and verify operations; and if the memory can speed up verify, this will improve write speed. This is particularly true for multi-state memories, where a verify step is needed between any two consecutive pulses, and multi-state memories require several sensing steps in each verify operation. The performance of non-volatile memory systems could be improved if these shortcomings could be reduced or eliminated.
• the present invention presents a scheme for sensing memory cells that is particularly useful for improving performance in multi-level nonvolatile memory systems. This is achieved by setting an initial state in selected memory cells by discharging their channels to ground, placing a voltage level on the traditional source (such as the common electrode that connects the same end of the NAND strings in one block together) and the control gate, and allowing the cell bit line to charge up for some time as a result of conduction of current through the cell during the signal integration period. The bit line of the memory cell will then charge up until the bit line voltage becomes sufficiently high enough to shut off any further cell conduction.
• the traditional source such as the common electrode that connects the same end of the NAND strings in one block together
• an exemplary embodiment uses this technique for sensing in both the verify phase of write operations and for read operations.
• a plurality of cells along the same word line are sensed concurrently by placing a constant, data independent voltage on the word line and constant, data independent common voltage level on the source side of these cells.
• the source side is now playing the role of the drain in the sense that its voltage is higher than the bit line side.
• the bit lines of cells, having previously been discharged, will then cause a voltage on their respective bit lines indicative of their individual data content.
• the present invention allows for a single pass of verify operation to verify the state of all cells being programmed, regardless of the cells target state. As the level to which the corresponding bit line will rise depends, due to the body effect, upon the state of the cell. This level can then be compared against the reference value corresponding to the respective target values. This improves performance over prior art techniques requiring multiple charge-discharge, and signal integration cycles following each program pulse, one cycle for each target state requiring a verify operation.
• read performance is improved as all data levels can be determined based upon the single discharge-charge cycle. As the level on a given cells bit line approaches an asymptotic value determined by the data content, once these levels are reached the level on the bit line can be compared to a set of reference levels, the comparison phase performed either sequentially or concurrently.
• the peripheral circuitry supplies the reference voltages to the bit line comparators sequentially.
• the reference values can all be available concurrently to a multiplexing circuit that supplies the different value, or the line supplying the reference values to the comparator can itself receive the various reference values in a time multiplexed manner.
• Another aspect of the present invention is sensing the state of the multi- state memory cells by performing multiple sensing sub-operations, each with a different control gate voltage, but with multiple states being sensed in each operation by charging the previously discharged cells up through their source.
• the sensing operation is sped up, as multiple states are read in each sensing sub-operation, while the use of multiple word line voltages provides sufficient dynamic range to resolve all of the data states.
• a specific embodiment of these aspects is based upon a flash memory with a NAND architecture.
• the cells along a selected word line are connected along bit lines to a common source line.
• Either an all bit line architecture or an architecture where the bit lines are divided into sets that are sensed alternately can be used.
• Figure 1 is a block diagram of a non- volatile memory system in which the various aspects for implementation of the present invention are described;
• Figure 2 illustrates an existing circuit and organization of the memory array of Figure 1 when the memory cell array is of a NAND type
• Figure 3 shows a cross-sectional view, along a column, of a NAND type memory array formed on a semiconductor substrate
• Figure 4 is a cross-sectional view of the memory array of Figure 3, taken at section 4-4 thereof;
• Figure 5 is a cross-sectional view of the memory array of Figure 3, taken at section 5-5 thereof;
• Figure 6 provides Table 1 of example operating voltages of the NAND memory cell array of Figures 2-5;
• Figure 7 illustrates another feature of the NAND memory cell array of Figures 2-5;
• Figure 8 shows an example of an existing distribution of threshold voltages of the NAND memory cell array of Figures 2-5 when operated in four states;
• Figures 9A and 9B show an example programming voltage signal that may be used in the memory cell array of Figures 2-5;
• Figure 10 illustrates a dynamic sensing technique based upon discharging a selected memory element.
• Figure 11 illustrates a sensing technique according to an exemplary embodiment of the present invention.
• Figure 12 shows a portion of a memory array and peripheral circuitry according to the present invention.
• Figures 13A-C show variations on peripheral circuitry of Figure 12.
• Figure 14 illustrates a hybrid sensing technique according to an exemplary embodiment of the present invention.
• FIG. 1 is a block diagram of a flash memory system.
• Memory cell array 1 including a plurality of memory cells M arranged in a matrix is controlled by a column control circuit 2, a row control circuit 3, a c-source control circuit 4 and a c-p-well control circuit 5.
• the column control circuit 2 is connected to bit lines (BL) of the memory cell array 1 for reading data stored in the memory cells (M), for determining a state of the memory cells (M) during a program operation, and for controlling potential levels of the bit lines (BL) to promote the programming or to inhibit the programming.
• BL bit lines
• the row control circuit 3 is connected to word lines (WL) to select one of the word lines (WL), to apply read voltages, to apply program voltages combined with the bit line potential levels controlled by the column control circuit 2, and to apply an erase voltage coupled with a voltage of a p-type region (labeled as "c-p-well” 11 in Figure 3) on which the memory cells (M) are formed.
• the c-source control circuit 4 controls a common source line (labeled as "c- source” in Figure 2) connected to the memory cells (M).
• the c-p-well control circuit 5 controls the c-p-well voltage.
• the data stored in the memory cells (M) are read out by the column control circuit 2 and are output to external I/O lines via an I/O line and a data input/output buffer 6.
• Program data to be stored in the memory cells are input to the data input/output buffer 6 via the external I/O lines, and transferred to the column control circuit 2.
• the external I/O lines are connected to a controller 20.
• Command data for controlling the flash memory device are input to a command interface) connected to external control lines that are connected with the controller 20.
• the command data informs the flash memory of what operation is requested.
• the input command is transferred to a state machine 8 that controls the column control circuit 2, the row control circuit 3, the c-source control circuit 4, the c- p-well control circuit 5 and the data input/output buffer 6.
• the state machine 8 can output a status data of the flash memory such as READY/BUSY or PASS/FAIL.
• the controller 20 is connected or connectable with a host system such as a personal computer, a digital camera, or a personal digital assistant. It is the host that initiates commands, such as to store or read data to or from the memory array 1 , and provides or receives such data, respectively.
• the controller converts such commands into command signals that can be interpreted and executed by the command circuits 7.
• the controller also typically contains buffer memory for the user data being written to or read from the memory array.
• a typical memory system includes one integrated circuit chip 21 that includes the controller 20, and one or more integrated circuit chips 22 that each contain a memory array and associated control, input/output and state machine circuits. The trend, of course, is to integrate the memory array and controller circuits of a system together on one or more integrated circuit chips.
• the memory system may be embedded as part of the host system, or may be included in a memory card that is removably insertable into a mating socket of host systems.
• a memory card may include the entire memory system, or the controller and memory array, with associated peripheral circuits, may be provided in separate cards.
• a flash EEPROM of a NAND type is described as an example.
• the memory cells (M) are partitioned into 1,024 blocks, in a specific example.
• the data stored in each block are simultaneously erased.
• the block is thus the minimum unit of a number of cells that are simultaneously erasable.
• In each block in this example, there are 8,512 columns that are divided into even columns and odd columns.
• the bit lines are also divided into even bit lines (BLe) and odd bit lines (BLo).
• WLO to WL3 word lines
• One terminal of the NAND cell unit is connected to corresponding bit line (BL) via a first select transistor whose gate electrode is coupled to a first select gate line (SGD), and another terminal is connected to the c-source via a second select transistor which gate electrode is coupled to a second select gate line (SGS).
• BL bit line
• SGD first select gate line
• SGS second select gate line
• four floating gate transistors are shown to be included in each cell unit for simplicity, a higher number of transistors, such as 8, 16, 32, or even 64, are used.
• each NAND string contains 4 cells and there are two bit lines per sense amp, one block can store at least eight pages.
• each memory cell (M) stores two bits of data, namely a multi-level cell, one block stores 16 pages.
• Figure 3 shows a cross sectional view of a NAND cell unit of the type shown schematically in Figure 2, in the direction of the bit line (BL).
• a p-type region c-p-well 11 is formed, the c-p- well being enclosed by an n-type region 10 to electrically isolate the c-p-well from the p-type substrate.
• the n-type region 10 is connected to a c-p-well line made of a first metal MO via a conductor filling the first contact hole (CB) and an n-type diffusion layer 12.
• the p-type region c-p-well 11 is also connected to the c-p-well line via the first contact (CB) and a p-type diffusion layer 13.
• the c-p-well line is connected to the c-p-well control circuit 5 ( Figure 1).
• Each memory cell has a floating gate (FG) that stores an amount of charge corresponding to the data being stored in the cell, the word line (WL) forming the gate electrode, and drain and source electrodes made of the n-type diffusion layer 12.
• the floating gate (FG) is formed on the surface of the c-p-well via a tunnel oxide film (14).
• the word line (WL) is stacked on the floating gate (FG) via an insulator film (15).
• the source electrode is connected to the common source line (c-source) made of the first metal (MO) via the second select transistor (S) and the first contact hole (CB).
• the common source line is connected to the c-source control circuit (4).
• the drain electrode is connected to the bit line (BL) made of a second metal (Ml) via the first select transistor (S), the first contact hole (CB), an intermediate wiring plate of the first metal (MO) and a second contact hole (Vl).
• the bit line is connected to the column control circuit (2).
• Figures 4 and 5 show cross sectional views of a memory cell (section 4-4 of Figure 3) and a select transistor (section 5-5 of Figure 3), respectively, in the direction of the word line (WL2).
• Each column is isolated from the neighbor columns by a trench formed in the substrate and filled with isolation material, known as shallow trench isolation (STI).
• the floating gates (FG) are isolated from each other by the STI and insulator film 15 and word line (WL).
• the space between the floating gates (FG) may be of the order of 0.1 um, and the capacitive coupling between the floating gates may be significant. Since the gate electrode (SG) of the select transistor is formed in the same formation process steps as the floating gate (FG) and word line (WL), it shows a stacked gate structure.
• select gate lines are electrically shorted together using one contact for each select gate, as in the STI embodiment the poly-1 layer is etched into isolated strips during the STI definition.
• poly 1 strips are also etched, leaving the polyl gates residing above select gate channels as isolated conductors.
• poly-2 layer will form a conducting line, connecting the individual poly-1 select gates to each other in order to form the select gate lines, which extend in a parallel direction to word lines.
• Table I of Figure 6 summarizes voltages applied to operate the memory cell array 1, in a specific example, each memory cell's floating gate storing two bits, having one of the states "11", “10", “01”, “00”.
• This table shows the case where the word line "WL2" and the bit lines of "BLe” are selected for reading and programming.
• By raising the c-p-well to an erase voltage of 20V and grounding the word lines (WL) of a selected block the data of the selected block is erased.
• bit lines (BL), select lines (SG) and c-source are put in a floating state, these are also raised to an intermediate voltage of, for example, 8V due to a capacitive coupling with the c-p-well. Therefore, a strong electric field is applied to only the tunnel oxide films 14 ( Figures 4 and 5) of the selected memory cells (M), and the data of the selected memory cells are erased as a tunnel current flows across the tunnel oxide film 14.
• the erased cell is, in this example, one of the four possible states, namely "11".
• the selected word line WL2 is connected to a program pulse Vpgm and the selected bit lines BLe are grounded.
• the corresponding bit lines BLe are connected to a positive voltage Vdd, for example 3V, at the onset of programming, in order to isolate their string channels and have them float up to an inhibit condition as mentioned earlier. This program inhibit is also done on all of the unselected bit lines BLo.
• the unselected word lines WLO, WLl and WL3 are connected to 10V, the first select gate (SGD) is connected to Vdd, and the second select gate (SGS) is grounded.
• a channel potential of the memory cell (M) that is being programmed is set at OV.
• the channel potential of a cell that is being inhibited is raised to around 8 V as a result of the channel potential being pulled up by the capacitive coupling with the word lines (WL).
• the select gates (SGD and SGS) and the unselected word lines (WLO, WLl, and WL3) are raised to a read pass voltage of 4.5V to insure that current between the bit line and common source line can pass through them.
• the selected word line (WL2) is connected to a voltage, a level of which is specified for each read and verify operation in order to determine whether a threshold voltage of the concerned memory cell has reached such level. For example, in a READ 10 operation (state A), the selected word line WL2 is grounded, so that it is detected whether the threshold voltage is higher than OV. In this read case, it can be said that a read level is OV. In a VERIFYOl operation (state C), the selected word line WL2 is connected to 2.4V, so that it is verified that whether the threshold voltage has reached 2.4V. In this verify case, it can be said that a verify level is 2.4V.
• the selected bit lines (BLe) are pre-charged to a high level, for example 0.7V. If the threshold voltage is higher than the read or verify level, the potential level of the concerned bit line (BLe) maintains the high level, because of the non- conductive memory cell (M). On the other hand, if the threshold voltage is lower than the read or verify level, the potential level of the concerned bit line (BLe) decreases to a low level, for example less than 0.5V, because of the conductive memory cell (M). Further details of the read and verify operations are explained below.
• FIG. 7 shows a part of the column control circuit 2 of Figure 1.
• Each pair of bit lines (BLe and BLo) is coupled to a data storage portion 16 which includes two data storage (DSl and DS2) registers, each being capable of storing one bit of data.
• the data storage portion 16 senses the potential level of the selected bit line (BL) during a read or verify operation and then stores the data in a binary manner, and controls the bit line voltage in the program operation.
• the data storage portion 16 is selectively connected to the selected bit line (BL) by selecting one of signals of "EVENBL” and "ODDBL".
• the data storage portion 16 is also coupled to the I/O line to output the read data and to store the program data.
• the I/O line is connected to the data input/output buffer 6, as described above with respect to Figure 1.
• Figure 8 illustrates threshold voltage distributions for the memory cell array 1 when each floating gate storage element stores two bits of data, namely four data states, in each memory cell (M).
• the curve 33 represents a distribution of the threshold levels V T of the cells within the array 1 that are in the erased state (E data state), being negative threshold voltage levels.
• Threshold voltage distributions 34 and 35 of memory cells storing A and B user data, respectively, are shown to be between V V A and V V B and between V V B and Vyc- A curve 36 shows the distribution of cells that have been programmed to the C data state, being the highest threshold voltage level set more than 2V and less than 4.5V of the read pass voltage.
• each of the two bits stored in a single memory cell (M) is from a different logical page. That is, each bit of the two bits stored in each memory cell carries a different logical page address from the other.
• state E can be represented as the "11” state, state A as the “10” state, state B as the "00” state, and state C as the "01" state, where the first binary digit represents the value stored in the upper page and the second binary digit represents the value stored in the lower page.
• state E can be represented as the "11" state
• state A as the "10” state
• state B as the "00” state
• state C as the "01” state
• the first binary digit represents the value stored in the upper page
• the second binary digit represents the value stored in the lower page.
• the threshold distribution narrowed the threshold distribution narrowed
• the distribution width remains tighter without a conspicuous degradation in the programming speed.
• FIG. 9 A shows an existing programming pulse technique.
• the programming voltage Vpgm is divided into many pulses, and increased 0.2V pulse by pulse.
• the starting level of Vpgm is 12V, in this particular example.
• the verify (read) operations are carried out. That is, the programmed level of each cell being programmed in parallel is read between each programming pulse to determine whether it is equal to or greater than the verify level to which it is being programmed. This is shown in Figure 9B, which is a more detailed version of Figure 9A, for a memory storing four bits per cell. If it is determined that the threshold voltage of a given memory cell has exceeded the verify level, programming is stopped or inhibited for that bit by raising the voltage of the bit line to which the series cell unit of the given cell is connected from OV to Vdd. Programming of others of the cells being programmed in parallel on the same page continues until they in turn reach their verify levels. When the threshold voltage moves from below the verify level to above it during the cell's last programming pulse, the shift of the threshold voltage is equal to the Vpgm step size of 0.2V. Therefore, the threshold voltages are controlled within a 0.2V-width.
• the cell's threshold level is set according to the bit being stored in the cell from the upper logical page. If a "1", no programming occurs since the cell is in one of the states 33 or 34, depending upon the programming of the lower page bit, both of which carry an upper page bit of "1". If the upper page bit is a "0", however, the cell is programmed a second time. If the first pass resulted in the cell remaining in the erased or E state 33, the cell is programmed from that state to the highest threshold state 36 (state C), as shown by the upper arrow Figure 8 and Vvc is used as the verify condition to inhibit further programming.
• the cell is further programmed in the second pass from that state to the state 35 (state B) using V VB as the verify condition, as shown by the lower arrow of Figure 8.
• the result of the second pass is to program the cell into the state designated to store a "0" from the upper page without changing the logical value written during the first pass programming.
• the threshold distribution of a cell can remain in state E or A, or shift into either state B or C. Since there are two different target threshold states occurring in different cells simultaneously during the same programming cycle, two different verify levels, V VB and Vvc, must be checked after each programming pulse. In some systems Vvc may be checked only during the later voltage pulses in order to speed up the total program cycle.
• the voltages V RA , V RB and V RC are used to read data from the memory cell array. These are the threshold voltages with which the threshold voltage state of each cell being read is compared. This is accomplished by comparing a current or voltage measured from the cell with reference currents or voltages, respectively. Margins exist between these read voltages and the programmed threshold voltage distributions, thus allowing some spreading of the distributions from disturbs and the like, as discussed above, so long as the distributions do not overlap any of the read voltages V RA , V RB and V RC . AS the number of storage state distributions increases, however, this margin is reduced and the programming is then preferably carried out with more precision in order to prevent such spreading.
• U.S. patent 6,046,935 describes a programming method in which selected cells are programmed from state E to state B during a first programming cycle. During a second programming cycle cells are programmed from state E to state A and from state B to state C.
• U.S. patent 6,657,891 elaborates on this method by teaching that the initial distribution of state B may be allowed to extend to a lower threshold limit and even overlap final state A at the end of the first programming cycle, being tightened to its distribution only during the second programming cycle.
• the binary coding adopted to represent states E, A, B and C may be chosen differently that that shown in Figure 8. Both patents 6,046,935 and 6,657,891 are hereby incorporated by reference.
• each program pulse is normally followed by as many as (N-I) verify operations each of which applies a different value of control gate voltage to the selected word line, where N is the number of states in an MLC embodiment.
• N is the number of states in an MLC embodiment.
• every program pulse is typically followed by 3 verify read operations.
• Each of these verify operations is typically at a successively higher read voltage applied to the selected word line.
• a non- volatile memory cell In sensing a non- volatile memory cell, whether as part of a read operation or as part of the verify phase of a program operation, there will typically be several phases. These include applying voltages to the cell so that it is biased appropriately with the correct initial conditions for its data content to be sensed or measured, followed by an integration period that measures a parameter related to the state of the cell.
• the parameter In an EEPROM cell, the parameter is usually a voltage or the source-drain current, but can also be a time or frequency that is governed by the state of the cell.
• An example of one embodiment for the sense voltages of this measurement process is shown schematically in Figure 10.
• Figure 10 shows the voltage level on a bit-line of a memory array, for example one of the bit lines shown in Figure 2.
• the first phase sets the gate voltages on the cells.
• the bit- lines of the cells to be read are charged up to a predetermined level.
• the voltage level on the bit-line is measured relative to a reference level V ref . If the voltage is at or above V ref , as in line 501, the cell is considered in an off state.
• V re f the reference voltage used to the sense the state of the cell: if t is taken too short, 501 and 503 will not have sufficiently seperated, while if t is taken too long, 503 and 501 will have bottomed out at ground; similarly if V re f is taken too high, even an off cell may be mistakenly read as on due to low level leakage currents, while if V ref is taken too low, even an on cell may be mistakenly read as off since on cells can carry a finite amount of current.
• V CG applied control gate voltage
• a verify operation for state 3 can be skipped for as long as no cell has yet verified for having reached state 2.
• Such a "smart verify” technique is described in U.S. patent-publication 2004-0109362-A1, published June 10, 2004 and which is hereby incorporated by reference.
• a principle aspect of the present invention replaces the (N-I) (or somewhat fewer) verify operations per program pulse with only a single verify operation.
• This is achieved by applying a single, fixed, high valued read voltage (e.g. 2.4V which is the typical word line voltage for discriminating between the highest programmed threshold state and the other lower programmed states) to the selected word line, and simultaneously verifying each cell against its own target state by taking advantage of the body effect in the following manner:
• a voltage of, for example, 2V is applied to the traditional source line of the NAND array ( Figure 2), while SGS transistors are turned on, in order to transfer this voltage to the traditional source sides of the NAND strings in the selected block.
• the traditional drains i.e.
• bit lines are discharged to ground before the beginning of the signal integration period by grounding the bit lines and applying a sufficiently high voltage to SGDs in order to guarantee that all bit lines are pre-discharged.
• SGDs grounding the bit lines and applying a sufficiently high voltage to SGDs in order to guarantee that all bit lines are pre-discharged.
• those cells which are initially conductive will experience a rise in their respective bit line voltages until each cell reaches its threshold voltage and shuts off the further charging of the its respective bit line, after which point the bit line voltage will not substantially rise any further.
• the threshold voltage of each memory cell will be a function of the source voltage through the body effect. This is illustrated schematically in Figure 11.
• Figure 11 shows voltage levels for the bit line (Figure 11C) in response to the sensing operation, along with the voltage V WL supplied by the word line to the control gates of the cells in the selected row ( Figure 1 IA), the voltage supplied to the common source line of the select cells ( Figure HB), and the reference levels ( Figure HD) for the case where three of these are supplied sequentially to reference voltage input side of the sense amplifiers through a single reference voltage carrying bus line.
• Figures 1 IA-C therefore respectively represent the voltage at the control gate (V WL ), source (V S0U rce), and drain (VBL) of selected storage elements.
• SGD drain side select gate
• SGS source side select gate
• V SGS , V SG D, and VREAD respectively correspond the source side select gate voltage, the drain side select gate voltage, and the voltage applied to the non- selected word lines in the block during the read operation.
• V SGS and V SGD can be at 5V just to guarantee that these transistors are on, despite the body effect
• V WL can be 3.5V (or whatever the highest V TH comparison voltage is)
• VREAD is higher than V W L- VREAD is also taken higher than the usual 5V (e.g.
• Figure 11 begins in an initial state, phase 1, corresponding to what ever process had previously been going on.
• V BL is shown to have some initial value and all of the others are shown low, but this is just an arbitrary starting point.
• the drain side select transistor (SGD) is turned on to allow the charge to flow out and held on through out the process, allowing the bit line to charge back up in phases 3 and 4.
• the word line voltage V WL is raised, allowing the bit lines to charge up in phase 3.
• Figure 12 shows a portion of two blocks of an array in an all bit line (ABL) arrangement.
• block i is flipped with respect to block i+1 in the sense that the common source line for block i, c-source_i 111, is at the top of bock i above the select gate line SGS i, which is in turn above the memory cells, whereas block i+1 is arranged with it common source line, c-source_i+l, at the bottom.
• ABL all bit line
• the sense amplifier circuits are all shown to be on the upper side of the array for simplicity of representation. In actually implementations, the circuitry for alternate bit lines may be located on the bottom side of the array, such as is described in U.S. patent application number 11/078,173 filed March 11, 2005, and which is hereby incorporated by reference.
• All of the NAND strings in a selected read page will have the same V S0U rce and same V WL applied, as they also will for the rest of voltages associated with the selected NAND block (to the non-selected word lines and the select gates): what differs is the charge stored on the floating gates of cells of the selected row, which will determine how fast and how far the voltage level on the corresponding bit line will rise, corresponding to the differing lines of Figure 11C. For example, on the cell 113 on bit line 7, this will control the level on bit line BL/ 107, which is then communicated along global bit line GBLy- 105 to the corresponding comparator 101/. The comparison values are supplied to the comparators along line (or lines) 103.
• line 103 can either be a single line with the different comparison values (V comp ) supplied sequentially or separate lines for the various comparison values that are then multiplexed into the comparators.
• V comp comparison values
• the level of each of the global bit lines can be supplied to multiple comparators for comparison to the different V comp values in parallel.
• each sense amplifier would include (N-I) comparators.
• (N-I) bus lines will be required to deliver the (N-I) reference voltages required for concurrently sensing and distinguishing N states from one another.
• the sense amplifiers can be designed to be much simpler and occupy smaller portions of the die. It should be noted that in the typical ABL architecture, every global bit line has a dedicated sense amplifier, and in the more conventional odd/even sensing, one sense amplifier is dedicated to every global bit line pair.
• Another advantage of performing the comparison phase in a sequential manner is that a single bus line running in the same direction as the word lines can be used for delivering the reference voltages in a time multiplexed manner to all sense amplifiers residing at the end of each memory plane. This also saves die area. However there will be some performance and power/energy penalties associated with charging the reference bus line voltage (N-I) times. It is also possible to design the memory to time multiplex the compare operations, but to do so using several reference voltages bus lines.
• an 8 state memory could have 4 bus lines, and the sense amps can be designed to each concurrently sense 2 states using two of the reference bus lines while the other 2 reference bus lines are charging to the next pair of reference voltages, reducing the performance impact of the reference bus lines' charging time. It is important to note that the bit line charging or discharging phase is a relatively slow process, taking on the order of several microseconds.
• I C dV/dt
• I the current which can be no bigger than the memory cell transistor's saturation current (for an on cell, a typically value for I is on the order of a micro-amperes or less)
• C is typically the bit line capacitance, which is usually dominated by the global bit line capacitance
• dV the minimum change in sensing node voltage required for a reliable, and noise-free operation, and it is in the range [5OmV, 50OmV].
• the VREAD voltage applied to the non- selected word lines of a NAND block will have to be overdriven by a higher amount than that needed for conventional reading of NAND memories.
• a higher VREAD value should be selected that enables the turning on of memory cells that have been programmed to the highest threshold voltage and who are now being read by having a positive source bias which will further raise their high threshold values. Consequently, higher VREAD values may be necessary. These high VREAD values can lead to read disturb. To alleviate this issue read scrubbing (such as is described in U.S.
• patent number 5,532,962 which is hereby incorporated by reference
• This rewriting of the data can be performed by moving the data to another block as is done in wear leveling schemes (such as described in US patent number 6,230,233, publication number US-2004-0083335- Al, and application numbers 10/990,189 and 10/281,739, all of which are hereby incorporated by reference).
• wear leveling schemes such as described in US patent number 6,230,233, publication number US-2004-0083335- Al, and application numbers 10/990,189 and 10/281,739, all of which are hereby incorporated by reference.
• N-I sensing operations
• M ⁇ N sequential sensing operations
• This hybrid scheme may be employed to alleviate the issues that may arise from the lack of availability of dynamic range in allowed source/drain voltages, where the magnitude of the body effect, together with disturb and reliability issues may necessitate the breaking down of a single verify for all (N-I) compares into more than a single verify operation.
• N-I single verify for all
• Erased and subsequently soft-programmed cells in state E will have negative threshold values in the range -1.5V to -0.5V
• cells in state A will have VthS in the range 0.3V to 0.9V
• cells in state B will have VT's in the range 1.5V to 2.1V
• cells in state C will have V ⁇ s in the range 2.7V to 3.3V as measured by this static method.
• the actual memory chips typically employ dynamic sensing which involves pre-charging the bit lines (drains) before the onset of integration, and some amount of discharging of the bit line during the integration period which would indicate whether the cell being sensed is on or off.
• the parameters of dynamic sensing can be chosen such that a V t h measured by the sort of dynamic sensing described above with respect to Figure 10 will have the same value as, or a close value to the cell's V ⁇ measured by the static method.
• a typical read operation for a four state memory using the dynamic sensing method described above with respect to Figure 10 will consist of 3 pre-charge and integration sequences each with the following control gate voltages: OV, 1.2V, and 2.4V.
• OV On the control gate an ON result of the sensing operation will indicate that the cell's state is E, and an OFF result will indicate that the cell's state is A, B, or C.
• 1.2V On the control gate an ON result of the sensing operation will indicate that the cell's state is E or A, and an OFF result will indicate that the cell's state is B or C.
• the threshold voltage of a cell may be IV.
• the same cell with exactly the same amount of charge on its floating gate will have a body effect shifted VT of 2.0V if the source voltage is raised to 0.5V and the drain voltage is raised to 1.0V, maintaining the same value of drain to source voltage.
• a source body effect factor of 2 has been assumed; for other factors, the values should be adjusted accordingly.
• a 0.5V increase in body bias can correspond to a 1.0 V increase in cell Vn 1 .
• bit line voltage is compared to a reference value of, for example, 0.65V in order to determine if the corresponding cell is ON or OFF.
• the non-selected word lines in the NAND block have to be driven to a sufficiently high V READ value of, for example, 5.0V in order to make sure that the cells on the non-selected word lines are not impeding the discharge of the bit line current.
• one preferable embodiment consists of using the body bias single read operation not only during program/verify operations, but also during read operations.
• the same latches that have stored the states that are to be programmed into their corresponding cells can be accessed in order to select the appropriate level of sensing trip point required for verifying the target state on a bit line by bit line basis. For example, if a cell is to be programmed to state A, then the reference trip point voltage for that cell would be (using the exemplary values from above) 1.5 V, whereas programming to state B would require a trip point voltage of 1.0V, and programming to state C would require a trip point voltage of 0.5V.
• three bus lines 103a-c each one carrying one of these voltages, can be designed to extend in the same direction as the word lines, allowing each bit line comparator 101 to use one of these three reference voltages through a MUX 121 whose select signals 103 d are derived from the latches that hold the target state data corresponding to each cell/bit line.
• one bus line 103 will sequentially carry all three voltages, and the each bit line's latch data will determine whether the valid comparison was at a time when reference voltage of 0.5V, 1.0V, or 1.5V was being applied to line 103. (As there is no latch data available during read operations, all three values will need to be compared.)
• three comparators 101a-c exist for each bit line (assuming ABL architecture) or for each pair of bit lines (assuming the more conventional NAND architecture) and the bit line voltage is concurrently compared to three reference voltages. This is at the expense of the extra circuitry required to have three comparators.
• the single comparator of Figure 13B can perform the three comparisons sequentially, affording a more compact design.
• the time penalty of this and other previously discussed sequential operations may be very small, as each comparison can be accomplished in a matter tens of nanoseconds, and the time it takes to change the reference bus line voltages can be very small through a properly designed bus line with small RC delay.
• the interstate sensing delays are neither dictated by RC time constants of the array, nor by the necessary time to pre-charge or sense. This is in contrast to inter-state sensing delays of existing embodiments where the recharge-discharge processes take appreciably longer.
• the present invention employs a hybrid sensing technique.
• multiple V WL values are used, but each according to the method described with respect to Figure 11 , with the cells discharged, allowed to charge up through the source, and then having multiple states sensed.
• For each V WL value a subset of the totality of multi-states are sensed, so that, when the separate sensing sub-operations are completed, sensing has been completed for all of the states. Consequently, all of these subsets will typically be distinct, in that although they may have some states in common, they will differ in at least some members.
• greater efficiency would follow from non- overlapping subsets, in some implementations it may be easier to allow some overlap for additional accuracy and to ensure no states are missed. Additionally, there may be cases where the highest or lowest subsets are contained entirely within a larger, adjacent subset.
• the hybrid approach is combining two somewhat antithetical techniques: the technique of Figure 11 eliminates the need for switching word line voltages for reading, allowing all states (in the 4-state case for Figure 11) to be sensed at once with the complexity of multiple read voltages.
• the more common multiple word line voltage method assigns the usual role to the source and drain sides of the memory cell and can eliminate the more involved operation of switching the source and drain polarities, to engage the body effect. To combine both methods, may at first seem to be over-complicating the sensing scheme.
• Figure 14 is arranged similarly to Figure 11. It shows the process for a 3- bit per cell system that reads four states in a first sensing sub-operation and the other four states in a second sensing operation.
• the same set of comparison values are used for both subsets of states, although more generally a separate set of comparison values may be used in each sub-operation.
• the process can be used for both data reading and program verify, where, as the target data can be known in a program operation, only the target state need be checked in whichever of the two sub-operations it would occur.
• V WLI is taken high enough so that states 0, 1, 2, and 3 can be separated, but not so high that the 0 and 1 states top out and cannot be differentiated. In this embodiment, V WLI leaves the higher states (4, 5, 6, and 7) unresolved. [0082] Once these states stabilize the sense node voltage can be compared with the various compare values as described above with respect to Figure 11 between ti and t2, although in this case four values instead of three are used and the corresponding changes need to be made in Figures 13A-C. This allows for a determination of whether each cell has data content corresponding to these lower states.
• the sensing for the four states is done consecutively, although one or more of the comparisons can be concurrently as described above with respect to Figure 13 (again with the change for four comparison points).
• the word line voltage is raised to V W L2 to differentiate states resolved at V W LI>V W L2- (Here, the word line voltage is stepped up from one sensing operation to the next, although other embodiments could use V W LI>V W L2-) Between t2 and ts the level on the bit lines transition from their response to V WLI to their response to V WL2 -
• the bit lines are not discharged between the sensing sub-operations.
• the bit lines can be discharged between t 2 and ts to, for example, stabilize the pre-charge level on the source side. This can be done in a number of ways, such as taking the selected word line voltage to ground, by taking V SGS to ground (with or without lowering V WL2 ), or otherwise shutting off the source voltage while leaving the drain side open to discharge the cells on the selected word line.
• the preferred embodiment for accomplishing this will depend on the specifics of the particular memory, based on factors such as relative speed and power consumption needed to raise and lower the levels on these different lines.
• bit lines are then allowed to charge back up in response to V WL2 -
• the word bit line can be replaced in the above by the sensing node in order to cover the case where the sensing node is not the bit line as in the ABL architecture.
• the new word line voltage V WL2 will have resolved some of the states that were not resolved for V WLI -
• the bias conditions using V WL2 are able to separate states 4, 5, 6, and 7, although the lower states (determined between ⁇ and ti) have now all coalesced above state 4.
• the second sensing sub- operation is executed.
• this is done in the same way and with the same values as for V WL2 , although different values and techniques could be used in the two cases.
• the two reads with the two word line values were sufficient to cover all of the cells. In other cases, the process can continue on to a third or more additional sensing sub-operations if needed to cleanly resolve all of the states.
• the various alternate sensing techniques described in this section can be particularly advantageous when used in conjunction with a programming method that writes multiple states at the same time.
• a programming method that writes multiple states at the same time.
• Such a method allows the simultaneous programming of multiple states by proportionately retarding the programming of cells whose target threshold voltage levels are lower.
• This target state dependent retarding of programming is achieved by creating semi-inhibit or semi-boosting conditions of various strengths depending on the target state.
• the resulting efficiencies can greatly enhance memory performance by combining these verify/read methods with such concurrent programming of all, or at least multiple states.
• Such concurrent programming can be based on the program voltage of the different cells being dependent upon their target state (as described in U.S.
• the dielectric can be separated into individual elements with the same sizes and positions as the floating gates, it is usually not necessary to do so since charge is trapped locally by such a dielectric.
• the charge trapping dielectric can extend over the entire array except in areas occupied by the select transistors or the like.
• Dielectric storage element memory cells are generally described in the following technical articles and patent, which articles and patent are incorporated herein in their entirety by this reference: Chan et al, "A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device," IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95; Nozaki et al, "A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application,” IEEE Journal of Solid State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501; Eitan et al, "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, Vol. 21, No. 11, November 2000, pp. 543-545, and United States patent no. 5,851,881.

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