Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
  • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
  • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
  • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
  • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
  • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
  • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
  • G06F13/366—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a centralised polling arbiter

Definitions

• the present invention relates to the field of electronics and computers and more particularly the high-performance deterministic buses.
• a local processor bus (or PLB of the English "Processor Local Bus") described with reference to Figure 9 in the patent application US687905 filed by the company International Business Machines Corporation includes several slaves and masters. Also, a bus access priority is set for the masters. In the PLB, the lowest-priority master has access to the bus only when another master with access to the bus releases it.
• this technique has the disadvantage of not guaranteeing bandwidth and latency for each master. Also, this bus is not suitable for low-level communications (including physical layer type (or abbreviated PHY) or access a communication channel (or MAC abbreviated to "Media Access Control”). Neither is it suitable for partitioning between hardware and software resources.
• PHY physical layer type
• MAC MAC abbreviated to "Media Access Control”
• the object of the invention is to allow a deterministic bus intended to be connected to a higher priority main master device and to secondary master peripherals and thus to guarantee a minimum bit rate and / or a maximum latency for a secondary master. to the bus, when the master master uses a small fraction of the time available on the bus.
• the invention proposes a method of access to a bus intended to be connected to a higher priority main master device and to secondary master peripherals, the bus being adapted to the transmission of data to and / or from devices.
• the method comprises: - a bus access authorization step to the main master device when it requests access to the bus;
• the selection step comprises:
• the selection step comprises an arbitration step for access to the bus between the secondary master peripherals when the secondary device that has the token does not request access to the bus.
• the arbitration step comprises:
• the method comprises a step of selecting the type of write or read access.
• the method comprises
• the bus comprises at least one slave device, the method comprising access to the bus for reading and / or writing to a device authorized to transmit data to or from the or at least one of the slave devices.
• the invention also relates to a bus access device for connection to a higher priority master master device and to secondary master peripherals, the bus being adapted for data transmission between the peripherals; advantageously, the device comprises:
• the invention also relates to a system which comprises: a bus;
• the system comprises at least one slave device connected to the bus, the slave device or devices that can not request access to the bus.
• the device or peripherals are memories.
• the main master device comprises a microprocessor.
• the main master device comprises means of access to a wireless medium.
• the system comprises a component that includes the bus and at least one of the secondary master devices and, optionally, the primary master device.
• FIG. 1 is a very schematic diagram of a communication system according to a particular embodiment of the invention.
• FIG. 2 schematically represents the layered structure of the system of FIG. 1;
• FIG. 3 details the system of FIGS. 1 and 2 applied to a device exchanging data with an access layer to the medium;
• FIG. 4 shows a bus implemented in the system of FIG. 1;
• FIGS. 5 and 6 illustrate timing diagrams during data exchanges on the bus of FIG. 4;
• FIG. 7 presents a bus access algorithm of FIG. 4
• FIGS. 8 and 9 show examples of access to the bus of FIG. 4; - Figures 10 and 1 1 illustrate referees adapted to manage access on the bus of Figure 4; and
• Figure 12 shows a master connected to the bus of Figure 4.
• Figure 1 schematically shows a communication system 1 according to a particular embodiment of the invention.
• the system 1 comprises:
• the masters 1 10 to 1 12 are adapted to initiate read and / or write data transfers on the bus 10. They have a lower priority than the master 100 to access the bus.
• the number of masters is not limited and can take any value (for example,
• the invention notably allows a fluidity in the accesses when the number of masters is high.
• Slaves 120 to 123 receive and / or transmit data on the bus 10 and can not initiate data transfers.
• at least one slave is connected to the bus 10.
• FIG. 2 schematically represents the layered structure of the system 1. More specifically, the system 1 implements at least three layers comprising: a physical layer or PHY;
• MAC Media Access Control
• the medium is, for example, a wireless communication layer (for example infra-red, radio (especially according to WiFi standards,
• the bit rate of the transferred data can in particular reach a few hundred megabits.
• Figure 2 shows in particular a distribution between the hardware (or electronic components) and software (or “hardware / software partitioning” in English).
• the system 1 comprises in particular:
• a MAC core 20 comprising the bus 10, the MAC core being connected to a data transmission medium (physical layer) and / or to an application layer; a central unit MAC or MAC CPU (or Central Processing
• an application layer 23 and a random access memory or SDRAM 24 which is connected to the layer 23 via a bidirectional link 28.
• the physical layer 20 and the MAC layer are connected by a PHY-MAC interface 25 which comprises: a bidirectional connection 252 for controlling between the layer 20 and the unit 22; and
• the application layer 23 is connected to the core 20 and the unit 22 via the bus 10 (interface 26) for the data transmission and a bidirectional link 270 respectively.
• the bus 10 is connected to several masters of the same priority (not shown in FIG. 2), to at least one slave (not shown in FIG. 2) and to the unit 22 which is the main master device of the bus with a priority stronger than other masters, says secondary master devices.
• the unit 22 has priority for access to the bus 10 (unlike the state of the art where a CPU has a lower priority than masters to access a bus).
• Figure 3 details the system 1 applied to a device exchanging data with the MAC layer.
• the bus 10 whose access is controlled by the arbiter 13 connects:
• control units of the physical layer respectively in transmission 201 (connected to link 251) and in reception 202 (connected to link 250); two DMA units 321 for sending and 322 for receiving in a security coder 32 (encrypting, for example, data);
• the bus 221 is a control bus of the other units of the system (for example for an initialization). It is implemented, for example, in the form of the so-called APB portion of an AMBA® bus). It is connected to link 252.
• the units 201 to 205, the encoder 32 and the decoder 31 belong to the MAC core 20
• the system of which an example is given for illustrative purposes in FIG. 3 thus comprises:
• a single component comprises the MAC core 20 is, for example, the programmable component type (eg PGA (or "Programmable Gate Array”), PLD (or “Programmable Logic Device”), dedicated component or ASIC (of the English “Application Specifies Integrated Circuit” or “integrated circuit for specific application” in French) or microcontroller
• the invention has the advantage of a very compact bus connecting several masters to the In fact, according to the state of the art, to guarantee a level of bus efficiency inside a component, the bus is divided into complete sub-buses (with data, addresses and controls), each of the sub-buses being assigned to a master.
• the MAC CPU 22 and the MAC core 20 are in the same component.
• the component comprising the MAC core 20 and, if applicable, the MAC CPU 22 also comprises the memory 30.
• the MAC CPU 22, the units 201 and 202, the module 206, the encoder 32 and the decoder 31 are all or in part in separate components.
• the bus 10 is connected to two slave memories.
• the bus 10 can be connected to more slaves.
• Figure 4 shows the bus 10 with some masters (the unit 22 and the encoder 32) and slave (the memory 30 and another memory 301 to better view shared connections or not).
• the unit 22 (respectively 32) is connected to the referee 13 in the master to referee direction via:
• a write address bus 400 (respectively 410) (or "address-write") of 16 bits (or 20 bits according to a variant);
• a write data bus 401 (respectively 41 1) (or “data-write”) of 32 bits (or 16 or 64 bits according to variants);
• a write data size link 402 (respectively 412) (or "size-write”) over 2 bits;
• a read address bus 404 (respectively 414) (or "address-read") of 16 bits (or 20 bits according to a variant);
• a read data size link 405 (respectively 415) (or “size-write”) over 2 bits; and a read request link 406 (respectively 416) (or
• the unit 22 (respectively 32) is connected to the referee 13 in the referee direction to the secondary master device, via:
• a read data bus 407 (or "data-read") of 32 bits (or 16 or 64 bits according to variants) shared by all the masters connected to the bus 13.
• a bus access authorization link connects a secondary master device to the arbitrator 13; in this case, a secondary master device can access to the bus write and read simultaneously if the master device master does not take control.
• a master device can also access the write bus (respectively read) at the same time as the main master device accesses the read bus
• the types of access by the secondary master device and the main master device being different.
• two bus access authorization links connect a secondary master device to the arbiter 13.
• two secondary master peripherals can access to the bus simultaneously, one in writing and the other in reading.
• This variant has the advantage of clarifying access to the bus and allow faster access and / or higher rates.
• the slave 301 (respectively 30) is connected to the referee 13 in the referee to slave direction via:
• a write address bus 420 (or “address-write”) shared by all the slaves connected to the bus 13, of 16 bits (or 20 bits according to a variant);
• a write data bus 421 (or “data-write”) shared by all the slaves, of 32 bits (or 16 or 64 bits according to variants);
• a write data size link 423 (respectively 433) (or “size-write”) over 2 bits; a read address bus 422 (or “address-read”) shared by all the slaves, of 16 bits (or 20 bits according to a variant);
• a read data size link 424 (respectively 434) (or “size-read”) on 2 bits;
• the slaves 30 and 301 are connected to the referee 13 in the slave-to-referee direction, via a read data bus 425 (respectively 435) (or “data-read") of 32 bits (or 16 or 64 bits according to variants).
• the data size signals 402, 412, 405, 415, 423, 433, 424 and 434 make it possible to define several data sizes conveyed on the bus 10.
• three predefined values of Data size is possible, for example: 8, 16 and 32 bits.
• the data bus comprises more than 32 bits (for example, 64 or 128 bits), the predefined values are then chosen according to the size of the bus (for example, for a 64-bit bus, four data size values, namely 8, 16, 32 and 64 bits, can be predefined).
• the predefined values follow an arithmetic progression of factor 2 (a predefined value being equal to twice the previous one).
• the predefined values do not follow an arithmetic progression and may be arbitrary while remaining smaller than or equal to the size of the data bus.
• the data is coded in a fixed size and the data size signals (and the corresponding links) are omitted.
• the arbiter 13 is, for example, implemented in the form of an electronic circuit, a programmable circuit, an ASIC or a microcontroller or microprocessor. Bus cabling identifies the highest priority CPU master (or primary master device), masters of the same priority (or secondary master devices), and slaves.
• the bus 10 comprises other signals such as the clock (or CLK) and reset (or reset) signals which are connected to all the peripherals connected to the bus and to the arbiter 13.
• the clock signal n ' is not shown in the figures to ensure readability.
• FIG. 5 illustrates a timing diagram during data exchanges on the bus 10 according to an embodiment where read and write operations of data can be simultaneous.
• a read operation and a simultaneous write operation are well suited to the masters that allow these operations (for example, masters who have direct access to memory or DMA (Direct Memory Access) in transmission and reception paired).
• DMA Direct Memory Access
• All the signals are synchronous with a clock signal 50.
• the write address signals 51 are activated at the same time as the data 52 for the master which has received authorization from access via the corresponding signal "bus grant". These signals remain valid during a clock cycle.
• a master requests (signal 53 "read-enable") and obtains access to the bus on a rising edge of the clock signal 50.
• the corresponding data (for example provided by the slave) are presented in the cycle of next clock (signal 55), a read access (signal 54) being granted by the referee 13.
• the bus 10 is separated into two separate buses which function respectively for reading and writing.
• the invention allows high rates on the physical layer.
• data rates on the physical layer greater than 100 Mbps with a 32-bit data bus.
• the read / write instantaneous rate can reach 2.56 Gbit / s.
• the clock can be clocked at much higher speeds (for example 80 MHz).
• the flows are then increased proportionally.
• the maximum latency for accessing the bus is equal to the product of the number of secondary master devices by the number of clock ticks per cycle.
• FIG. 6 illustrates a timing diagram during data exchanges on the bus 10 according to an alternative embodiment of the invention, the reading and writing operations being done sequentially and not simultaneously.
• the elements 51 and 52 are common to Figures 5 and 6 and have the same references. They are therefore not described further.
• the data reading signal at a specific address 63 is implemented only when the bus is free to read.
• the bus arbitrator manages in a decorrelated manner the read accesses and the write accesses. Access to the bus is alternately read and write. According to an alternative embodiment of the invention, the read accesses and the write accesses do not occur alternately and the priority between reading and writing is defined in any manner, for example, random, or on the contrary according to a law. predefined, in particular according to the order of arrival and / or according to the priority of the secondary master device requesting access to the bus.
• FIG. 7 presents a bus access algorithm 10 (which can for example be implemented in VHDL when the arbiter is implemented in a programmable component).
• the arbitrator 13 is initialized, the output signals are inactivated and the internal registers (in particular a current master register) are also initialized. Then, read / write cycles of data are implemented. These cycles are synchronized to the clock signal, an elementary loop in the flowchart corresponding to a clock cycle.
• the elementary loop begins with a test 71, during which the arbitrator 13 checks whether the central unit 22 wishes access (write-enable signal or read-enable enabled). If so, access is given to the central unit 22 during a step 72 by activation of the signal 408.
• the central unit 22 has not requested access, and access may be given to another master.
• the arbitrator 13 manages cycles so that each of the secondary masters of the same priority have equitable access to the bus 10. Also, the arbitrator 13 defines an ordered sequence among the secondary master peripherals. Thus, during a step 73, it checks whether it has reached the end of the sequence. If so, during a step 740, it resets the sequence and considers the first secondary master device as the current master. Otherwise, during a step 741, it goes to the next secondary master device in the sequence that becomes the current master.
• the ordered sequence is fixed by being defined a first time in a random manner or according to the types of masters.
• the ordered sequence is randomly changed in step 740.
• master brewing can be achieved for greater equity.
• the ordered sequence is modified during step 740 as a function of external events (for example, as a function of a command transmitted by the main master or a secondary master).
• the arbitrator 13 checks whether the current master M has requested access to the bus. If so, it gives the bus access to the current master during a step 76. If not, it determines a master Mj among the masters who requested access to the bus during a step of arbitration 77 and gives access to the bus during a step 78.
• the arbitration step 77 allows in particular to increase the bandwidth when the current master does not request access to the bus.
• the masters being connected to the bus according to their priority, for example, in a purely electronic implementation, with pins assigned according to the respective priority of the masters);
• an access according to a logical order dependent on the previous accesses for example, access to a master which generally requests access following the access of another given master
• the logical order being for example tabulated
• the algorithm preferably corresponds to a hardware implementation using logic gates.
• the write access signals can be summarized as follows:
• bus-grant (Mp) write-enable (Mp)
• bus-grant (M) wte-enable (Mp)). w ⁇ te-enable (M);
• Mp represents the main master (here unit 22), M the current master and Mj the master determined by an arbitration step;
• bus-grant (X) represents the bus access authorization signal for an X master, write-enable (X), the bus access request signal by a master X and w ⁇ te-enable (X ) the opposite signal (obtainable with an inverting door).
• the operator " Represents a logical multiplication and can be implemented using an AND gate.
• Step 73 can be implemented using a counter.
• the above operations are synchronized to the clock.
• FIGS. 8 and 9 show the successive accesses to the bus 10. More precisely, FIG. 8 corresponds to a simplified implementation that does not provide access to the bus when neither the MAC CPU nor the current master requests the bus (II n there are no steps 77 and 78 in this case).
• FIG. 9 shows the successive accesses to the bus 10 according to the algorithm presented with reference to FIG. 7, implementing an arbitration phase when neither the MAC CPU nor the current master requests the bus.
• the first column represents the masters (the MAC CPU has a parameter ⁇ / equal to i).
• the master with N equal to 5 is the current master does not request access to the bus.
• the secondary master device with N equal to 2 is the current master, it requests and obtains access to the read bus (symbolized by the letter R).
• the unit 22 requests read access and obtains it, prohibiting read access for the secondary master device with N equal to 3.
• the referee gives the hand to the unit 22 in priority or, if the unit 22 does not request access to the bus, to the current master ( ⁇ / taking the successive values of the ordered sequence (2, 3, 4, 5, 6, 7)) in writing (symbolized by the letter W) or in reading.
• the table of FIG. 9 successively comprises the following lines:
• the secondary master device selected by the arbitrator during the selection step, the main master device not requiring access to the bus;
• the master device having access to the bus for reading
• the MAC CPU requests the read hand and thus obtains it.
• the master selected with N equal to 3 does not request the hand; the master with N being 6 being the only master to request access to the bus, during the arbitration step, he gets access to the bus read.
• the master with N equaling 2 requests access to the bus both in writing and writing and obtains this access, the master selected with N equaling 4 not requiring access to the bus.
• the master master and the secondary master devices with N equaling 7 and 5 request access to the bus.
• the master master thus obtains access to the bus.
• the secondary master device with N equaling 3 also requests access to the bus.
• the referee selects the master with N equal to 5. The latter thus obtains access to the bus.
• the master selected with N equaling 6 not requesting access to the bus the referee, during an arbitration step between the masters with N equaling 3 and 7 gives the hand at the device with N worth 7. Then, during a cycle 907, the master with N equal to 3 has access to the bus.
• the arbitration phase makes it possible to use the time slots (or "time slots" in English) when the main master and the secondary master do not request access to the bus.
• FIG. 10 illustrates the structure of the arbiter 13, the read accesses and the write accesses to the bus being decorrelated.
• Referee 13 includes:
• a write-size multiplexer 133 a read access selection module 134;
• the access selection module 130 receives as inputs the signals 403, 413 (respectively 406, 416) write access request write-enaalt from the different masters. It implements the algorithm of Figure 7 to give access to one of the masters and activates, where appropriate:
• one of the access authorization signals (bus-grant) 4010 to 4110 (respectively 409 to 419) associated with the master having received the access authorization;
• the address multiplexer 131 receives the address signals 400, 410 (respectively 404, 414) from the different masters. It outputs the address signals 420 (respectively 422) as a function of the control signal 138 (respectively 139) it receives.
• the address multiplexer 132 also generates a control signal 1390 depending on the device (slave) including the selected address.
• the data multiplexer 132 receives the data signals 401, 41 1 (respectively 425, 435) from the different slaves. It outputs the data signals 421 (data-write) (respectively 407 (data-read)) as a function of the control signal 138 (respectively 1390) that it receives.
• the bus accepts only a slave adapted to provide read data.
• the module 136 and the signal 1390 (and the means generating it) are omitted.
• the size multiplexer 133 receives the signals of size 402, 412 (respectively 404, 414) from the different masters. It outputs the signals of size 433
• control signal 138 (respectively 424) as a function of the control signal 138
• FIG. 11 illustrates a structure of an arbitrator 14 according to an alternative embodiment of the invention, corresponding to an implementation in which read and / or write accesses are authorized for the main master device and / or only one secondary master device during a given cycle.
• Referee 14 is similar to the referee with the exception of modules 131 and 134 which are replaced by a single address selection module 140, the bus being unable to support writing and simultaneous reading.
• Each master receives a read / write access authorization signal 141, 142 which is dedicated to it.
• the other elements are similar, have the same references and are not described further.
• the module 140 receives the write access request authorization signals 403, 413 and read 406, 416 from the different masters connected to the bus. It generates:
• control signals 138 and 139 as a function of the master thus determined and the type or types of access (write or read) requested by the master thus determined.
• the invention is not limited to the embodiments described above.
• the invention is compatible with numbers and functions of masters and / or slave different from those described above.
• the number of data bit, address, data size transmitted in parallel on the bus is not fixed and may take other values than those indicated above according to various embodiments of the invention.
• These signals may in particular be implemented by a CPU (of the English “Central Process Unit” or central processing unit).
• the invention allows a great flexibility of use, facilitates a reconfiguration of a base core for adaptation to a particular application and / or a specific physical layer and is well suited to a modular design.
• the invention is also compatible with a completely electronic implementation (in the form of components) or, conversely, partly with software (for example in the case of "radio software” (or “software radio” in English that can be Reconfigured easily according to the context.)
• the invention is applicable to many fields, and in particular in the field of wired or wireless communications (including an interface with a physical layer of the IEEE 802.16 type, IEEE802.15.3 (UWB )).

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• 2005
  • 2005-12-14 FR FR0553872A patent/FR2894696A1/fr active Pending
• 2006
  • 2006-12-01 US US12/086,457 patent/US20100122000A1/en not_active Abandoned
  • 2006-12-01 CN CN2006800474571A patent/CN101331469B/zh not_active Expired - Fee Related
  • 2006-12-01 WO PCT/EP2006/069181 patent/WO2007068606A1/fr active Application Filing
  • 2006-12-01 EP EP06819883A patent/EP1960891A1/fr not_active Ceased
  • 2006-12-01 JP JP2008544948A patent/JP2009519524A/ja active Pending
  • 2006-12-01 KR KR1020087014190A patent/KR20080080538A/ko not_active Application Discontinuation

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