EP1927210A2 - Technique stroboscopique pour recuperer une horloge dans un signal numerique - Google Patents

Technique stroboscopique pour recuperer une horloge dans un signal numerique

Info

Publication number
EP1927210A2
EP1927210A2 EP06815244A EP06815244A EP1927210A2 EP 1927210 A2 EP1927210 A2 EP 1927210A2 EP 06815244 A EP06815244 A EP 06815244A EP 06815244 A EP06815244 A EP 06815244A EP 1927210 A2 EP1927210 A2 EP 1927210A2
Authority
EP
European Patent Office
Prior art keywords
clock
memory
edge time
signal
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06815244A
Other languages
German (de)
English (en)
Inventor
Ronald A. Sartschev
Ernest P. Walker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teradyne Inc
Original Assignee
Teradyne Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/234,599 external-priority patent/US7573957B2/en
Priority claimed from US11/234,814 external-priority patent/US7574632B2/en
Priority claimed from US11/234,542 external-priority patent/US7856578B2/en
Application filed by Teradyne Inc filed Critical Teradyne Inc
Publication of EP1927210A2 publication Critical patent/EP1927210A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937—Timing aspects, e.g. measuring propagation delay
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
    • G01R31/31726—Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56004—Pattern generation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56012—Timing aspects, clock generation, synchronisation

Definitions

  • the present invention relates generally to testing of semi-conductor chips and more specifically to clocking of digital devices.
  • ATE Automatic test equipment
  • DUT device under test
  • ATE typically determines the relative timing between applied input signals and measured output signals when evaluating the performance of a DUT. Very accurate timing of the test system clock is often required to ensure that appropriate data is collected, particularly when evaluating a DUT's response to high speed signals.
  • ATE can typically be configured to measure output at times relative to the DUT's internal clock.
  • measurements relative to the DUT's system clock can be inaccurate at high data rates and clock speeds because signal slewing and jitter significantly affect measurement results.
  • Embodiments of the present invention recover clock information embedded in a digital signal such as a data signal.
  • a set of strobe pulses is generated by routing an edge generator to a series of delays with incrementally increasing delay values.
  • a digital signal is applied to the input of each of a set of parallel latches which are clocked by the strobe pulses.
  • the set of parallel latches thereby captures a single shot series of samples of the data signal at incrementally increasing delayed times.
  • an encoder converts the single shot series of samples to a word representing edge time and polarity of the sampled signal.
  • the word representing edge time can be stored in memory.
  • An accumulator collects the average edge time over a number (N) of samples. The value N used in the accumulator, which sets the number of samples over which to average data, thereby sets the effective bandwidth of the illustrative embodiments of the present invention.
  • the average edge time is adjusted with a fixed de- skew value, which can be stored in a register, for example.
  • the resulting adjusted time represents a recovered clock time which is then used as a pointer to memory. The difference between the recovered clock time and data edge time stored at the address pointed to by the recovered clock can be determined and compared against expected values.
  • the present invention provides a method for extracting a clock signal from a digital signal by applying a strobe to the digital signal, storing the state of the digital signal at the time of each strobe pulse of the strobe, encoding the stored states as a digital word winch identities an edge time of a state change in the digital signal and determining an average edge time over a predetermined number of samples of the digital word.
  • the digital signal can be a data signal of a device under test, for example.
  • the digital word can be stored in a memory location and the average edge time can be used as a pointer to the memory location.
  • a fixed de-skew value can be added to the average edge time to form an adjusted average edge time.
  • the adjusted average edge time represents the extracted clock which can be used as a pointer to memory.
  • the average edge time or adjusted average edge time can be distributed to a plurality of channels over a bus and used as a pointer to memory on a recipient channel of the plurality of channels. Data edge times stored in memory that are addressed by the average edge time or the adjusted average edge time can be compared with expected data to provide a pass or fail indication for a device under test.
  • the strobe can be applied to the digital signal by applying each edge of the strobe as a latch-clock signal to a corresponding latch of a plurality of latches, applying the digital signal to the input of each of the latches and receiving the state of the digital signal as output of each of the latches.
  • the encoding step results in a multi-bit word of which a first portion identifies the time of the state change and a second portion identifies the polarity of the state change. Transmission of the multi-bit word can be de-multiplexed to reduce a transmission rate thereof.
  • the strobe can be generated by applying an edge generator output signal to delay circuitry including a series of delay elements and providing a connection between each of the delay elements to receive a plurality of sequentially delayed copies of the pulses of the edge generator output signal. Each of the delayed copies forms one of the strobe pulses.
  • the delay circuitry can be controlled by a delay locked loop wherein the delay elements include controllable summing elements which are tunable to correct delay line errors.
  • the illustrative apparatus includes a plurality of increasing strobe delay elements in communication with an edge generator, a plurality of latches, each having a clocking input connected to a corresponding one of the delay elements and having a data input receiving the data signal and an encoder in communication with the plurality of latches.
  • the encoder is adapted to transform information stored in the plurality of latches into a digital word representing edge time of the digital signal.
  • the illustrative embodiment also includes averaging circuitry adapted to receive a plurality of the digital words from the encoder and determine the average thereof.
  • a memory in communication with the encoder can be provided for receiving and storing the digital words.
  • Demultiplexing circuitry can be provided in communication with the encoder and the memory for reducing the rate of data transfer into the memory.
  • the averaging circuitry can include an accumulator in communication with the encoder and receiving the digital words.
  • a clock delay data register stores a de-skew value. Adding circuitry in communication with the accumulator and the clock delay register is adapted for adding the average edge time to the de-skew value to provide an adjusted average edge time which represents an extracted clock value.
  • Routing circuitry in communication with the averaging circuitry and the memory can be provided for addressing the memory using the extracted clock value as a pointer to the memory.
  • the routing circuitry can be adapted for communication with a plurality of channels and can include a clock bus, for example.
  • Comparison circuitry in communication with the memory can be provided for comparing expected values of the data at specific clock times with values of the data in the memory addressed by the extracted clock value.
  • FIG. 1 is a functional block diagram of a method for testing data signals or clock signals of a device under test using particular elements of illustrative embodiments of the present invention
  • FIG. 2 is a schematic timing diagram showing the application of a strobe to digital signals according to illustrative embodiments of illustrative embodiments of the present invention
  • FIG. 3 is a schematic diagram of multi-strobe sampler used in the several illustrative embodiments of the present invention.
  • FIG. 4 is a schematic diagram of an apparatus for testing data signals or clock signals of a device under test using particular elements of illustrative embodiments of the present invention
  • FIG. 5 is a functional block diagram of a method for recovering clock information from a digital signal according to illustrative embodiments of the present invention.
  • FIG. 6 is a schematic diagram of an apparatus for recovering clock information from a digital signal according to illustrative embodiments of the present invention.
  • a sampling step 10 data signals and clock signals of a device under test (DUT) are sampled to acquire binary values of their state at a high rate using a strobe.
  • the sampled data is thus acquired as a single-shot series of samples of the signal under test at incrementally delayed intervals.
  • multiple iterations of the sampling step 10 can be performed, for example on multiple channels or over time in multiple iterations of the inventive clock recovery method, such that a plurality of "single-shot" series can be acquired in various embodiments of the present invention.
  • an edge time and edge polarity of the signal under test is detected.
  • the detected edge time and polarity is encoded in a binary word.
  • the encoded edge time is represented as the five least significant bits of a 6 - bit word and the polarity is represented as the most significant bit.
  • the encoded 6 - bit words are generated at about 2 gigabytes per second.
  • the encoded words are de-multiplexed to provide 48 - bit words at only 250 megabytes per second.
  • the 48 - bit words represent eight 5 - bit edge times and the corresponding eight 1 - bit edge polarities.
  • a selector step 14 it is determined whether the encoded data represents the edge time and polarity of a sampled data signal or the edge time and polarity of sampled clock signal. If the encoded data represents the edge time and polarity of a sampled data signal, a storage step 16 is performed in which the encoded data is stored in random access memory. In the illustrative method a 96 by 40 random access memory is used to store the encoded data. If the encoded data represents the edge time and polarity of a sampled synchronous clock signal, then only encoded data having one polarity is selected and used as a clock edge time. In a clock selection step 18, the encoded clock edge time is routed to a clock bus. Thus, the clock edge data can be routed to a plurality of channels and used in one or more chips.
  • the clock data is used as a pointer to the random access memory address of corresponding encoded data signal edge time.
  • the data edge time found in memory at the clock address is compared to an expected value to determine whether the represented data signal edge time is within pre-specified limits of the represented clock edge time. A pass/fail indication can thereby be automatically generated.
  • FIG. 2 is a schematic timing diagram showing an example of the relative timing of a data signal 24 edge and a clock signal 26 of a device under test.
  • the data signal 24 in a device under test is shown as a voltage/logic level that changes state at edge 28.
  • the clock signal 26 changes state at edge 30.
  • the strobes 32, 34 provide pulses which each trigger a sampling of the state of the data signal under test.
  • the sampling thereby results in a series of bits 36, 38 indicating the state of the data or clock signal under test at closely spaced time intervals.
  • a change of state 40 in the series of bits 38 representing the clock signal can be used as a timing reference for comparison against the state 42 of the data signal in the series of bits 36 representing the data signal.
  • the series of bits 36 and 38 are further encoded before a comparison is made therebetween as described herein with reference to FIG. 1 and FIG. 4.
  • FIG. 3 A sampling apparatus for acquiring strobed samples of a data or clock signal under test is shown in FIG. 3.
  • An initiator signal such as a single strobe pulse is generated by a conventional edge generator, and applied to a delay line input 44.
  • a series of delay elements output incrementally delayed copies 48 of the initiator signal.
  • the incrementally delayed copies 48 of the initiator signal are directed through summing circuitry 50 as known in the art to interpolate between the delay elements and thereby provide additional more closely spaced copies 52 of the initiator signal.
  • the summing circuitry 50 includes summing elements 52 which each comprise a Gilbert cell based on a fine vernier with 8 settings (i.e., 3 - bit control). The settings can be tuned to correct delay line errors.
  • Speed control currents for the delay line elements 46 are provided by a delay locked loop 56.
  • Each of the closely spaced delayed copies of the input strobe pulse are provided to the clock input of a corresponding D- latch 58.
  • the data signal or synchronous clock signal under test 60 is routed to the input to each of the D-latches.
  • the data stored in the D-latches represents a binary snap shot of the states of the data signal, or clock signal under test.
  • a set of 31 D-latches is used to capture a 31 - bit wide strobed representation of the signal under test.
  • FIG. 4 An apparatus for using a strobed representation of the synchronous clock to test data signals in a DUT is described with reference to FIG 4.
  • a signal under test 59 and a strobe 61 are applied to a sampling circuit 62.
  • the sampling circuit 62 is the sampling apparatus described in detail with respect to FIG. 3.
  • An encoder circuit 64 in communication with the sampling circuit 62 accepts the closely spaced strobed representation of the signal under test from the sampling circuit 62 and converts it to a data word representing an edge time and an edge polarity, (i.e., high to low or low to high).
  • the encoder converts a 31 - bit binary snap shot of the edge transition to a 6 - bit word.
  • the most significant bit is used to represent the edge polarity and the remaining 5 - bits are used to represent the edge time.
  • the encoding described herein uses 6 - bit words, and 1 - bit polarity representation for the purposes of illustration, persons having ordinary skill in the art should appreciate that numerous other word lengths can be used and data can be encoded therein under other schemes.
  • the 6 - bit words are output from the encoder at about 2 gigabytes per second.
  • a de-multiplexer 66 in communication with the encoder 64 is used to convert the data into 48 - bit words at a data rate of 250 megabytes per second.
  • the 48 - bit words include eight 5 - bit data words representing edge times and their corresponding 8 single polarity bits.
  • demultiplexing may not be necessary in all cases and that various other bit rates and/or demultiplexing details can be chosen.
  • Router circuitry 70 is used to route signals that represent the synchronous clock of the DUT onto a tester clock bus 72.
  • the routing circuitry 70 also selects only clock edge times with one polarity to represent a system clock, i.e., selects edge times representing a clock set (up polarity) and disregards of the clock reset (down polarity).
  • the clock edge times thereby routed to a tester bus 72 can be used on a plurality of channels.
  • the words output from the de-multiplexer 66 that represent data signals of a DUT are not selected as clock signals and are stored directly in random access memory 68.
  • the data is stored in 96 x 40 random access memory. Persons having ordinary skill in the art should appreciate that numerous other random access memory configuration can be used.
  • the clock edge times on the tester bus 72 are used as pointers to address the data stored in random access memory 68.
  • Routing circuitry 74 selects which clock on the bus to use as a pointer and routes that clock edge time to comparison circuit 76.
  • Comparison circuit 76 provides the clock edge time as an address to random access memory 68 and reads the data edge time stored at that address. The data read from random access memory is compared with the clock edge time to determine the difference therebetween.
  • Comparison circuitry 78 compares expected values 77 of the difference between a data edge and synchronous clock edge with the difference found by comparison circuit 76.
  • the comparison circuitry 78 outputs pass or fail signals for each comparison according to whether the difference from expectations is within specified limits.
  • the various embodiments of the multi-strobe testing method and apparatus described herein may provide a means for representing a signal under test in terms of its precise edge times and polarity of transition at the corresponding edge times.
  • the edge times and polarities thus represented are stored for comparison with a timing signal such as the synchronous clock of a device under test.
  • the timing signal is also represented in terms of its precise edge times.
  • This representation of the timing signal edge time can be provided to a clock bus for use throughout a test system, for example, to compare with a corresponding data signal edge time in random access memory. The result of such a comparison can be checked against an expected value to determine whether a device under test is in compliance with test specifications.
  • An illustrative method of recovering clock information from a data signal can be achieved by adding steps to the method for testing and evaluating synchronously clocked data that was described hereinbefore with reference to FIG. 1.
  • the illustrative method for recovering clock information from a data signal is described generally with reference to FIG. 5.
  • a sampling step 82 is performed in which an edge generator initiates an input strobe.
  • Digital signals such as data signals of a device under test (DUT) are sampled to acquire binary values of their state at a high rate using the strobe. The acquired binary values provide a single-shot series of samples of the digital signal at incrementally delayed intervals.
  • an edge time and edge polarity are detected.
  • the detected edge time and polarity is encoded as a binary word.
  • the encoded edge time is represented as the five least significant bits of a 6 - bit word and the polarity is represented as the most significant bit.
  • the encoded 6 - bit words are generated at about 2 gigabytes per second.
  • the encoded words may be de-multiplexed to provide 48 - bit words at only 250 megabytes per second.
  • the 48 - bit words represent eight 5 - bit edge times and the corresponding eight 1 - bit edge polarities.
  • a storage step 86 is performed in which the encoded edge time is stored in memory.
  • a 96 by 40 random access memory is used to store the encoded edge time.
  • An average accumulator step 88 is performed in which encoded edge times are accumulated over a number (N) of samples and an average edge time over N samples is determined.
  • An average adjustment step 90 can then be performed in which the average edge time is adjusted by a de-skew value.
  • the de-skew value is a fixed value.
  • the adjusted average can be written to a clock bus. The adjusted average represents an extracted clock.
  • a memory accessing step 94 the adjusted average is used as a pointer to the memory address of corresponding encoded data signal edge time.
  • a comparison step 96 the data edge time found in memory at the address pointed to by the extracted clock is compared to an expected value to determine whether the represented data signal edge time is within pre-specified limits of the extracted clock time.
  • a pass/fail indication can thereby be automatically generated.
  • An illustrative apparatus for extracting clock information from a digital signal is described by adding elements to the apparatus for using a strobed representation of the synchronous clock to test data signals in a DUT that was described hereinbefore with reference to FIG 4.
  • the illustrative apparatus for extracting clock information is described generally with reference to FIG. 6.
  • a digital signal 59 from a DUT is applied to a sampling circuit 62.
  • a signal from an edge generator 61 is applied as the second input to sampling circuit 62.
  • the sampling circuit 62 is the sampling apparatus described in detail with respect to FIG. 3.
  • An encoder circuit 64, a de-multiplexer 66, random access memory 68, comparison circuitry 76, and comparison circuitry 78 which operates on expected values 77 to output pass/fail signals 80 are configured and operate as described hereinbefore with reference to FIG. 4.
  • Router circuitry 100 can be used to direct encoded edge times from the de-multiplexer 66 to an accumulator 102.
  • the accumulator 102 collects N samples of the encoded edge times and determines the average edge time over N samples.
  • An initial value register 104 in communication with the accumulator 102 stores the accumulator initial value and provides it to the accumulator for calculating average edge times.
  • a clock delay data register 106 can be used to store a de-skew value for combining with the average edge time provided by the accumulator 102 to adjust the average time as needed for providing a correct pointer value.
  • Adder circuitry 108 in communication with the clock delay data register 106 and the accumulator 102 can be used to combine the de-skew value with the average edge time determined by the accumulator 102 to form an adjusted average edge time.
  • the adjusted average edge time can be communicated to a clock bus 72.
  • the adjusted average edge times represent an extracted clock.
  • the clock edge times thereby routed to a tester bus 72 can be used on a plurality of channels.
  • routing circuitry 74 which is used to select the signal to be used for pointing to memory 68. This signal becomes the random access memory pointer.
  • the extracted clock time from adder circuitry 108 can be used as a pointer to address the data stored in memory 68. Routing circuitry 54 should select the local clock coming from the adder circuitry 108 and route this clock edge time to the comparison circuit 76. hi addition, the clock from adder circuitry 108 can be routed to the clock bus 72 to be used as a clock for other channels if necessary.
  • the comparison circuit 76 provides the clock edge time as an address to memory 68 and reads the data edge time stored at that address. The data read from memory is compared with the clock edge time to determine the difference therebetween.
  • the various embodiments of the present invention provide a means for extracting a clock signal from a digital signal of a device under test by adding elements to the multi-strobe apparatus described hereinbefore.
  • the clock extraction means can be used to complement multi-strobe test methods or can stand alone and perform only clock extraction operations.
  • strobe pulses can include application of a threshold voltage in a cycle of various wave forms such as square wave signals, sine waves signals, triangular waves, impulses and the like to trigger a corresponding latch.
  • a threshold voltage in a cycle of various wave forms such as square wave signals, sine waves signals, triangular waves, impulses and the like to trigger a corresponding latch.
  • a leading edge of a rectangular wave pulse can be used as a strobe pulse in illustrative embodiments of the invention.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

L'invention concerne un procédé et un appareil permettant de récupérer des informations d'horloge intégrées dans un signal numérique. Un ensemble d'impulsions stroboscopiques peut être généré par acheminement d'un générateur de limite à des éléments de retard avec des valeurs de retard augmentant progressivement. Un ensemble de verrous déclenché par des signaux retardés progressivement à partir du générateur de limite peut capturer des échantillons du signal de données. Un codeur peut convertir les échantillons en un mot représentant un temps limite et une polarité du signal échantillonné. Le mot représentant le temps limite peut être stocké en mémoire. Un accumulateur peut recueillir le temps limite moyen sur N échantillons. Le temps limite peut être ajusté sur une valeur de réalignement fixe de façon à former les informations d'horloge extraites, qui peuvent servir de pointeur aux mots stockés en mémoire.
EP06815244A 2005-09-23 2006-09-22 Technique stroboscopique pour recuperer une horloge dans un signal numerique Withdrawn EP1927210A2 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/234,599 US7573957B2 (en) 2005-09-23 2005-09-23 Strobe technique for recovering a clock in a digital signal
US11/234,814 US7574632B2 (en) 2005-09-23 2005-09-23 Strobe technique for time stamping a digital signal
US11/234,542 US7856578B2 (en) 2005-09-23 2005-09-23 Strobe technique for test of digital signal timing
PCT/US2006/037099 WO2007038339A2 (fr) 2005-09-23 2006-09-22 Technique stroboscopique pour recuperer une horloge dans un signal numerique

Publications (1)

Publication Number Publication Date
EP1927210A2 true EP1927210A2 (fr) 2008-06-04

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EP06804068A Withdrawn EP1927204A2 (fr) 2005-09-23 2006-09-22 Technique stroboscopique d'horodatage d'un signal numerique
EP06804013A Withdrawn EP1927203A2 (fr) 2005-09-23 2006-09-22 Technique stroboscopique d'essai de synchronisation de signaux numeriques
EP06815244A Withdrawn EP1927210A2 (fr) 2005-09-23 2006-09-22 Technique stroboscopique pour recuperer une horloge dans un signal numerique

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EP06804068A Withdrawn EP1927204A2 (fr) 2005-09-23 2006-09-22 Technique stroboscopique d'horodatage d'un signal numerique
EP06804013A Withdrawn EP1927203A2 (fr) 2005-09-23 2006-09-22 Technique stroboscopique d'essai de synchronisation de signaux numeriques

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Country Link
EP (3) EP1927204A2 (fr)
JP (3) JP5254794B2 (fr)
KR (3) KR101236769B1 (fr)
WO (3) WO2007038340A2 (fr)

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WO2007038339A2 (fr) 2007-04-05
JP5254794B2 (ja) 2013-08-07
KR101236769B1 (ko) 2013-02-25
KR101239743B1 (ko) 2013-03-06
WO2007038233A3 (fr) 2008-10-30
JP2009509174A (ja) 2009-03-05
WO2007038340A2 (fr) 2007-04-05
KR20080048487A (ko) 2008-06-02
JP4907663B2 (ja) 2012-04-04
JP2009510842A (ja) 2009-03-12
JP2009510403A (ja) 2009-03-12
KR101237878B1 (ko) 2013-02-27
WO2007038233A2 (fr) 2007-04-05
KR20080045714A (ko) 2008-05-23
KR20080047403A (ko) 2008-05-28
EP1927203A2 (fr) 2008-06-04
JP5254795B2 (ja) 2013-08-07
WO2007038340A3 (fr) 2007-11-22
EP1927204A2 (fr) 2008-06-04
WO2007038339A3 (fr) 2007-12-06

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