EP1920462A2 - Procede pour produire un composant semi-conducteur presentant une metallisation planaire et composant semi-conducteur - Google Patents

Procede pour produire un composant semi-conducteur presentant une metallisation planaire et composant semi-conducteur

Info

Publication number
EP1920462A2
EP1920462A2 EP06791327A EP06791327A EP1920462A2 EP 1920462 A2 EP1920462 A2 EP 1920462A2 EP 06791327 A EP06791327 A EP 06791327A EP 06791327 A EP06791327 A EP 06791327A EP 1920462 A2 EP1920462 A2 EP 1920462A2
Authority
EP
European Patent Office
Prior art keywords
insulating layer
component
glass coating
substrate
glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06791327A
Other languages
German (de)
English (en)
Inventor
Karl Weidner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Publication of EP1920462A2 publication Critical patent/EP1920462A2/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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    • H01L2224/82007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting a build-up interconnect during or after the bonding process
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    • H01L2224/82009—Pre-treatment of the connector or the bonding area
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating

Definitions

  • the glass coating is applied by means of physical vapor deposition (PVD) and / or plasma ion assisted deposition (PIAD), in particular electron-beam PVD-PIAD.
  • PVD physical vapor deposition
  • PIAD plasma ion assisted deposition

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

La présente invention concerne un procédé pour produire un composant semi-conducteur, en particulier une structure de semi-conducteur présentant une structure de surface ou une topographie qui est produite sur un substrat (1) au moyen de composants électroniques (2). Selon cette invention, un ou plusieurs composants électroniques (2) sont appliqués sur un substrat (1), puis une couche d'isolation (3) est appliquée sur la topographie produite sur le substrat (1) au moyen du composant (2). Ensuite, des ouvertures de connexion (5) sont ménagées dans la couche d'isolation (3) en des points de connexion (8, 9) dudit composant électronique, la couche d'isolation (3) et les points de connexion (8, 9) sont métallisés de façon planaire dans les ouvertures de connexion (5) et la métallisation est structurée afin de produire des connexions électriques (4). La couche d'isolation (3) présente un revêtement de verre.
EP06791327A 2005-08-30 2006-08-30 Procede pour produire un composant semi-conducteur presentant une metallisation planaire et composant semi-conducteur Withdrawn EP1920462A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102005041099A DE102005041099A1 (de) 2005-08-30 2005-08-30 LED-Chip mit Glasbeschichtung und planarer Aufbau- und Verbindungstechnik
PCT/DE2006/001513 WO2007025521A2 (fr) 2005-08-30 2006-08-30 Procede pour produire un composant semi-conducteur presentant une metallisation planaire et composant semi-conducteur

Publications (1)

Publication Number Publication Date
EP1920462A2 true EP1920462A2 (fr) 2008-05-14

Family

ID=37692604

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06791327A Withdrawn EP1920462A2 (fr) 2005-08-30 2006-08-30 Procede pour produire un composant semi-conducteur presentant une metallisation planaire et composant semi-conducteur

Country Status (8)

Country Link
US (1) US7859005B2 (fr)
EP (1) EP1920462A2 (fr)
JP (1) JP5215853B2 (fr)
KR (1) KR101295606B1 (fr)
CN (1) CN101253623B (fr)
DE (1) DE102005041099A1 (fr)
TW (1) TWI313075B (fr)
WO (1) WO2007025521A2 (fr)

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DE102007033288A1 (de) * 2007-07-17 2009-01-22 Siemens Ag Elektronisches Bauelement und Vorrichtung mit hoher Isolationsfestigkeit sowie Verfahren zu deren Herstellung
US20090079057A1 (en) * 2007-09-24 2009-03-26 Infineon Technologies Ag Integrated circuit device
DE102008011809A1 (de) * 2007-12-20 2009-06-25 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement
DE102008019902A1 (de) * 2007-12-21 2009-06-25 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement und Herstellungsverfahren für ein optoelektronisches Bauelement
DE102008015551A1 (de) * 2008-03-25 2009-10-01 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement mit planarer Kontaktierung und Verfahren zu dessen Herstellung
DE102009039891A1 (de) * 2009-09-03 2011-03-10 Osram Opto Semiconductors Gmbh Optoelektronisches Modul aufweisend zumindest einen ersten Halbleiterkörper mit einer Strahlungsaustrittsseite und einer Isolationsschicht und Verfahren zu dessen Herstellung
DE102009042205A1 (de) * 2009-09-18 2011-03-31 Osram Opto Semiconductors Gmbh Optoelektronisches Modul
CN102456803A (zh) * 2010-10-20 2012-05-16 展晶科技(深圳)有限公司 发光二极管封装结构
US9437756B2 (en) 2013-09-27 2016-09-06 Sunpower Corporation Metallization of solar cells using metal foils
KR101856106B1 (ko) * 2015-04-24 2018-05-09 주식회사 아모센스 세라믹 기판 제조 방법 및 이 제조방법으로 제조된 세라믹 기판
KR101856107B1 (ko) * 2015-04-24 2018-05-09 주식회사 아모센스 세라믹 기판 제조 방법 및 이 제조방법으로 제조된 세라믹 기판
KR101856109B1 (ko) * 2015-04-24 2018-05-09 주식회사 아모센스 세라믹 기판 제조 방법 및 이 제조방법으로 제조된 세라믹 기판
KR101856108B1 (ko) * 2015-04-24 2018-05-09 주식회사 아모센스 세라믹 기판 제조 방법 및 이 제조방법으로 제조된 세라믹 기판
WO2016171530A1 (fr) 2015-04-24 2016-10-27 주식회사 아모센스 Procédé de fabrication de substrat en céramique et substrat en céramique fabriqué par celui-ci
KR102563421B1 (ko) * 2016-07-19 2023-08-07 주식회사 아모센스 세라믹 기판 제조 방법

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TW200715621A (en) 2007-04-16
JP2009506558A (ja) 2009-02-12
CN101253623B (zh) 2010-05-19
CN101253623A (zh) 2008-08-27
WO2007025521A2 (fr) 2007-03-08
KR20080039904A (ko) 2008-05-07
KR101295606B1 (ko) 2013-08-12
US20090278157A1 (en) 2009-11-12
JP5215853B2 (ja) 2013-06-19
DE102005041099A1 (de) 2007-03-29
US7859005B2 (en) 2010-12-28
WO2007025521A3 (fr) 2007-05-03
TWI313075B (en) 2009-08-01

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