CN101253623B - 用于制造具有平面接触的半导体器件的方法以及半导体器件 - Google Patents
用于制造具有平面接触的半导体器件的方法以及半导体器件 Download PDFInfo
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Abstract
在本发明用于制造半导体器件、尤其是具有借助衬底(1)上的电子组件(2)产生的表面结构或形貌结构的半导体结构的方法中,将一个或多个电子组件(2)敷设到衬底(1)上,并且将隔离层(3)敷设到借助衬底(1)上的该至少一个组件(2)产生的形貌结构上。接着在隔离层(3)中的所述至少一个电子组件(2)的接触位置(8,9)上产生接触开口(5),将隔离层(3)和接触位置(8,9)平面地金属化到接触开口(5)中,并且将该金属层结构化以产生电连接(4),其中隔离层(3)具有玻璃涂层。
Description
技术领域
本发明涉及按照权利要求1的前序部分的方法以及利用该方法制造的半导体器件。
本专利申请要求德国专利申请102005041099.5的优先权,在此通过引用将其公开内容包含于此。
背景技术
在由文献WO 03/030247A2公开的平面连接工艺中,这种连接工艺也称为SiPLIT工艺,以预定层厚均匀叠加在形貌结构(Topographie)上的薄膜包围组件,并形成隔离层。利用平面连接技术的平面构成方式的基本原理通过采用隔离膜实现了多种多样的、特定于应用的结构可能。
传统的,目前用透明的灌注材料或隔离膜来覆盖组件。但在采用传统的隔离膜时,热的、针对老化的或针对UV的抵抗力受到部分限制。
发明内容
本发明要解决的技术问题是提供一种改进的半导体器件及其制造方法,该方法结合平面连接工艺,而且其特征尤其在于改进的热机械和化学物理稳定性。尤其是应当具有隔离层,该隔离层能抵抗老化、基本上不受环境因素的影响,而且可以与光源结合来提高光输出。
该技术问题通过按照权利要求1的方法和按照权利要求15的半导体器件解决。优选的实施方式是从属权利要求的内容。
在本发明用于制造半导体器件、尤其是具有借助衬底上的电子组件产生的表面结构或形貌结构的半导体结构的方法中,将一个或多个电子组件敷设到衬底上,并且将隔离层敷设到借助衬底上的该至少一个组件产生的形貌结构上。
通过采用玻璃涂层来代替传统上使用的聚合薄膜,可以为由一个或多个电子组件形成在衬底上的结构、尤其是由一个或多个LED形成的结构产生密闭保护层,使得该结构不会受到环境的影响。另一个优点在于具有很高的透明度,从而可以结合光源实现高的光输出。由于玻璃涂层对紫外线具有很高的UV稳定性,因此该结构的抗老化性相对于传统薄膜来说得到了改善。
玻璃涂层可以实现比较高的热机械稳定性。为此将玻璃涂层的热膨胀系数CTE(coefficient of thermal expansion)优选与至少一个组件和/或衬底匹配。玻璃涂层的热膨胀系数优选具有介于5*10-7K-1(含)和30*10-7K-1(含)之间的值。此外玻璃涂层的特征还在于高的化学物理稳定性。
玻璃涂层用作隔离层基本上不会影响制造平面连接结构的其它方法步骤,从而玻璃涂层的使用可以通过简单方式集成到用于产生平面的连接和组合结构的公知方法中。由此通过用玻璃涂层来代替聚合薄膜,尤其是给出了适用于由文献WO 03/020247A2公开的平面连接方法(SiPLIT方法)的过程。至于用于制造平面连接结构的各个方法步骤,通过引用将该文献的公开内容合并于此。
隔离层可以完全由玻璃涂层组成。根据优选实施方式,玻璃涂层具有硼硅酸盐玻璃。玻璃涂层可以完全由硼硅酸盐玻璃来产生。这种玻璃可以含有强碱。这种玻璃还可以由多个玻璃层组装而成。
按照另一优选实施方式,首先在组件和/或衬底上敷设聚合物涂层,然后敷设隔离层,其中要完成隔离层与组件和衬底面之间的热机械去耦。聚合物涂层优选是高弹性的,使得能平衡热机械张力。优选地,玻璃涂层的膨胀系数(CTE)与组件和衬底面的膨胀系数的差异可以借助该聚合物涂层来平衡。这对于在运行期间组件会剧烈发热的半导体器件来说特别有利,如高功率的LED。聚合物涂层在这种情况下降低了玻璃层由于机械张力而破裂的危险,该机械张力可能由于组件的静止状态和运行状态之间的温度差异而出现。
按照另一优选实施方式,隔离层可以具有并排设置的玻璃涂层和聚合物层。由此隔离层可以有效地与组件的相应功能匹配。玻璃涂层对LED芯片是有利的,尤其是对所发射的射线的至少一部分具有位于紫外线频谱区域的波长的LED芯片很有利,因为玻璃涂层相对于聚合物层来说具有更好的射线稳定性。例如可以让一个或多个设置在衬底上的LED芯片具有由玻璃制成的隔离层,而衬底和/或一个或多个设置在衬底上的其它组件具有由聚合物制成的隔离层。
按照另一优选实施方式,玻璃涂层1仅设置在组件的电激活区域中。作为例如LED芯片的电激活区域,在此假定是发射光的区域。尤其是可以将玻璃涂层敷设在LED芯片的表面和侧面上。
按照另一优选实施方式,所述玻璃涂层密闭地封装了至少一个电组件,尤其是LED芯片。
按照另一优选实施方式,所述玻璃涂层具有5到500μm范围内的厚度。
按照另一优选实施方式,所述玻璃涂层借助物理蒸镀沉积(PVD)和/或等离子辅助沉积(PIAD)、尤其是电子束PVD-PIAD敷设。
按照另一优选实施方式,所述玻璃涂层借助剥离(lift off)方法来结构化。
按照另一优选实施方式,借助激光处理、化学蚀刻、干蚀刻或喷砂来产生接触开口。
按照另一优选实施方式,所述金属化借助例如由TiW和/或TiCu制成的籽晶层(Keimschicht)进行。在此例如借助溅射将薄金属层敷设在隔离层上。对于随后的金属层敷设,例如可以采用CVD、PVD或电解方法。
按照另一优选实施方式,借助光电方法执行金属层的结构化。
附图说明
下面借助附图中的实施例详细描述本发明。
图1示出本发明半导体器件的第一实施例的横截面的示意图,
图2示出本发明半导体器件的第二实施例的横截面的示意图,
图3示出本发明半导体器件的第三实施例的横截面的示意图,
附图中相同或等效的元件具有相同的附图标记。
具体实施方式
图1示出半导体器件,其中LED芯片2设置在衬底1上。衬底1例如可以是晶片、印刷电路板(PCB)和/或柔性材料(Flexmaterial)。
在衬底1上和LED芯片2上敷设了由玻璃制成的隔离层3,例如薄的硼硅酸盐玻璃层。该硼硅酸盐玻璃层既用作LED芯片2的热保护层,也用作衬底1的热保护层。因此玻璃涂层3保护LED芯片2和衬底1免受诸如潮气、灰尘或射线的环境影响。
隔离层3还用于LED2的子区域、尤其是LED芯片2的侧面与电连接4之间的电绝缘,该电连接4用于平面地电接触LED芯片。在此,平面的接触应理解为借助结构化的金属层形成的无线接触,该金属层形成电连接4。因此尤其是不采用接合线(Bonddraht)来接触LED芯片2。这使得半导体器件的结构高度比较低。隔离层3尤其是防止LED芯片2的短路,否则在将金属层4直接敷设到LED芯片2的侧面上时就会出现这样的短路。
薄玻璃涂层3优选通过PVD或PIAD方法产生。
在将隔离层3敷设到电子组件2和衬底1上之后,可以通过剥离技术对隔离层3进行结构化。
在隔离层3上形成电连接4优选通过敷设和结构化金属层来进行。在敷设金属层之前优选在隔离层上敷设薄的、例如由TiCu或TiW制成的籽晶层。对金属层进行结构化例如可以借助照相平板印刷方法进行。借助对金属层的结构化,尤其是可以从金属层4中空出LED芯片的射线逸出平面11。玻璃涂层3优选对由LED芯片2发射的射线是高度透明的。
在该实施例中,LED芯片2的第一连接触点8与位于衬底1的背朝LED芯片2的一面上的背面触点6连接。LED芯片2的第二连接触点9与位于衬底1的面向LED芯片2的一面上的正面触点7连接。当然还可以考虑其它的接触变形。
用作为密闭保护层和介电质的硼硅酸盐玻璃层对LED芯片2的封装尤其适用于平面连接和组装技术,如在专利申请WO 03/030247A2中描述的。
在图2中示出的实施例中,隔离层具有由玻璃涂层3和聚合物层10组成的并排设置的子区域。LED芯片2的表面和侧面具有玻璃涂层3,而衬底1的子区域通过聚合物层10与电连接4绝缘。由此优选隔离层3的直接受到LED芯片2的射线照射的子区域具有玻璃涂层3.
否则第二实施例就相当于第一实施例,尤其是在结合图1描述的优选结构方面。
在图3示出的实施例中,在敷设是玻璃涂层的隔离层3之前,在设置于衬底上的表面结构上敷设聚合物层10,该表面结构包含LED芯片2。
其优点是,玻璃涂层3不直接与组件2邻接,由此减小了通过热张力损坏玻璃层的危险,该热张力可能由于玻璃和组件2和/或衬底1的半导体材料之间的膨胀系数不同而出现。为了平衡热机械张力,优选聚合物涂层是高弹性的。
聚合物层10优选借助PIAD方法敷设到衬底和LED芯片2上。如果在敷设玻璃涂层3之前敷设可能会在高温下降低质量的聚合物层10,则PIAD方法由于在待涂层的组件上比较低的处理温度而成为优选。
否则第三实施例就相当于第一实施例,尤其是在结合图1描述的优选结构方面。
本发明不限于借助实施例进行的描述。本发明还包括每个新特征以及特征的各种组合,该组合尤其是包含权利要求中的特征的各种组合,即使该特征或该组合本身没有在权利要求或实施例中直接给出。
Claims (15)
1.一种用于制造半导体器件的方法,具有步骤:
将一个或多个电子组件(2)敷设到衬底(1)上;
将隔离层(3)敷设到借助衬底(1)上的该至少一个组件(2)产生的形貌结构上;
在隔离层(3)中的所述电子组件的接触位置(8,9)上产生接触开口(5);
将隔离层(3)和接触位置(8,9)平面地金属化在接触开口(5)中;
将该金属层结构化以产生电连接(4),
其特征在于,
所述隔离层(3)具有并排设置的玻璃涂层和聚合物涂层(10)。
2.根据权利要求1所述的方法,其特征在于,所述玻璃涂层具有硼硅酸盐玻璃。
3.根据权利要求1或2所述的方法,其特征在于,所述玻璃涂层仅设置在组件(2)的电激活区域中。
4.根据权利要求1至2中任一项所述的方法,其特征在于,所述玻璃涂层密闭地封装和/或覆盖所述电子组件(2)。
5.根据权利要求1或2所述的方法,其特征在于,所述玻璃涂层具有5到500μm的厚度。
6.根据权利要求1或2所述的方法,其特征在于,所述玻璃涂层借助物理蒸镀沉积方法和/或物理蒸镀沉积-等离子辅助沉积方法敷设。
7.根据权利要求1或2所述的方法,其特征在于,所述玻璃涂层借助剥离方法来结构化。
8.根据权利要求1或2所述的方法,其特征在于,借助激光处理、化学蚀刻、干蚀刻或喷砂来产生接触开口(5)。
9.根据权利要求1或2所述的方法,其特征在于,所述金属化借助籽晶层进行。
10.根据权利要求1或2所述的方法,其特征在于,借助光电结构化执行金属层的结构化。
11.根据权利要求1或2所述的方法,其特征在于,所述至少一个电子组件(2)是发射射线的光电子组件。
12.根据权利要求11所述的方法,其特征在于,所述光电子组件(2)是LED芯片。
13.一种半导体器件,具有衬底(1),在衬底上敷设了一个或多个电子组件(2),还具有敷设在该至少一个组件(2)上的隔离层(3),以及在隔离层(3)中的所述电子组件的接触位置(8,9)上的接触开口(5),其中隔离层(3)和接触位置(8,9)平面地金属化在接触开口(5)中,而且对该金属层结构化以产生电连接(4),
其特征在于,
所述隔离层(3)具有并排设置的玻璃涂层和聚合物涂层(10)。
14.根据权利要求13所述的半导体器件,其特征在于,所述半导体器件是光电子器件。
15.根据权利要求14所述的半导体器件,其特征在于,所述光电子器件包含一个或多个LED芯片(2)。
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PCT/DE2006/001513 WO2007025521A2 (de) | 2005-08-30 | 2006-08-30 | Verfahren zur herstellung eines halbleiterbauelements mit einer planaren kontaktierung und halbleiterbauelement |
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DE102007033288A1 (de) * | 2007-07-17 | 2009-01-22 | Siemens Ag | Elektronisches Bauelement und Vorrichtung mit hoher Isolationsfestigkeit sowie Verfahren zu deren Herstellung |
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DE102008011809A1 (de) | 2007-12-20 | 2009-06-25 | Osram Opto Semiconductors Gmbh | Optoelektronisches Bauelement |
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DE102008015551A1 (de) * | 2008-03-25 | 2009-10-01 | Osram Opto Semiconductors Gmbh | Optoelektronisches Bauelement mit planarer Kontaktierung und Verfahren zu dessen Herstellung |
DE102009039891A1 (de) * | 2009-09-03 | 2011-03-10 | Osram Opto Semiconductors Gmbh | Optoelektronisches Modul aufweisend zumindest einen ersten Halbleiterkörper mit einer Strahlungsaustrittsseite und einer Isolationsschicht und Verfahren zu dessen Herstellung |
DE102009042205A1 (de) * | 2009-09-18 | 2011-03-31 | Osram Opto Semiconductors Gmbh | Optoelektronisches Modul |
CN102456803A (zh) * | 2010-10-20 | 2012-05-16 | 展晶科技(深圳)有限公司 | 发光二极管封装结构 |
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KR101856108B1 (ko) * | 2015-04-24 | 2018-05-09 | 주식회사 아모센스 | 세라믹 기판 제조 방법 및 이 제조방법으로 제조된 세라믹 기판 |
US10529646B2 (en) | 2015-04-24 | 2020-01-07 | Amosense Co., Ltd. | Methods of manufacturing a ceramic substrate and ceramic substrates |
KR101856106B1 (ko) * | 2015-04-24 | 2018-05-09 | 주식회사 아모센스 | 세라믹 기판 제조 방법 및 이 제조방법으로 제조된 세라믹 기판 |
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