EP1597757A2 - Technique des connexions destinee a des semi-conducteurs de puissance et utilisant une matiere electriquement isolante qui suit les contours de surface - Google Patents

Technique des connexions destinee a des semi-conducteurs de puissance et utilisant une matiere electriquement isolante qui suit les contours de surface

Info

Publication number
EP1597757A2
EP1597757A2 EP04705063A EP04705063A EP1597757A2 EP 1597757 A2 EP1597757 A2 EP 1597757A2 EP 04705063 A EP04705063 A EP 04705063A EP 04705063 A EP04705063 A EP 04705063A EP 1597757 A2 EP1597757 A2 EP 1597757A2
Authority
EP
European Patent Office
Prior art keywords
layer
insulating material
electrically insulating
component
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04705063A
Other languages
German (de)
English (en)
Inventor
Norbert Seliger
Karl Weidner
Jörg ZAPF
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP1597757A2 publication Critical patent/EP1597757A2/fr
Withdrawn legal-status Critical Current

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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Definitions

  • the chip surface is contacted via a solder that is introduced through holes in a ceramic plate.
  • the contacts are made using soldered copper posts.
  • DCB Direct Copper Bonding
  • Power semiconductors are applied to a film stretched in a frame.
  • the object of the invention is to provide a method for contacting one or more electrical contact surfaces of a component located on a substrate, which is suitable for power electronics and in which there is the possibility of contacting a conductor track located on the substrate even in the case of high-power components.
  • a layer of electrically insulating material on the substrate and the The component is applied such that the layer of electrically insulating material follows the surface contour formed from the substrate and the component, that is to say that the layer of electrically insulating material runs on the surface contour in accordance with the surface contour formed from the substrate and the component.
  • logic chips are embedded in a polymer according to the prior art, only the underside of the polymer layer follows the surface contour, but not the polymer layer itself.
  • the layer of electrically insulating material follows the surface contour formed from the substrate and the component, there are two advantages, in particular if a power component is used as the component. On the one hand, a sufficient thickness of the layer of electrically insulating material is guaranteed over the edges of the component facing away from the substrate, so that breakdown at high voltages or field strengths is prevented. On the other hand, the layer of electrically insulating material is usually very high in addition to the
  • Power component on the substrate is not so thick that an exposure and contacting of contact areas on conductor tracks of the substrate would be problematic.
  • the electrical contact surface of the component remains free when the layer of electrically insulating material is applied and / or is exposed after the layer of electrically insulating material has been applied, in particular by opening a window.
  • a layer of electrically conductive material is applied to the layer of electrically insulating material and the electrical contact surface of the component.
  • the layer of electrically insulating material is therefore a carrier layer for the layer of electrically conductive material.
  • the layer of electrically insulating material is in particular not a film.
  • the thickness of the layer of electrical, insulating material above the substrate in its rectilinear region deviates by less than 50% from its thickness above the component in its rectilinear region, in particular by less than 20%.
  • the thicknesses are preferably approximately the same, that is to say deviate from one another by less than 5% or even less than 1%.
  • the percentages relate in particular to the thickness of the layer above the component in its rectilinear area, which accordingly indicates 100%.
  • the rectilinear area is used because the layer in the inner edges of the substrate and the component is generally thicker, and generally thinner over the edges of the component facing away from the substrate.
  • the substrate For contacting the component with the substrate, the substrate preferably has an electrical contact surface which remains free when the layer of electrically conductive material is applied or is exposed after the layer of electrically insulating material is applied and to which the layer of electrically conductive material is likewise applied becomes.
  • the contact surface of the component is connected to the contact surface of the substrate via the layer of electrically conductive material.
  • the contact area of the component and the contact area of the substrate are preferably approximately the same size in order to ensure a continuous current flow.
  • the electrical contact surface of the component can be left free when the layer of electrically insulating material is applied and / or later exposed. The complete or partial release already during application can be realized particularly advantageously if the layer of electrically insulating material with openings is applied. Then a layer of electrically insulating material with one or more corresponding openings or windows can be used from the outset, which can be created beforehand, for example, by inexpensive punching or cutting.
  • the method can be used for power components whose contact area is a have the appropriate size.
  • the size of the window should not be more than 99.9% of the size of the side and / or area of the component on which the window is opened, in particular not more than 99% and more preferably not more than 95%.
  • the window is opened in particular on the largest and / or on the side of the component facing away from the substrate and preferably has an absolute size of more than 50 mm 2 , in particular more than 70 mm 2 .
  • Any substrates on an organic or inorganic basis can be used as substrates.
  • Substrates are, for example, PCB (Printed Circuit Board), DCB, IM (Insulated Metal), HTCC (High Temperature Cofired Ceramics) and LTCC (Low Temperature Cofired Ceramics) substrates.
  • the layer of electrically insulating material is in particular made of plastic. Depending on the further processing, it can be photosensitive or non-photosensitive.
  • curtain casting dipping, in particular one-sided dipping, spraying, in particular electrostatic spraying, printing, in particular screen printing, overmolding, dispensing, spin coating.
  • the layer of electrically conductive material that is to say for two-dimensional contact
  • physical or chemical deposition of the electrically conductive material is advantageously carried out.
  • Such physical processes are sputtering and vapor deposition (Physical Vapor Deposition, PVD).
  • Chemical deposition can be carried out from the gaseous phase (Chemical Vapor Deposition, CVD) and / or liquid phase (Liquid Phase Chemical Vapor Deposition). It is also conceivable that a thin electrically conductive partial layer, for example made of titanium / copper, is first applied by one of these methods, on which a thicker electrically conductive partial layer, for example made of copper, is then deposited.
  • A is preferably used in the method according to the invention
  • Substrate with a surface used with one or more semiconductor chips in particular
  • Power semiconductor chips are fitted, on each of which there is or are one or more contact surfaces to be contacted, and the layer of electrically insulating material is applied to this surface under vacuum, so that the layer of electrically ⁇ insulating material.
  • Surface including each semiconductor chip and each contact area closely covered and adheres to this surface including each semiconductor chip.
  • the layer of electrically insulating material is designed so that a height difference of up to 10.00 ⁇ m can be overcome. The height difference is caused, among other things, by the topology of the substrate and by the semiconductor chips arranged on the substrate.
  • the thickness of the layer of electrically insulating material can be 10 ⁇ m to 500 ⁇ m.
  • a layer of electrically insulating material with a thickness of 25 to 150 ⁇ m is preferably applied.
  • the application is repeated until a certain thickness of the layer of electrically insulating material is reached.
  • partial layers made of electrically insulating material of smaller thickness are processed to form a layer made of electrically insulating material of higher thickness.
  • These partial layers made of electrically insulating material advantageously consist of a type of plastic material. It is also conceivable that the partial layers made of electrically insulating material consist of several different plastic materials. The result is a layer made of partial layers of electrically insulating material.
  • a window in the layer of electrically insulating material is opened by laser ablation to expose the electrical contact surface of the component.
  • the wavelength of a laser used for this is between 0.1 ⁇ m and 11 ⁇ m.
  • the power of the laser is between 1 W and 100 W.
  • a CO 2 laser with a wavelength of 9.24 ⁇ m is preferably used.
  • the windows are opened without damaging a chip contact made of aluminum, gold or copper, which may be under the layer of insulating material.
  • a photosensitive layer made of electrically insulating material is used and a window is opened by a photolithographic process to expose the electrical contact surface of the component.
  • the photolithographic process comprises exposing the photosensitive layer of electrically insulating material and developing and thus removing the exposed or unexposed areas of the layer of electrically insulating material.
  • a cleaning step is optionally carried out in which remnants of the layer of electrically insulating material are removed.
  • the cleaning step is carried out, for example, by wet chemistry. In particular, a plasma cleaning process is also conceivable.
  • a layer of several partial layers of different, electrically conductive material arranged one above the other is used.
  • different metal layers are applied one above the other.
  • the number of sub-layers or metal layers is, in particular, 2 to 5.
  • a sub-layer functioning as a diffusion barrier can be integrated, for example, by the electrically conductive layer composed of a plurality of sub-layers.
  • Such a partial layer consists, for example, of a titanium-tungsten alloy (TiW).
  • TiW titanium-tungsten alloy
  • a partial layer that promotes or improves adhesion is advantageously applied directly to the surface to be contacted.
  • Partial layer consists for example of titanium.
  • At least one conductor track is produced from the electrically conductive material after the two-dimensional contacting and / or on the layer.
  • the conductor track can be applied to the layer.
  • a is used to generate the conductor track Structuring the layer performed. This means that the conductor track is created in this layer.
  • the conductor track is used, for example, to make electrical contact with a semiconductor chip.
  • the structuring is usually carried out in a photolithographic process.
  • a photoresist can be applied to the electrically conductive layer, dried and then exposed and developed.
  • a tempering step may follow in order to stabilize the applied photoresist against subsequent treatment processes.
  • Conventional positive and negative resists (coating materials) can be used as photoresist.
  • the photo lacquer is applied, for example, by a spraying or dipping process.
  • another structurable material can be used with one or more of the following
  • Procedures are applied: curtain casting, dipping, in particular one-sided dipping, spraying, in particular electrostatic spraying, printing, in particular screen printing, overmolding, dispensing, spin coating, laminating a film.
  • photosensitive foils can also be used, which are laminated on and exposed and developed in a manner comparable to the applied photoresist layer.
  • the following can be used to produce the conductor track: in a first sub-step, the electrically conductive layer is structured and in a subsequent sub-step a further metallization is applied to the conductor track produced.
  • the conductor track is reinforced.
  • copper becomes on the conductor track produced by structuring galvanically deposited in a thickness of 1 ⁇ m to 400 ⁇ m.
  • the photoresist layer or the laminated film or the structurable material used alternatively is then removed. This can be done, for example, with an organic solvent, an alkaline developer or the like. Subsequent differential etching removes the flat, metallically conductive layer that is not reinforced with the metallization.
  • the reinforced conductor track is retained.
  • the steps of laminating, exposing, contacting and generating the conductor track are carried out several times to produce a multilayer device.
  • the invention advantageously provides a novel technology for the electrical contacting and wiring of connection pads or contact surfaces which are arranged on semiconductor chips, in particular on power semiconductor chips.
  • the flat connection and the special insulation result in a low-inductance connection in order to enable fast and low-loss switching.
  • An electrical insulation layer is produced by applying the layer of electrically insulating material.
  • the production of the insulation layer by applying the layer of electrically insulating material according to the invention offers the following advantages: Use at high temperatures. With a suitable choice of material, a layer of electrically insulating material is heat-resistant up to 300 ° C.
  • the entire chip contact area can be used so that high currents can be derived.
  • the chips can be controlled homogeneously due to the flat contact.
  • the inductance of the contact in a contact area is smaller due to the areal geometry than with thick wire bonding.
  • Preferred and advantageous configurations of the device result from the preferred configurations of the method.
  • Figure 1 shows a method for contacting a power semiconductor.
  • the substrate of the example is generally designated 1 in FIG.
  • This substrate 1 has, for example, a DCB Substrate consisting of a substrate layer 10 made of ceramic material, a layer 12 made of copper applied to a lower surface of the substrate layer 10 and a layer 11 made of copper applied to a surface of the substrate layer 10 facing away from the lower surface.
  • the layer 11 on the upper surface of the substrate layer 10 is partially removed down to the upper surface of the substrate layer 10, so that the upper surface is exposed there.
  • Conductor tracks are formed on the substrate by the layers 11 and 12 made of copper.
  • One or more are on the surface of the remaining copper layer 11 facing away from the substrate layer 10
  • Applied semiconductor chips 2 which may be the same and / or different from each other.
  • the semiconductor chip 2 which is preferably a power semiconductor chip, contacts the upper surface of the layer 11 of copper with a contact surface, not shown, which is present on a lower surface of the semiconductor chip 2 facing the layer 11 of copper.
  • this contact surface is soldered to the layer 11 made of copper.
  • the contact area on the lower surface of this semiconductor chip 2 is the contact area of a collector or drain contact and the contact on the upper surface of the semiconductor chip 2 is an emitter or source contact, the contact area of which is the contact area 210.
  • the entire upper surface of the substrate 1 equipped with the semiconductor chip 2 is given by the exposed parts of the upper surface of the substrate layer 10, the upper surface of the layer 11 of copper outside of the semiconductor chips 2 and by the free surface of each semiconductor chip 2 itself, which by the upper surface and the lateral surface of this chip 2 is determined.
  • step 301 a layer 3 of electrically insulating plastic material is applied under vacuum to the entire surface of the substrate 1 equipped with the semiconductor chip 2, so that the layer 3 of electrically insulating material tightly contacts the surface of the substrate 1 equipped with the semiconductor chip 2 covered and adheres to this surface.
  • the layer 3 of electrically insulating material follows that through the exposed parts of the upper surface of the substrate layer 10, the upper one
  • the layer 3 made of electrically insulating material is preferably applied in step 301 using one or more of the following procedures: curtain casting, dipping, in particular one-sided dipping, spraying, in particular electrostatic spraying, printing, in particular screen printing, overmolding, dispensing, spin coating.
  • the layer 3 made of electrically insulating material serves as an insulator and as a carrier for a layer 4 made of electrically conductive material that is applied further on.
  • Typical thicknesses of layer 3 made of electrically insulating material are in the range of 25-150 ⁇ m, whereby larger thicknesses can also be achieved from layer sequences of thinner partial layers made of electrically insulating material. This advantageously enables insulation field strengths in the range of a few 10 kV / mm to be achieved.
  • each contact surface to be contacted is opened on the surface of the substrate 1, including the component 2, by opening respective windows 31 in FIG.
  • a contact area to be contacted is not only a contact area 210 on a semiconductor chip 2, but can also be any region of the upper surface of the layer 11 made of copper or another metal which is exposed by opening a window 31 in the layer 3 made of electrically insulating material.
  • Contact area (210) is opened is more than 60% of the size of the component, in particular more than 80%.
  • One of the windows 31 in the layer 3 made of electrically insulating material is preferably opened by laser ablation.
  • each exposed contact surface 210 of the component and exposed contact surface 112 of the substrate is coated with a layer 4 of electrically conductive
  • Material preferably metal, is contacted over the surface by metallizing and structuring the exposed contact surfaces 210 and 112 using the usual methods and thus making contact in a planar manner.
  • the layer 4 made of electrically conductive material can cover the entire surface of both contact surfaces 210 and 112 as well as on the upper surface of the layer 3 made of electrically insulating material facing away from the surface of the substrate 1 and thereafter, for example, structured photolithographically so that each contact surface 210 and 112 remains in contact with the surface and via the contact surfaces 210 and 112 and the layer 3 Conductive tracks 4, 6 are formed from insulating material.
  • step 303 Sputtering a Ti adhesive layer of approximately 100 nm in thickness and a Cu conductive layer 4 of approximately 200 nm in thickness.
  • a mask is applied to the upper surface of the layer 3 made of electrically insulating material facing away from the surface of the substrate 1, said mask covering the contact areas 210 and 112 and areas for the contact areas 210 and 112 and the layer 3 leaves conductive tracks 4, 6 extending from insulating material, and that layer 4 of the electrically conductive material is then applied over the entire area to the mask and the contact surfaces 210 and 112 and to the areas free of the mask.
  • the mask with the layer 4 located thereon is then removed, so that only the surface-contacted contact surfaces 210 and 112 and the over the contact surfaces 210 and 112 and the layer 3 of insulating material running conductor tracks 4, 6 remain on the mask-free areas.
  • a device is then provided from a substrate 1 with component 2 with a surface on which electrical contact surfaces 210, 112 are arranged, in which an insulator in the form of a layer 3 of electrically insulating material is applied to the surface, which is closely attached bears on the surface and adheres to the surface and in which the layer 3 of electrically insulating material has windows 31 in each case at the contact surfaces 210 and 112, in which this contact surface 210, 112 is free of the layer 3 of electrically insulating material and flat with one layer 4 and, for example, is additionally contacted with a layer 6 of electrically conductive material.
  • Special designs of this device result from the above description.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

On applique une couche de matière électriquement isolante sur un substrat et un composant posé dessus, de telle manière que cette couche suive les contours de surface formés par le substrat et le composant.
EP04705063A 2003-02-28 2004-01-26 Technique des connexions destinee a des semi-conducteurs de puissance et utilisant une matiere electriquement isolante qui suit les contours de surface Withdrawn EP1597757A2 (fr)

Applications Claiming Priority (3)

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DE10308978 2003-02-28
DE10308978 2003-02-28
PCT/EP2004/000629 WO2004077548A2 (fr) 2003-02-28 2004-01-26 Technique des connexions destinee a des semi-conducteurs de puissance et utilisant une matiere electriquement isolante qui suit les contours de surface

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EP (1) EP1597757A2 (fr)
JP (1) JP4763463B2 (fr)
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JP2006514785A (ja) 2006-05-11
JP4763463B2 (ja) 2011-08-31
US7208347B2 (en) 2007-04-24
US20060192290A1 (en) 2006-08-31
US20070216025A1 (en) 2007-09-20
WO2004077548A3 (fr) 2005-05-12
WO2004077548A2 (fr) 2004-09-10
US7855451B2 (en) 2010-12-21
CN100499053C (zh) 2009-06-10
CN1757103A (zh) 2006-04-05

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