Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
  • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Definitions

• MOS transistors generally comprise a polycrystalline silicon gate.
• Figure 1 is a schematic sectional view of such a transistor.
• a transistor 2 is formed between shallow isolation zones 3, for example made of silicon oxide, commonly known as STI (Shallow Trench Isolation).
• the transistor 2 comprises a polycrystalline silicon gate 4 formed on a gate insulator 5 which may be an example of silicon oxide or a material with a high dielectric constant such as hafnium oxide.
• Lightly doped zones 8 and 9, commonly called LDD (Lightly Doped Drain), are then produced, for example by ion implantation.
• spacers 10 of insulating material, for example oxide or silicon nitride.
• Source 11 and drain 12 areas are performed, for example by ion implantation.
• Source areas 11 and drain 12 as well as on the top of the gate 4 are simultaneously developed contacts 13, 14 and 16 metal silicide, for example silicon nitride.
• the gate structure is thus composed of a stack ⁇ ment of an insulating layer, a polycrystalline silicon layer doped by ion implantation and a metal silicide layer.
• the first reason is to overcome the phenomenon of depletion of polycrystalline silicon. Indeed, the electrons of the gate 4 are repelled with respect to the gate oxide 5. A depletion zone is thus created above the oxide 5 with fewer carriers. By way of example, this zone may have a thickness of 0.4 nm. A parasitic capacitance is thus generated in series with the capacity of the gate oxide 5, the capacitance of the assembly becoming lower. Since the operating current of the transistor is proportional to this capacitance, it will be lower. The second reason is to decrease the resistance of the grid.
• Figure 2 is a schematic sectional view illus trating ⁇ a possibility to realize a fully silicided gate. We start from a structure such as that of the figure
• an insulating layer 31 made of silicon oxide, a polycrystalline silicon layer 32 and then a hard oxide mask layer are successively formed. of silicon 33.
• the three layers 31, 32 and 33 are etched successively. This results in a grid pattern 34 consisting of a stack of a gate oxide 36, an insulated gate 37 and a hard mask 38.
• the implantations of LDD zones 8 and 9 are carried out using the grid pattern 34 as a mask and then spacers 10 are made before doping source 11 and drain 12 zones using the grid pattern as mask.
• the source and drain zones 12 are metallically silicided to obtain the contact zones 13 and 14.
• the hard mask 38 before depositing a thick layer of oxide 40.
• a planarization of the layer 40 is carried out by chemical mechanical polishing CMP
• the layer 40 is etched until the grid 37 is exposed.
• nickel layer 41 before annealing for a period of time sufficient to completely silicide polycrystalline silicon 37.
• FIG. 3G is a schematic sectional view of the resulting MOS transistor whose gate 20 is completely siliconized.
• the gate structure is therefore composed of a stack of an insulating layer and a metal silicide layer.
• this manufacturing process is difficult to implement because of the high number of steps that it requires and is critical regarding the uniformity of the Supe ⁇ higher area of the grid due to the presence of a CMP planarization step. Summary of the invention
• An object of the present invention is to obtain a new structure of the fully siliconized gate MOS transistor.
• the encapsulation layer is selected from the group consisting of titanium nitride and tantalum nitride. According to one embodiment of the present invention, the thickness of the metal silicide layer is less than 25 nm.
• the thickness of the encapsulation layer is less than 20 nm.
• the gate further comprises a second layer of a metal silicide at the top of the polysilicon layer.
• the present invention also provides a process for fabri ⁇ cation of a MOS transistor gate comprising the sequential steps of forming an insulating layer of gate insulator; forming a thin polycrystalline silicon layer; implanting an N or P type dopant in the polycrystalline silicon layer; transforming the polycrystalline silicon into a metal silicide; forming a layer of a material conduc tor ⁇ encapsulation; and forming a layer of polysilicon ⁇ lens so that the total thickness of the grid have the usual thickness of a gate in a MOS transistor fabrication given technology.
• FIG. 1, previously described is a schematic sectional view of a conventional transistor comprising a polycrystalline silicon gate
• Figure 2 previously described, is a schematic sectional view of a conventional transistor comprising a metal silicide grid
• FIGS. 3A to 3G previously described, illustrate a conventional manufacturing method making it possible to obtain a totally silicided grid
• 4A to 4D illustrate a method of manufac ⁇ a gate of a MOS transistor according to the invention.
• FIGS. 4A to 4D The present invention will be described in relation to FIGS. 4A to 4D in the context of a particular method of obtaining the desired structure, it being understood that this method constitutes only one example and that those skilled in the art may devise other methods for arriving at the invention and variants of the structure according to the invention.
• a solid silicon substrate 1 or constituted by a layer of silicon on insulator or any other conventional integrated circuit substrate In the substrate 1 is defined an active region delimited by insulating zones 3.
• an insulating thin layer 31 is formed for serving as a gate oxide.
• a thin layer of polycrystalline silicon 50 is deposited.
• the layer 31 intended to serve as a gate oxide layer will have a thickness of the order of a few nanometers.
• the polycrystalline silicon layer 46 will for example have a thickness of the order of 10 to 30 nm.
• the structure is covered with a mask 51 having an opening which projects relative to the location where it is desired to form higher ⁇ the grid.
• FIG. 4B results from a succession of steps during which the mask 51 is eliminated and any known means, for example a metal layer deposited and annealed, are subjected to the silicidation of the thin layer.
• polycrystalline silicon 50 The metal is for example nickel or cobalt which has the property of rejecting at conventional silicon doping dopants such as As, B, P are then deposited.
• a layer 53 of an encapsulating conductive material is then deposited which does not react with the polycrystalline silicon, for example TiN or TaN on a sufficient thickness to provide the desired encapsulation function. After which a polycrystalline silicon layer 55 is deposited.
• the thickness of the polycrystalline silicon layer 55 is chosen so that the total thickness of the layers 50, 53, 55 corresponds to the thickness commonly used of a grid in a techno. - vector gy of manufacturing MOS transistors as described in connection with Figure 1.
• the thickness of the polycrystalline silicon layer 55 is chosen so that the total thickness of the layers 50, 53, 55 corresponds to the thickness commonly used of a grid in a techno. - vector gy of manufacturing MOS transistors as described in connection with Figure 1.
• the etched stack ⁇ gate 31, 50, 53, 55 to form a grid having the usual desired configuration.
• LDD zones 8 and 9 are implanted, side spacers 10 are formed around the grid, and then source areas 11 and drain 12 are implanted.
• source areas 11 and drain 12 are implanted.
• the upper polycrystalline silicon portion 55 of the grid will be implanted, which will therefore be made highly conductive.
• a conventional siliciding step is performed to silicide the upper part of the source 11 and drain 12 zones and obtain silicide regions 13 and 14.
• a silicic region 57 is obtained. on the top of the grid stack.
• NiSi NiSi
• the encapsulation layer overcomes this disadvantage.
• dopant ion implantation has been carried out in the polycrystalline silicon layer 50 prior to its silicidation.
• the dopant chosen is not or only slightly soluble in silicide.
• N- or P-type dopants remain and modify in a desired manner the gate extraction work for operation. optimum of an N-channel or P-channel transistor.
• the grid according to the present invention is not totally silicided as there is a region 55 of non-silicided polycrystalline silicon. In fact, this has no effect on the operation of the transistor gate according to the invention because what matters is that a layer having a metallic behavior is present in the immediate vicinity of the gate insulator 31.
• each technology particu ⁇ transistor manufacturing MOS die is characterized by the minimum gate length, and the thickness of the grid to obtain dimensions of spacers satisfactory and sufficient protection of the zone under the grid with respect to the implantations carried out for the realization of the source and drain zones.
• the gate width is of the order of 0.3 microns

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Electrodes Of Semiconductors (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)

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• 2005
  • 2005-10-04 TW TW094134627A patent/TW200633216A/zh unknown
  • 2005-10-05 WO PCT/FR2005/050812 patent/WO2006037927A1/fr active Application Filing
  • 2005-10-05 CN CNA2005800338712A patent/CN101061586A/zh active Pending
  • 2005-10-05 EP EP05810641A patent/EP1831929A1/fr not_active Withdrawn
  • 2005-10-05 JP JP2007535216A patent/JP2008516437A/ja active Pending
  • 2005-10-05 US US11/664,853 patent/US20110095381A1/en not_active Abandoned

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