Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
  • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

• the invention relates to the production of new structures for semiconductor components or devices of the MEMS type, and in particular SOI or SOI type.
• MEMS Micro Electro Mechanical Systems in English
• SOI English Silicon On Insulator
• the materials of the SOI type are structures composed of a surface layer 2 made of monocrystalline silicon on an insulating layer 4, generally made of silicon oxide (FIG. 1). These structures are obtained for example by molecular bonding assembly of a plate 6 of surface-oxidized silicon with another silicon wafer.
• This assembly comprises a surface preparation step of the two plates, a contacting step and a heat treatment step.
• this heat treatment is carried out at temperatures between, typically, 900 ° and 125 ° C. for 2 hours.
• the two plates is thinned, leaving a thin semiconductor layer 2 on an insulating layer 4.
• the thinning takes place by various mechanical means, or chemical, or by separation at a fragile layer created for example by ion implantation. For some applications, it is interesting to obtain circuits on a metal ground plane.
• the circuit SOI made in the layer 2 and superficial to the buried layer 4, of small thickness (for example a layer of silicon oxide), is such that the assembly constituted by said circuit and the layer 4 buried either on an electrically conductive layer, or metal ground plane.
• a buried oxide of very small thickness for example 10 nm to 50 nm.
• the circuits can be transferred to plates containing a metal ground plane.
• One possibility is to transfer the layer containing the circuits to a layer with a metal deposit by the double transfer techniques using molecular adhesion.
• the invention firstly relates to a method for producing a semiconductor structure, comprising: a) producing at least all or part of a component or a circuit, in or on the surface layer of a substrate, comprising said surface layer, a layer buried beneath the surface layer, and an underlying layer serving as a first support, b) a transfer of this substrate onto a handle substrate and then an elimination of the first support, c) forming a ground plane layer on the buried layer, d) forming, on the ground plane layer, a bonding layer, e) a transfer of the assembly to a second support and an elimination of the handle substrate.
• the bonding layer may be electrically insulating, for example selected from SiO 2, Si 3 N 4, SiON or other. It may also be electrically conductive, for example doped Si or doped polycrystalline Si.
• the invention also relates to a method for producing a semiconductor structure, comprising: a) producing at least all or part of a component or a circuit, in or on the surface layer of a substrate , comprising said surface layer, a layer buried beneath the surface layer, and an underlying layer serving as a first support, b) a transfer of this substrate on a handle substrate and then an elimination of the first support, c) the formation of a layer of highly doped semiconductor material, forming both a bonding layer and electrically conductive layer or ground plane on the buried layer, d) a transfer of the assembly to a second support and an elimination of the handle substrate.
• a circuit is produced on a substrate comprising a surface layer, a buried layer, for example silicon oxide, thick or thin, under the surface layer, and a first support.
• This assembly is then assembled on a plate, for example in semiconductor, which serves as a handle.
• This thinning step may be carried out for example by mechanical thinning and / or chemical etching.
• the ground plane layer may be of a metallic material or a highly doped semiconductor material. Its lateral extension can be limited, and can therefore only cover part of the buried layer.
• the ground plane layer also forms a bonding layer.
• the transfer step may be carried out by molecular adhesion or by bonding with an adhesive substance such as an adhesive, a resin, etc.
• a step of thinning the buried layer of the substrate can be carried out, for example by mechanical and / or chemical means
• the surface layer may be of semiconductor material, for example silicon or germanium, or a III-V semiconductor, II-VI, or a compound semiconductor, for example SiGe.
• the initial substrate may be an SOI substrate.
• the component or circuit may be an electronic or optoelectronic type component or MEMS.
• the invention also relates to a semiconductor device comprising a surface layer of circuits or components, a first layer buried in a dielectric material, a second buried layer forming a conductive layer or ground plane, of possibly limited lateral extension, a third buried layer of glue, and a substrate.
• the ground plane layer may be of a highly doped metal or semiconductor material.
• the invention also relates to a semiconductor device comprising a surface layer of circuits or components, a first layer buried in a dielectric material, a second layer buried in a highly doped semiconductor material, forming both a bonding layer and a layer. electrically conductive, or ground plane, and a substrate.
• the surface layer in which the circuits are formed may be in semiconductor, for example in silicon or germanium, or in a semiconductor III-V, II-VI, or in a semi-conductor. compound conductor, for example in SiGe.
• the first buried layer may be an electrical insulator, such as silicon dioxide, or thermal silica or a multilayer for example SiO2 / Si3N4 type.
• Figure 1 shows an SOI structure.
• Figure 2 shows a component according to
• Figures 3A-3E show steps of a method according to the invention.
• Figure 4 shows another component according to the invention.
• FIG. 2 represents a device or component according to the invention, comprising, on a substrate 30, a bonding layer 12, a ground plane layer 14, a dielectric layer 4 and finally a layer 2 of circuits.
• the 2-layer layer assembly 4 forms an "SOI circuit".
• the layer 14 may be metallic or of semiconductor material (for example in silicon) which is heavily doped. This layer can be only local and not uniform or continuous, for example it can be under some components only.
• the bonding layer 12 may be electrically insulating; it can be an oxide, for example SiO2. It can also be chosen from, for example, Si3N4, SiON or other.
• It can also be electrically conductive, being then for example in If doped amorphous or doped polycrystalline Si, or even doped Si.
• the bonding interface may be located between the bonding layer 12 and the support substrate 30. This interface may also, in the case where a bonding layer is deposited on both the ground plane and the support 30, be located in the middle of the bonding layer itself.
• the layer 4 has a thickness of, for example, between 10 nm and 500 nm or 1 ⁇ m, and the layer 2 has a thickness of between 10 nm and 1 ⁇ m or 10 ⁇ m.
• the metal layer may have a thickness between 100 nm and 500 nm, and the bonding layer a thickness between 500 nm and a few microns, for example 5 microns. All these ranges of thicknesses may vary outside the ranges indicated.
• ground plane side 14 it may be advantageous to carry out a planarization before the gluing step or before the deposition of the conductive layer.
• An SOI plate initially comprises, as illustrated in Figure 1, a support 6, a buried layer 4 and a surface layer 2.
• the latter is for example silicon, but it can also be in germanium, or in a semiconductor III -IV, or II-VI, or a compound semiconductor, such as SiGe for example.
• circuits 18 or all or part of a component are produced in layer 2.
• the assembly is then assembled (FIG. 3B), by the side of the layer 2 of circuits, with a handle substrate 20, by bonding for example by molecular adhesion.
• Such bonding has the advantage of being compatible with thermal processes at higher or lower temperatures, unlike adhesives with adhesives or resins.
• the support 6 can then be removed for example by mechanical thinning, and / or mechanical-chemical, and / or chemical ( Figure 3C).
• the thickness of the buried layer 4 can then be adapted to the desired thickness. This step makes it possible to control the effect of the conductive layer through the dielectric layer 4.
• Thinning of this layer 4 is preferably carried out by CMP (mechanical-chemical polishing) or chemical etching (wet or dry etching) to a low thickness, for example from 10 nm to 50 nm.
• CMP mechanical-chemical polishing
• chemical etching wet or dry etching
• a conductive layer 14 is formed (FIG. 3D), for example by chemical vapor deposition.
• This layer may be for example copper, or aluminum or doped silicon, or tungsten silicide (WSi2).
• This layer can cover the entire surface or be located according to patterns for the purposes of the application; we will then use lithography and etching techniques to delimit the areas with this conductive layer and the areas without this conductive layer.
• the conductive layer may be only local, for example under certain components.
• this conductive layer 14 another layer 12 of a material to facilitate bonding to a substrate, in particular semi ⁇ conductive type, may be deposited or formed.
• This bonding layer 12 is, for example, a silicon oxide layer or an amorphous or polycrystalline silicon layer.
• the contact of the conductive layer can be taken by the front face or the rear face of the structure. In the case of a conductive bonding layer, the contact can be made by the rear face.
• This bonding layer 12 may be a thick layer, for example greater than 100 nm, which makes it possible to obtain a good bonding quality.
• the handle plate 20 which was used as a manipulator for thinning the initial plate can be eliminated, for example by mechanical and / or chemical thinning or by taking off at the bonding interface between front face and handle.
• the handle plate 20 which was used as a manipulator for thinning the initial plate can be eliminated, for example by mechanical and / or chemical thinning or by taking off at the bonding interface between front face and handle.
• the whole is based on a layer 12 which has ensured the bonding of the structure on a new support 30.
• FIG. 4 represents another component according to the invention, comprising, on a substrate 30, a layer 34 made of highly doped semiconductor material, forming a ground plane and a bonding layer, a layer 4 of dielectric and finally a layer 2 of circuits.
• the doping of the layer 34 allows the resistivity of this layer to be at most of the order of a few m ⁇ / cm 2 , for example at most of the order of 10 m ⁇ / cm 2 or 100 m ⁇ / cm 2 .
• This is for example a doped polysilicon layer.
• the layer 2 - layer 4 assembly forms an "SOI type circuit".

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Manufacturing & Machinery (AREA)
• Element Separation (AREA)
• Thin Film Transistor (AREA)
• Semiconductor Integrated Circuits (AREA)

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• 2004
  • 2004-12-24 FR FR0453229A patent/FR2880189B1/fr active Active
• 2005
  • 2005-12-22 US US11/793,863 patent/US8298915B2/en active Active
  • 2005-12-22 KR KR1020077013647A patent/KR20070086316A/ko active Search and Examination
  • 2005-12-22 WO PCT/FR2005/051139 patent/WO2006070167A1/fr active Application Filing
  • 2005-12-22 JP JP2007547604A patent/JP2008526009A/ja active Pending
  • 2005-12-22 CN CNB2005800443969A patent/CN100543962C/zh active Active
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