EP1759321A4 - Procede et appareil pour la conception de topologies de circuits integres - Google Patents

Procede et appareil pour la conception de topologies de circuits integres

Info

Publication number
EP1759321A4
EP1759321A4 EP05740549A EP05740549A EP1759321A4 EP 1759321 A4 EP1759321 A4 EP 1759321A4 EP 05740549 A EP05740549 A EP 05740549A EP 05740549 A EP05740549 A EP 05740549A EP 1759321 A4 EP1759321 A4 EP 1759321A4
Authority
EP
European Patent Office
Prior art keywords
integrated circuit
circuit layouts
designing integrated
designing
layouts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05740549A
Other languages
German (de)
English (en)
Other versions
EP1759321A2 (fr
Inventor
Louis K Scheffer
Steven Teig
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cadence Design Systems Inc
Original Assignee
Cadence Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/836,582 external-priority patent/US7254798B2/en
Priority claimed from US10/836,581 external-priority patent/US7082588B2/en
Application filed by Cadence Design Systems Inc filed Critical Cadence Design Systems Inc
Publication of EP1759321A2 publication Critical patent/EP1759321A2/fr
Publication of EP1759321A4 publication Critical patent/EP1759321A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
EP05740549A 2004-05-01 2005-04-29 Procede et appareil pour la conception de topologies de circuits integres Withdrawn EP1759321A4 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/836,582 US7254798B2 (en) 2004-05-01 2004-05-01 Method and apparatus for designing integrated circuit layouts
US10/836,581 US7082588B2 (en) 2004-05-01 2004-05-01 Method and apparatus for designing integrated circuit layouts
PCT/US2005/015024 WO2005109257A2 (fr) 2004-05-01 2005-04-29 Procede et appareil pour la conception de topologies de circuits integres

Publications (2)

Publication Number Publication Date
EP1759321A2 EP1759321A2 (fr) 2007-03-07
EP1759321A4 true EP1759321A4 (fr) 2009-10-28

Family

ID=35320879

Family Applications (2)

Application Number Title Priority Date Filing Date
EP05740554A Withdrawn EP1759322A4 (fr) 2004-05-01 2005-04-29 Procedes et dispositif pour la conception de topologies de circuits integres
EP05740549A Withdrawn EP1759321A4 (fr) 2004-05-01 2005-04-29 Procede et appareil pour la conception de topologies de circuits integres

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP05740554A Withdrawn EP1759322A4 (fr) 2004-05-01 2005-04-29 Procedes et dispositif pour la conception de topologies de circuits integres

Country Status (3)

Country Link
EP (2) EP1759322A4 (fr)
JP (2) JP5147391B2 (fr)
WO (2) WO2005109256A2 (fr)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
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US7011600B2 (en) 2003-02-28 2006-03-14 Fallbrook Technologies Inc. Continuously variable transmission
US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
EP1759322A4 (fr) * 2004-05-01 2008-03-12 Cadence Design Systems Inc Procedes et dispositif pour la conception de topologies de circuits integres
JP4974896B2 (ja) 2004-10-05 2012-07-11 フォールブルック テクノロジーズ インコーポレイテッド 連続可変変速機
CN102425649B (zh) 2005-10-28 2014-09-24 福博科知识产权有限责任公司 电动驱动器
US20070155567A1 (en) 2005-11-22 2007-07-05 Fallbrook Technologies Inc. Continuously variable transmission
CN102226464B (zh) 2005-12-09 2013-04-17 福博科技术公司 一种用于变速器的轴向力产生机构
EP1811202A1 (fr) 2005-12-30 2007-07-25 Fallbrook Technologies, Inc. Transmission à variation continue
CN102269056B (zh) 2006-06-26 2013-10-23 福博科技术公司 无级变速器
PL2089642T3 (pl) 2006-11-08 2013-09-30 Fallbrook Ip Co Llc Generator siły zaciskającej
US8738255B2 (en) 2007-02-01 2014-05-27 Fallbrook Intellectual Property Company Llc Systems and methods for control of transmission and/or prime mover
WO2008100792A1 (fr) 2007-02-12 2008-08-21 Fallbrook Technologies Inc. Transmissions variables en continu et procédés destinés à celles-ci
EP2700843A3 (fr) 2007-02-16 2017-11-08 Fallbrook Intellectual Property Company LLC Transmissions infiniment variables, transmissions variables en continu, procédés, ensembles, sous-ensembles, et composants de celles-ci
JP5591686B2 (ja) 2007-04-24 2014-09-17 フォールブルック インテレクチュアル プロパティー カンパニー エルエルシー 電気牽引駆動装置
US8641577B2 (en) 2007-06-11 2014-02-04 Fallbrook Intellectual Property Company Llc Continuously variable transmission
CA2983530A1 (fr) 2007-07-05 2009-01-08 Fallbrook Intellectual Property Company, Llc Transmission a variation continue
CN101861482B (zh) 2007-11-16 2014-05-07 福博科知识产权有限责任公司 用于变速传动装置的控制器
JP5783723B2 (ja) 2007-12-21 2015-09-24 フォールブルック インテレクチュアル プロパティー カンパニー エルエルシー 自動変速機及びその方法
US7861196B2 (en) 2008-01-31 2010-12-28 Cadence Design Systems, Inc. System and method for multi-exposure pattern decomposition
US8317651B2 (en) 2008-05-07 2012-11-27 Fallbrook Intellectual Property Company Llc Assemblies and methods for clamping force generation
CN102084155B (zh) 2008-06-23 2014-06-11 福博科知识产权有限责任公司 无级变速器
US8818661B2 (en) 2008-08-05 2014-08-26 Fallbrook Intellectual Property Company Llc Methods for control of transmission and prime mover
US8069423B2 (en) 2008-08-11 2011-11-29 Cadence Design Systems, Inc. System and method for model based multi-patterning optimization
US8469856B2 (en) 2008-08-26 2013-06-25 Fallbrook Intellectual Property Company Llc Continuously variable transmission
US8167759B2 (en) 2008-10-14 2012-05-01 Fallbrook Technologies Inc. Continuously variable transmission
US8209656B1 (en) 2008-10-14 2012-06-26 Cadence Design Systems, Inc. Pattern decomposition method
RU2011140072A (ru) 2009-04-16 2013-05-27 Фоллбрук Текнолоджиз Инк. (Сша/Сша) Узел статора и механизм переключения передач для бесступенчатой коробки передач
US8512195B2 (en) 2010-03-03 2013-08-20 Fallbrook Intellectual Property Company Llc Infinitely variable transmissions, continuously variable transmissions, methods, assemblies, subassemblies, and components therefor
US8888643B2 (en) 2010-11-10 2014-11-18 Fallbrook Intellectual Property Company Llc Continuously variable transmission
AU2012240435B2 (en) 2011-04-04 2016-04-28 Fallbrook Intellectual Property Company Llc Auxiliary power unit having a continuously variable transmission
US8386974B2 (en) 2011-04-14 2013-02-26 Synopsys, Inc. Accelerating coverage convergence using symbolic properties
US8443316B1 (en) 2011-11-09 2013-05-14 Synopsys, Inc. Accelerating coverage convergence and debug using symbolic properties and local multi-path analysis
US10047861B2 (en) 2016-01-15 2018-08-14 Fallbrook Intellectual Property Company Llc Systems and methods for controlling rollback in continuously variable transmissions
US10023266B2 (en) 2016-05-11 2018-07-17 Fallbrook Intellectual Property Company Llc Systems and methods for automatic configuration and automatic calibration of continuously variable transmissions and bicycles having continuously variable transmissions
US11215268B2 (en) 2018-11-06 2022-01-04 Fallbrook Intellectual Property Company Llc Continuously variable transmissions, synchronous shifting, twin countershafts and methods for control of same
WO2020176392A1 (fr) 2019-02-26 2020-09-03 Fallbrook Intellectual Property Company Llc Entraînements variables réversibles et systèmes et procédés de commande dans des directions avant et arrière
US11501052B1 (en) 2021-05-27 2022-11-15 Taiwan Semiconductor Manufacturing Company, Ltd Conductor scheme selection and track planning for mixed-diagonal-Manhattan routing

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030229412A1 (en) * 2002-06-07 2003-12-11 David White Electronic design for integrated circuits based on process related variations
US20040058255A1 (en) * 2002-09-24 2004-03-25 Scott Jessen Substrate topography compensation at mask design: 3D OPC topography anchored

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JPH0844038A (ja) * 1994-08-03 1996-02-16 Matsushita Electron Corp マスターマスク作成装置及び半導体装置の製造方法
US5587923A (en) * 1994-09-07 1996-12-24 Lsi Logic Corporation Method for estimating routability and congestion in a cell placement for integrated circuit chip
US5723233A (en) * 1996-02-27 1998-03-03 Lsi Logic Corporation Optical proximity correction method and apparatus
JP2950280B2 (ja) * 1997-03-31 1999-09-20 日本電気株式会社 電子線の描画方法
JP3241010B2 (ja) * 1998-11-18 2001-12-25 日本電気株式会社 半導体製造プロセスの光近接効果補正方法
JP2002148779A (ja) * 2000-11-07 2002-05-22 Toshiba Corp マスクパターン補正方法、フォトマスク及びマスクパターン補正方法プログラムを格納したコンピュータ読み取り可能な記録媒体
US6574782B1 (en) * 2000-11-15 2003-06-03 International Business Machines Corporation Decoupled capacitance calculator for orthogonal wiring patterns
US6578190B2 (en) * 2001-01-11 2003-06-10 International Business Machines Corporation Process window based optical proximity correction of lithographic images
JP4187947B2 (ja) * 2001-04-26 2008-11-26 株式会社東芝 パターン補正方法、パターン補正装置、およびパターン補正プログラムを記録した記録媒体
JP4592240B2 (ja) * 2001-09-29 2010-12-01 株式会社東芝 マスクパターン作成方法及び半導体装置の製造方法
JP3609810B2 (ja) * 2002-09-18 2005-01-12 株式会社東芝 マスクパターン作成方法及び半導体装置の製造方法
JP3686367B2 (ja) * 2001-11-15 2005-08-24 株式会社ルネサステクノロジ パターン形成方法および半導体装置の製造方法
JP3615182B2 (ja) * 2001-11-26 2005-01-26 株式会社東芝 光近接効果補正方法及び光近接効果補正システム
JP2004037827A (ja) * 2002-07-03 2004-02-05 Sony Corp 設計パターンの検証方法および設計パターンの補正方法
JP2004046880A (ja) * 2003-07-18 2004-02-12 Matsushita Electric Ind Co Ltd 回路パラメータ抽出装置
EP1759322A4 (fr) * 2004-05-01 2008-03-12 Cadence Design Systems Inc Procedes et dispositif pour la conception de topologies de circuits integres

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030229412A1 (en) * 2002-06-07 2003-12-11 David White Electronic design for integrated circuits based on process related variations
US20040058255A1 (en) * 2002-09-24 2004-03-25 Scott Jessen Substrate topography compensation at mask design: 3D OPC topography anchored

Also Published As

Publication number Publication date
WO2005109257A3 (fr) 2005-12-15
EP1759322A4 (fr) 2008-03-12
JP2007538272A (ja) 2007-12-27
WO2005109256A2 (fr) 2005-11-17
JP2007535715A (ja) 2007-12-06
EP1759321A2 (fr) 2007-03-07
WO2005109257A2 (fr) 2005-11-17
WO2005109256A3 (fr) 2006-05-04
JP5147391B2 (ja) 2013-02-20
EP1759322A2 (fr) 2007-03-07

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