EP1668694A1 - Dispositif a semi-conducteurs, son procede de fabrication, etiquette d'identification et support d'informations - Google Patents

Dispositif a semi-conducteurs, son procede de fabrication, etiquette d'identification et support d'informations

Info

Publication number
EP1668694A1
EP1668694A1 EP04769931A EP04769931A EP1668694A1 EP 1668694 A1 EP1668694 A1 EP 1668694A1 EP 04769931 A EP04769931 A EP 04769931A EP 04769931 A EP04769931 A EP 04769931A EP 1668694 A1 EP1668694 A1 EP 1668694A1
Authority
EP
European Patent Office
Prior art keywords
layer
substrate
semiconductor
semiconductor device
present
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04769931A
Other languages
German (de)
English (en)
Inventor
Ronald Dekker
Theodorus M. Michielsen
Antoon M. H. Tombeur
Johann-Heinrich Fock
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Intellectual Property and Standards GmbH
Koninklijke Philips NV
Original Assignee
Philips Intellectual Property and Standards GmbH
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Intellectual Property and Standards GmbH, Koninklijke Philips Electronics NV filed Critical Philips Intellectual Property and Standards GmbH
Priority to EP04769931A priority Critical patent/EP1668694A1/fr
Publication of EP1668694A1 publication Critical patent/EP1668694A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Definitions

  • the invention relates to a semiconductor device having a first and an opposite second side, comprising: a substrate comprising a semiconductor layer and an electrically insulating layer and being present on the first side of the device; - an integrated circuit provided with a plurality of semiconductor elements, which are defined in or on the semiconductor layer and are interconnected according to a desired pattern in an interconnect structure; a first contact face that is present on the first side of the device, and a second contact face that is present on the second side of the device, and is connected to the interconnect structure.
  • the invention also relates to a method of manufacturing such a semiconductor device.
  • the invention further relates to an identification label and an information carrier comprising such a semiconductor device.
  • Such a semiconductor device is known from WO-A 02/075647.
  • the known device is an integrated circuit that is provided on its opposite sides with electrically conductive contact faces.
  • the integrated circuit is - according to conventional technology - defined in a silicon substrate layer, on surface of which an electrically insulating layer is present.
  • This insulating layer is generally a thermal oxide layer.
  • This object is achieved in that: - an electrically insulating support layer is present, which covers on the second side the integrated circuits and extends laterally around the integrated circuit in a non-active area, through which support layer a vertical interconnect is present to connect the second contact face with the interconnect structure; the semiconductor layer is laterally partially removed so as to be absent in the non-active area, and the first contact face is connected to the interconnect structure through a vertical interconnect.
  • the integrated circuit in the device of the invention is in fact an island within an encapsulation, that is electrically insulating at least for the larger part and except for the vertical interconnects. Due to this island-like structure and the vertical interconnects, there is no risk of the semiconductor substrate or any interconnects on a side face coming into contact with any metal foil. Then any uncontrollable and undesired effects giving rise to degraded functioning or even malfunctioning are prevented in this way.
  • the non-active area of the device is an area laterally around an active area in which the integrated circuit is defined. The non-active area and the active area may be complementary to fill the complete surface area of the device. However, it is not excluded that there is an intermediate area between the active and the non-active area.
  • the non-active area is then an edge area.
  • the object of the invention to prevent any short- circuitry during lamination is achieved. It is an advantage of the device of the invention, that the thickness of the substrate can be reduced without imparing the stability of the device.
  • the support layer take over the function of support from the semiconductor substrate. As the support layer can be chosen freely, this allows the device as a whole to be bendable or even completely flexible. It is another advantage, as a consequence of the thinning, that the device can be completely or largely transparent. This feature is advantageous in view of the possible security functions.
  • the vertical interconnect to the first contact face is present in the non-active area, the first contact face being defined in an electrically conducting layer.
  • the electrically insulating layer is laterally substantially continuous so as to be present in the non-active area.
  • this insulating layer extends through the complete device from the one side face to the opposite side face.
  • Such a continuous presence is not only beneficial to the stability of the device; it is also an effective barrier layer - particularly an etch stop layer - during processing.
  • the effectiveness is large, in that it can be used as such both during the processing from the first side, and from the second side.
  • the insulating layer which is or comprises oxide by preference, allows to establish adequate adhesion with the organic layers.
  • the semiconductor device of the present invention can be provided in at least two technologies. In the first technology, use is made of a monocrystalline semiconductor substrate, on the second side of which the elements are defined and a thermal oxide layer is provided.
  • the active area of the semiconductor elements is protected against the etching means (wet or dry) by a hard mask.
  • the device is provided with a mesa on its first side.
  • a substrate with a buried oxide layer A well-known example of such a substrate is a silicon-on-insulator (SOI) substrate.
  • SOI silicon-on-insulator
  • the use of an SOI substrate allows the resulting device to be not just bendable, but completely flexible. This is particularly advantageous for identification labels, in which the presence of an integrated circuit is preferably kept secret.
  • an electrically insulating layer is present on the second side of the substrate, and the vertical interconnect extends through it.
  • a passivation layer can be present, for instance a nitride and particularly a nitride provided with an LPCVD. This layer will prevent the diffusion of impurities, including water, from the environment to the devices after the removal of the substrate.
  • a passivation layer can be present, for instance a nitride and particularly a nitride provided with an LPCVD. This layer will prevent the diffusion of impurities, including water, from the environment to the devices after the removal of the substrate.
  • PHNL031150 As the base layer of this SOI substrate is meant as PHNL031150
  • the interconnect structure is provided with a first and a second via pad, which are present in the non-active area, and at which pads the first and the second vertical interconnects respectively are present. Due to the provision of the vertical interconnects outside the active area of the semiconductor elements, chemical contamination and parasitic electrical interaction can be prevented or at least considerably reduced. Moreover, any cracking as a result of pressure differences or differences in thermal expansion is more easily prevented if the vertical interconnects are constructed outside the active area, that is in practice a multilayer stack of a number of thin and vulnerable layers. Particularly the second via pad has large-scale dimensions as compared to other patterns in the integrated circuit.
  • the via pads may be for instance about 10 by 10 micrometers or larger, as a consequence of the thickness of the support layer and an etching step through this support layer. It is highly preferred that the via pads are present on the electrically insulating layer that is part of the substrate. This presence is advantageous for the stability.
  • the via pads and the vertical interconnect comprise a ductile material, such as Al.
  • the electrically insulating layer comprises an oxide layer by preference.
  • the support layer preferably comprises an organic material. Such a material can be chosen to be photosensitive. It can furthermore have a large thickness, for instance in the range from 5 to 20 microns, so as to provide the required support, but is nevertheless not detrimental to the flexibility. It may also have a low dielectric constant.
  • the dielectric constant can be amended and increased to desire.
  • the resulting parasitic capacitor can be used as a tuning capacitor, which is particularly suitable in combination with a dipolar antenna.
  • a support layer is present on the first side of the device as well.
  • the device is therewith encapsulated on both sides in such a support layer. This has a considerable advantage in view of the bending properties.
  • the device has turned out to be more sensitive to compressive stress than to elastic stress.
  • the compressive stress may lead to microcracks in the semiconductor layer and/or the interconnect structure.
  • the support layer thereto has sufficient elasticity.
  • the device of the invention can be suitably integrated in an identification label further incorporating an antenna for wireless transmission.
  • identification labels for use in logistics or in security of products
  • such an identification label can be a security paper, and documents incorporating such paper, such as bank notes, passports and other tickets.
  • an integrated circuit in a bank note to the security thread which is present in the bank note.
  • the security thread may be used as a dipole antenna with any modifications needed.
  • the device of the invention is suited very well to this purpose.
  • the parasitic capacitors between the first and second contact faces can be designed to function as a tuning capacitor for the desired frequency.
  • the device of the invention can be integrated in other apparatus, including an information carrier, such as a DVD or a CD, or even a smart card.
  • the coupling between the device of the invention and the antenna may be realized both as a DC coupling, for instance with anisotropically conducting glue, but also capacitively, in that the contact faces form capacitor electrodes together with the antenna.
  • the semiconductor device is provided with glue before assembly.
  • a particularly suitable glue is that type of which the adhesive force increases on heating. It is a second object of the invention to provide a method of manufacturing a semiconductor device of the invention in a robust manner.
  • the method comprises the steps of: providing a substrate with a semiconductor layer and an electrically insulating layer, an integrated circuit provided with a plurality of semiconductor elements being defined in an active area, the semiconductor elements being mutually interconnected according to a desired pattern in an interconnect structure, which interconnect structure comprises a first and a second via pad, which via pads are present in an area that is laterally substantially outside the active area; applying a support layer of an electrically insulating material on the second side and providing a contact window in the support layer corresponding to the second via pad; - applying electrically conductive material in a desired pattern on the second side, therewith providing a second contact face and a second vertical interconnect between the said contact face and the second via pad; attaching the substrate on its second side to a carrier with removable attaching means; PHNL031150
  • the substrate further comprises a base layer and the semiconductor layer, which base layer is removed in the thinning step and in and on a surface of which semiconductor layer the semiconductor elements are defined.
  • the first vertical interconnect can be provided as part of the integrated circuit or after the finalization of the thinning process. It is preferred to provide this first vertical interconnect before the processing, e.g. as part of the integrated circuit. This has the advantage that for none of the described method steps a high resolution is required. Such low-resolution patterning can be done in assembly factories, that are cheaper in use than semiconductor wafer factories. If desired, the patterned support layer can be provided as well before transfer of the device to an assembly factory. It is furthermore advantageous that a plurality of semiconductor devices is provided in a single operation, as is well known in the art. In order to improve the removal of the devices from the carrier, it is preferred that at the edges of the wafer the support layer is removed and an adhesive is applied instead.
  • Figs. 1 to 7 show cross-sectional views of several steps in a first embodiment of the method
  • Fig. 8 shows a diagrammatical cross-sectional view of the semiconductor device in the first embodiment
  • FIGs. 9-14 show cross-sectional views of several steps in a second embodiment of the method;
  • Fig. 15 shows a diagrammatical cross-sectional view of the semiconductor device in the second embodiment;
  • Fig. 16 shows a detail of Fig. 15;
  • Fig. 17 shows a diagrammatical cross-sectional view of integration of the semiconductor device in the identification label.
  • Figs. 1 to 7 relate to a first embodiment of the method of manufacturing a semiconductor device according to the invention.
  • the resulting device is shown in Fig. 8.
  • the buried layer 11 is typically an oxide layer, but includes preferably a nitride layer for improved chemical protection of the integrated circuit 20, which is provided in and on the semiconductor layer of a semiconductor material that is generally grown epitaxially.
  • a base layer is present on the opposite side of the buried layer 11.
  • the semiconductor material of both the base layer and the semiconductor layer in the substrate 10 is silicon in this case.
  • the integrated circuit 20 comprises a plurality of semiconductor elements (non-shown) in an active area A.
  • the elements are mutually interconnected according to a desired pattern in an interconnect structure (not specifically shown).
  • the structure comprises a first via pad 21 and a second via pad 22, which pads 21,22 are present in an area B that is laterally substantially outside the active area A.
  • the via pads are preferably provided in a layer of aluminum in view of its ductility.
  • Cu, Ni, Ag or a conductive paste could be used alternatively.
  • Fig. 2 shows the result after a support layer 12 of an electrically insulating material has been applied on the second side 2. In this case use is made of polyimide in a typical thickness of 10 to 20 ⁇ m.
  • the surface Before applying the polyimide, for instance by spincoating, the surface has been cleaned and a primer layer has been provided for improved adhesion. After the application of the polyimide, it is heated first to 125 °C and thereafter to 200 °C. Then a photoresist is applied, exposed to a suitable source of radiation and developed. The development includes the structuring of the polyimide layer, so as to create contact windows 13 that expose the second via pads 22.
  • the support layer 12 of polyimide is PHNL031150
  • Fig. 3 shows the result, after an electrically conducting layer has been provided on the second side 2 of the substrate 10.
  • the electrically conducting layer is applied in a pattern which comprises a second contact face 31 and a second vertical interconnect 32 between this contact face 31 and the second via pad 22.
  • the electrically conductive layer comprises Al. This, in combination with the use of Al for the second via pad 22, provides a good electrical connection and has the required flexibility to withstand any bending of the foil and any forces during lamination of the device into a label.
  • FIG. 4 shows the substrate 10 after it has been attached to a carrier 40 with removable attaching means 41.
  • This means 41 is in this case a layer of adhesive, which is releasable upon irradiation with UV-radiation.
  • the carrier 40 is transparent, and in this example a layer of glass. It is preferred to apply a layer of an oxide on the support layer and the second contact face 31 and the interconnect 32. The advantage hereof is again the yield improvement. If desired, this layer can be provided according to a desired pattern.
  • the edge area C is primered. The result hereof is a good adhesion between adhesive 41 and the support layer 12 in the edge area C, and a substantially weak adhesion in other areas.
  • FIG. 5 shows the result after the substrate 10 has been thinned from the first side. This thinning is usually achieved by grinding and continued etching with KOH. The thinning is continued until the base layer of the substrate 10 is removed.
  • the buried layer 11 acts herein as the etch stop layer.
  • Fig. 6 shows the result after patterning the buried oxide layer has been patterned so as to create contact windows 14.
  • Fig. 7 shows the result after applying a further metal layer, by which a first vertical interconnect 34 and a first contact face 33 are created.
  • the further metal layer comprises for instance Al or Cu. In the case of Cu, a barrier layer may be applied so as to prevent any contamination of the semiconductor layer. After removal of the carrier 40 the individual devices 100 can be separated.
  • the device 100 comprises a first contact face 33 and a second contact face 31, as well as an integrated circuit 20.
  • the integrated circuit is provided with vertical interconnects 32, 34 for establishing connections to the contact faces 31, 33.
  • the device 100 is provided with an active area A and a non-active area B. It is supported by a support layer 12.
  • the support layer 12 herein has atypical thickness of about 5-15 ⁇ m, preferably about 10 ⁇ m, and the contact faces 31,33 have a thickness of about 0.2-1.5 ⁇ m, preferably about 1.0 ⁇ m.
  • Figs. 9 to 14 show a second embodiment of the method of the invention. This method comprises a number of steps which are equal to those in the first method.
  • the substrate 10 is a substrate of monocrystalline or polycrystalline silicon without any buried oxide layer.
  • the oxide layer 11 is present on the second side of the substrate 10 and is used at the same time as gate oxide layer of the semiconductor elements within the integrated circuit 20.
  • the semiconductor elements have been defined on the surface of the substrate 10 in known manner, e.g. by implanted dopants of a selected material in a required concentration.
  • Also implanted is a well extending through part of the substrate 10 towards the first side 1.
  • the oxide layer 11 has been patterned and an electrical connection is made. This constitutes a first vertical interconnect 34 to a first contact face to be provided in a later stage of the process.
  • a first via pad 21 and a second via pad 22 are defined. These via pads 21,22 are located outside an active area A, and not necessarily but probably partly in a non-active area B.
  • Fig. 10 shows the result after a flexible support layer 13 has been applied, cured and patterned in a desired manner so as to remove it from an edge area C and so as to create contact windows 13 to the second via pads 22.
  • Fig. 11 shows the result after an electrically conductive material has been applied in a desired pattern on the second side on top of the support layer 12, therewith defining the second contact faces 31 and a vertical interconnect 32 to the second contact pad 22.
  • Fig. 12 shows the result after the structure has been attached to a carrier 40 with an adhesive 41.
  • FIG 13 shows the result after the substrate 10 has been thinned from the first side 1 and an etch mask 33 has been applied.
  • This etch mask is made from an electrically conductive material, and will subsequently function as the first contact face.
  • the contact to the first contact pad 21 is herein made through the well through the substrate 10, which is PHNL031150
  • Fig. 16 shows the substrate 10, an element of the integrated circuit 20 and the vertical interconnect 34, that is formed by the metal trace 34A and the well 34B through the substrate 10.
  • Fig. 14 shows the result after the substrate 10 is etched from the first side, and in this manner a mesa 50 is created.
  • the mesa 50 further defines the non-active area B, which is present outside the mesa, and in which the semiconductor substrate 10 is absent.
  • the via 34 may be present outside the mesa 50.
  • the via 34 is formed in that after the forming of the mesa an electrically conductive layer is provided on the first side 1 of the substrate according to a desired pattern.
  • FIG. 15 shows the resulting semiconductor device 100, having an active area A and a non-active area B. It is to be noticed that in this case there is a further area between the non-active area B and the active area A.
  • the device 100 comprises first and second contact faces 31, 33 and vertical interconnects 32,34 for connecting the faces 31,33 to the integrated circuit 20.
  • Fig. 17 shows a method of integration of the semiconductor device 100 of the invention into an identification label 200.
  • the label 200 is manufactured by laminating a first foil 211 and a second foil 212.
  • the foils are provided on rolls 300, and the laminating process is structured through wheels 310.
  • the foils 211, 212 are each provided with a plurality of conductive patterns 201, 202, which are able to act as an antenna, for instance a dipole antenna.
  • the semiconductor device 100 is provided between the foils.
  • Adhesive may be present on either the semiconductor device 100 or the foils 201,202 so as to improve the attachment.
  • the semiconductor device 100 is provided on the foils without a specific orientation. Due to the absence of the semiconductor substrate 10 in the non-active area B, there is no risk of one of the conductive patterns 201,202 being in electrical contact with both the first contact face and the second contact face of the device, or there being a substantial parasitic capacitance due to the interaction through the semiconductor substrate.
  • the pattern in the foil 201, 202 could further be designed to be a security thread. It is a further advantage of the device of the invention, that the active area hereof is protected against the forces during lamination into the label. In this lamination, the largest forces are exerted in the metal areas, which are the vertical interconnects.
  • the semiconductor device 100 of the invention comprises an integrated circuit 20 and a first and a second contact face 31,33. These are connected with vertical interconnects 32,34 to the integrated circuit 20.
  • This integrated circuit 20 is present in a semiconductor layer of a substrate. This substrate is absent in a non-active area B. This leads to the fact that on the side faces 101 of the device 100 neither conductive material nor parts of the semiconductor substrate are exposed. On lamination of the device between two metallized foils into an identification label, the risk of short-circuitry due to undesired contact on the side face 101 of the device 100, is prevented thereby.

Abstract

Ce dispositif à semi-conducteurs (100) comporte un circuit intégré (20) et une première et une seconde face de contact (31, 33). Lesdites faces sont connectées au circuit intégré (20) via des éléments d'interconnexion verticaux (32, 34). Ce circuit intégré (20) est présent dans une couche semi-conductrice d'un substrat. Le substrat est absent d'une zone non active (B). Pour cette raison, ni le matériau conducteur ni les parties du substrat semi-conducteur ne sont exposées sur les faces latérales (101) du dispositif (100). Lorsque le dispositif est stratifié entre deux feuilles métallisées pour former une étiquette d'identification, le risque d'un court-circuit provoqué par un contact indésirable au niveau de la face latérale (101) du dispositif (100) est ainsi évité.
EP04769931A 2003-09-24 2004-09-02 Dispositif a semi-conducteurs, son procede de fabrication, etiquette d'identification et support d'informations Withdrawn EP1668694A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP04769931A EP1668694A1 (fr) 2003-09-24 2004-09-02 Dispositif a semi-conducteurs, son procede de fabrication, etiquette d'identification et support d'informations

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP03103525 2003-09-24
EP04769931A EP1668694A1 (fr) 2003-09-24 2004-09-02 Dispositif a semi-conducteurs, son procede de fabrication, etiquette d'identification et support d'informations
PCT/IB2004/051676 WO2005029578A1 (fr) 2003-09-24 2004-09-02 Dispositif a semi-conducteurs, son procede de fabrication, etiquette d'identification et support d'informations

Publications (1)

Publication Number Publication Date
EP1668694A1 true EP1668694A1 (fr) 2006-06-14

Family

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Family Applications (1)

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EP04769931A Withdrawn EP1668694A1 (fr) 2003-09-24 2004-09-02 Dispositif a semi-conducteurs, son procede de fabrication, etiquette d'identification et support d'informations

Country Status (5)

Country Link
EP (1) EP1668694A1 (fr)
JP (1) JP2007507101A (fr)
KR (1) KR20060098432A (fr)
CN (1) CN1856875A (fr)
WO (1) WO2005029578A1 (fr)

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