WO2002043145A1 - Dispositifs passifs integres a capacite de substrat parasite reduite - Google Patents

Dispositifs passifs integres a capacite de substrat parasite reduite Download PDF

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Publication number
WO2002043145A1
WO2002043145A1 PCT/US2000/032367 US0032367W WO0243145A1 WO 2002043145 A1 WO2002043145 A1 WO 2002043145A1 US 0032367 W US0032367 W US 0032367W WO 0243145 A1 WO0243145 A1 WO 0243145A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor body
electrical component
metal layer
passive electrical
component structure
Prior art date
Application number
PCT/US2000/032367
Other languages
English (en)
Inventor
Francois Herbert
Original Assignee
Ultrarf, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ultrarf, Inc. filed Critical Ultrarf, Inc.
Priority to PCT/US2000/032367 priority Critical patent/WO2002043145A1/fr
Priority to AU2001219296A priority patent/AU2001219296A1/en
Publication of WO2002043145A1 publication Critical patent/WO2002043145A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates generally to electronic integrated circuits (ICs) and more particularly the invention relates to passive devices such as inductors and capacitors of an IC having reduced parasitic substrate capacitance.
  • the quality, Q, of inductors and capacitors is a strong function of the losses within such devices. Losses can be caused by parasitic series resistances or parasitic shunting capacitances for example.
  • High quality IC inductors and capacitors are required in order to realize on-chip matching elements, narrow-band circuits, filter networks, and transformers, for example.
  • typical integrated inductors and capacitors on silicon substrates have low quality factor due to the parasitic capacitance with the substrate.
  • the typical Q for a silicon substrate is in the range of 3 to 6.
  • IC inductors consist of metal spirals formed on thick oxides and high- resistivity epitaxial silicon substrates.
  • the high dielectric constant of the layers under the spiral inductor result in significant parasitic capacitance.
  • Figs. 1 A and IB which are a section view of a metal spiral inductor 10 formed on a thick field oxide 12 on a high resistivity epitaxial silicon layer 14 and grounded substrate 16.
  • the inductor 10 has parasitic capacitance 18 with the epitaxial layer 14 and substrate 16.
  • Prior art structures for increasing the quality of inductive devices in an IC include etching the silicon substrate under the capacitive structures and thereby forming a low dielectric constant air gap between the capacitive devices and the substrate. See for example Chang et al. 'Large Suspended Inductors on Silicon and Their Use in a 2- ⁇ m CMOS RF Amplifier" IEEE Electron Device Letters, vol. 14, No. 5, May 1993; Ribas et al. 'Micromachined Planar Spiral Inductor in Standard GaAs HEMT MMIC
  • the present invention is directed to a process and resulting structure for a passive device having high quality and which is compatible with high temperature standard silicon processing which can be implemented at the beginning, middle, or end of an integrated circuit fabrication process.
  • a passive electrical component structure is fabricated on a major surface of a semiconductor body by forming a field oxide layer on the major surface, at least one patterned metal layer on the field oxide layer which forms the electrical component, and a sealed air-gap formed in the semiconductor body underlying the at least one patterned metal layer.
  • the patterned metal layer can have a generally spiral configuration and function as an inductor, or the at last one patterned metal layer can include a first metal plate spaced from a second metal plate and function as a capacitor.
  • a field silicon oxide layer is formed on a major surface of the semiconductor body with a patterned metal layer formed on the field silicon oxide, either before or after other process steps.
  • a plurality of openings are formed through the field silicon oxide and expose the underlying major surface of the semiconductor body which is then isotropically etched to form an air-gap in a semiconductor body under the field silicon oxide.
  • the plurality openings are then sealed with deposited silicon oxide, hi a process including formation of an active device having a gate electrode on the major surface of the semiconductor substrate, the step of sealing the plurality of openings can include forming gate passivation for the active device.
  • a plurality of air-gaps can be formed in the semiconductor body underlying the field oxide.
  • the semiconductor body includes a silicon substrate and a high resistivity epitaxial layer with the epitaxial layer having the major surface.
  • Figs. 1A, IB are a section view and a schematic of electrically inductors of an integrated circuit in accordance with the prior art.
  • Figs. 2 and Fig. 3 are section views of an inductor and of a capacitor respectively in accordance with embodiments of the invention.
  • Fig. 4A is a top view and Figs. 4B - 4F are side views illustrating steps in fabricating an inductor in accordance with one embodiment of the invention.
  • Fig. 5 is a section view of another embodiment of the invention.
  • Figs. 6A, 6B are a section view and a plan view respectively of another embodiment of the invention.
  • Figs. 7A, 7B are a section view and a ian view of another embodiment of the invention.
  • Figs. 2 and 3 are section views illustrating high quality inductor and capacitors in accordance with embodiments of the invention.
  • a silicon substrate 20 has a high resistivity typically in the range of 10- 100 ohm-cm (the higher values being preferred) epitaxial layer 22 formed thereon with a thick (i.e. 0.2 to 3.0 microns) field oxide 24 formed on the high resistivity epitaxial layer.
  • a sealed air-gap 26 which underlies a metal spiral inductor 28 formed on field oxide 24.
  • the air-gap is greater than one micron in thickness with the air having a dielectric constant of 1 which is more than 11 times lower than the dielectric constant of silicon.
  • the air-gap structure can be formed early or late in the fabrication process in accordance with the invention.
  • Fig. 3 is a section view of a capacitor structure in accordance with an embodiment of the invention.
  • an air-gap 26 is formed between field oxide layer 24 in the high resistivity epitaxial layer 22 on a silicon substrate 20.
  • a lower capacitor electrode 30 is formed on the field oxide 24 and a dielectric such as silicon oxide 32 is then formed over the electrode 30.
  • a top capacitor electrode 34 is formed on dielectric 32 and completes the capacitor structure.
  • a contact 36 is provided through dielectric 32 for contacting the lower electrode 30.
  • Figs. 4A - 4F illustrate steps in fabricating the structure of Fig. 2.
  • Fig. 4 is a plan view illustrating field oxide 24 in which a plurality of openings 40 are etched to expose the underlying epitaxial layer. The openings are shown as rectangles, but other configurations such as circles, for example, can be used for the openings. Thereafter, as shown in this section view of Fig. 4B the epitaxial layer is isotropically etched through the openings to form the beginning of air-gap 26.
  • the field oxide thickness is typically 0.2 to 3.0 micron in thickness, 0.5 to 1.5 micron being preferred, and the silicon undercut openings are etched after the field oxide formation, the silicon undercut opening mask patterning and oxide etch.
  • An optional photoresist mask etch can be employed if an oxide hard mask is preferred.
  • the air-gap 26 is formed using standard processing such as SF6 plasma, SF6 resistive ion etching, SF 6 downstream plasma, SF6+02 RLE or plasma, or downstream SF6+CF4 plasma, and the like.
  • the etch depth can be in the range of 0.5 to greater than 3 micron.
  • a silicon etch rate on the order of 1 micron per minute can be achieved using SF6 in a RLE reactor.
  • the isotropic silicon etching is continued a shown in Fig. 4C to increase the air-gap in the epitaxial layer, as shown.
  • a dielectric such as silicon dioxide is deposited to passivate the interior of the air-gap as shown at 42 and to close the openings through the field oxide.
  • the oxide is typically deposited using low pressure chemical vapor deposition or PECVD equipment.
  • PECVD equipment The deposited oxide thickness under the field oxide and on the bottom of the air-gap can be thin since it is used only to passivate the surface.
  • a thermal oxidation process can be employed after the undercut etch in order to passivate the surface.
  • Fig. 4E the dielectric deposition is continued to planarize the surface as shown at 44 and an optional etch back (RLE or CMP) can be utilized for further planarization of the surface.
  • RLE or CMP etch back
  • metalization is deposited and patterned to form the inductive spiral 46 and complete fabrication of the passive device.
  • a capacitor lower electrode can be formed followed by dielectric formation and an upper capacitor electrode, as shown in Fig. 3.
  • Fig. 5 is an alternative embodiment which can be used in a standard RF LDMOS, CMOS, bipolar or BiCMOS process, in which the air-gap is formed after active device formation but before contact formation.
  • the silicon undercut openings are etched after the formation of polycide gate 50 of an active device with the gate passivation used to passivate the air-gap and close the openings. Thereafter the device is completed as shown in Fig. 4F.
  • Figs. 6A, 6B are a section view and plan view of another embodiment as applied to any bipolar LDMOS, or CMOS or BiCMOS process.
  • the air-gap is formed after metalization and later in the process.
  • the silicon undercut openings are etched after metal patterning with the openings patterned between metal lines 60 as shown in the plan view of Fig. 6B.
  • the air-gap can be segmented in order to maintain the structural rigidity of the structure.
  • Figs. 7A, 7B illustrate a section view and a plan view respectively of such a segmented structure.
  • three air-gaps 70 are formed in epitaxial layer 22 through air-gaps 72 in the field oxide 24 as shown in Fig. 7B.
  • Fig. 7 A shows the three separate air-gaps after the complete silicon etch but before filling of the undercut holes 72 with oxide.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention porte sur une structure de composant électrique passive comprenant un corps à semi-conducteur (26) à entrefer étanche (26) formé dans le corps à semi-conducteur (20) situé sous une couche métallique (46) configurée. Le procédé de formation d'inducteurs et de condensateurs de haute qualité dans des circuits intégrés à semi-conducteurs utilise un ou plusieurs entrefers étanches (26) dans un substrat de support positionné sous les dispositifs passifs. Ce processus est compatible avec le traitement classique du silicium et peut être mis en oeuvre dans un traitement à haute température, au début, au milieu ou à la fin d'un processus de fabrication de circuit intégré. Un entrefer d'un micromètre situé dans une couche épitaxiale à haute résistivité a pour résultat une capacité parasite équivalente à un oxyde de silicium de 3.9 micromètres d'épaisseur ou une couche d'appauvrissement de 11 micromètres d'épaisseur dans du silicium.
PCT/US2000/032367 2000-11-27 2000-11-27 Dispositifs passifs integres a capacite de substrat parasite reduite WO2002043145A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/US2000/032367 WO2002043145A1 (fr) 2000-11-27 2000-11-27 Dispositifs passifs integres a capacite de substrat parasite reduite
AU2001219296A AU2001219296A1 (en) 2000-11-27 2000-11-27 Integrated passive devices with reduced parasitic substrate capacitance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2000/032367 WO2002043145A1 (fr) 2000-11-27 2000-11-27 Dispositifs passifs integres a capacite de substrat parasite reduite

Publications (1)

Publication Number Publication Date
WO2002043145A1 true WO2002043145A1 (fr) 2002-05-30

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170162927A1 (en) * 2014-05-31 2017-06-08 Hatem Mohamed Aead Air Gap Creation In Electronic Devices

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5532506A (en) * 1994-08-31 1996-07-02 Texas Instruments Incorporated Integrated circuit adapted for improved thermal impedance
US6153489A (en) * 1997-12-22 2000-11-28 Electronics And Telecommunications Research Institute Fabrication method of inductor devices using a substrate conversion technique

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5532506A (en) * 1994-08-31 1996-07-02 Texas Instruments Incorporated Integrated circuit adapted for improved thermal impedance
US6153489A (en) * 1997-12-22 2000-11-28 Electronics And Telecommunications Research Institute Fabrication method of inductor devices using a substrate conversion technique

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170162927A1 (en) * 2014-05-31 2017-06-08 Hatem Mohamed Aead Air Gap Creation In Electronic Devices

Also Published As

Publication number Publication date
AU2001219296A1 (en) 2002-06-03

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