TW200302560A - Chip arrangement - Google Patents

Chip arrangement Download PDF

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Publication number
TW200302560A
TW200302560A TW091135828A TW91135828A TW200302560A TW 200302560 A TW200302560 A TW 200302560A TW 091135828 A TW091135828 A TW 091135828A TW 91135828 A TW91135828 A TW 91135828A TW 200302560 A TW200302560 A TW 200302560A
Authority
TW
Taiwan
Prior art keywords
contact
wafer
front side
substrate
rear side
Prior art date
Application number
TW091135828A
Other languages
Chinese (zh)
Other versions
TW594957B (en
Inventor
Boris Mayerhofer
Jochen Mueller
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of TW200302560A publication Critical patent/TW200302560A/en
Application granted granted Critical
Publication of TW594957B publication Critical patent/TW594957B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]

Abstract

The invention proposes a chip arrangement with a chip (20) having a front side (21) and a rear side (22), in the front side of which at least one integrated component is formed, the chip being provided on or in its front side with contact pads (23) for contacting the integrated component and having contact material elements (24) of a contact material which extend in material receptacles (29) between the contact pads (23) and contact points (26) on the rear side of the chip, and with a substrate (10) with a contact side (11), on which contact areas (12) are formed to define a contact area layout, the chip being arranged on the substrate in such a way that the rear side (22) of the chip (20) is arranged on the contact side (11) of the substrate (10), and the contact areas (12) come to lie opposite the contact points (26), thereby establishing an electrical connection.

Description

200302560 ⑴ 玟、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、内容、實施方式及圖式簡單說明) 技術領域 本發明係關於基板上晶片的配置或連接，其係藉由與倒 裝晶片技術相似之技術。上述配置中，在基板的一接觸側 上有複數個接觸區（用於定義接觸區域配置），該晶片與其 電性連接。晶片配置經常安裝於支持結構中，如在晶片卡 中。 先前技術 、在先前技術中，採用倒裝晶片技術將晶片與基板連接廣 為人知。圖2中顯不该種連接之示範性具體實施例。在基板 W的接觸側11上，示範性地提供兩接觸區12。在該具體實 她例中，該等接觸區12還可利該接賴11的表面來對齊 人曰日片20的月ij側2 1上配有接觸焊墊23，用以接觸前側内整 合之一組件；該晶片藉由接觸金屬化25分別與基板ι〇上的 各接觸區12連接。在晶片20的前側21上通常具有一鈍化層 ⑽中^顯示）以保護整合組件。接觸焊墊23位於該純化層 内或牙過該鈍化層以接觸形成於該晶豸前側内的整合组 ^牛。此外，在前側21與基板接觸側n之間提供封裝化;物 二f可為(例如)黏合劑。其目的係保護該峨 丨生接觸免受潮氣及/或改進 。徒# 逆/日日月在基板上的機械穩定性 榼官圖2中未予顯示，但該封裝 完全包圍。 '衣化。物31可將該晶片20 如果上述晶片配置固定於晶片卡中，去曰 詈i Μ物 田日日片卡或晶片酉己 ;%曲負載受損時’使用該類晶 乂大貝曰曰片或電性接觸的晶片 (2) 200302560 發明_明續頁 卡會有危險。為避免該種損害，已知可在美 二如稭由有意使基板變軟以保證晶 ： 片=倒裝晶片技術建構的晶片配置中，f曲負 y 成、'且件所垅成的損害大於傳統晶 係利用焊線在晶片的接觸焊墊與基板立， 性接觸。 j匕I間建立電 發明内容 因此，本發明之目的係提供—種晶片配置 板接觸，且該晶片配置 Ή曰片轉基 能力。 四刀蚪具有較鬲的負載承受 此目的之達成係藉由申請專利範圍第工項之特徵 附之申請專利範圍可獲得較佳改進。 ，Κ據所 本發明係根據在晶片配置中，a 的一側發生斷列,^ 日日片主要係從與基板連接 配w Γ 倒裝晶片技術與基板接觸的晶片 配置中，係前侧（整合組件形成其 杜曰丄Α Λ y j 暴板的接觸側相連。 /、取大危險係導致從前側發生斷 又土 —衣’亚因此對前铜 的整合組件產生損害。 〆成 因此’本發明提供-種晶片配置，其晶片具有前側及後 側；在該前侧内形成至少一個整 、有別側及後 L 1, y ?. 、、、件’在该晶片的前側 上或刖侧内使用接觸焊墊以接 ,_ α 正口組件。此外，依眧 备明’該晶片具有—種接觸材料的接觸材料元件，立在、 接觸焊墊與晶片後側上的 /、 _曰H ^ f⑨~ A 〃、、之間的材料容器内延展。 ^ " ，、有一接觸側，其上形成接觸 £以疋義一接觸區域配置。 罝曰曰片與基板接觸之方法係該晶 200302560 ，說明_ 片的後側與基板的接觸側接觸，且接觸區與接觸點相對， 因此建立一種電性連接。 即才木用與倒裝晶片技術相似的方法，藉由晶片的後侧與 基板發生接觸。由於這時整合組件的位置係在晶片遠離基 板接觸側的-側’因此電性連接的發生必須（例如）藉由通二 或错由貫穿該晶片表面的導體軌道，則晶片後側上相應的 接觸點可用於進一步的接觸。 其結果為該晶片前側上的接觸焊墊無需一定在該前側上 形成。另外’用於接觸整合組件的接觸焊墊也可配置於前 [J之内使之热法從外部接觸。例如，接觸焊墊可如本文 首段提到的那樣位於鈍化層之下。在兩項具體實施例中， 接觸;c干塾均係金屬化形成。然而’如果該等接觸焊塾組成 一埋放於晶片前側内的摻雜區域則不必如此。 在一較佳具體實施例中，該晶片後側變薄。可採取各種 方法使後側變薄’如姓刻或抛光。藉由選擇適當的工:方 法，可增強後侧的斷裂強度。然而，如果接觸焊墊形成於 晶片前侧之上，則會限制該前側斷裂強度的增強。因此，、 使晶片的後側變薄可增強機械穩定性’且增強該晶片的 裂強度。 在另一較佳改進中，材料容器貫穿晶片。因此，該材料 容器内的接觸材料元件組成通孔或後侧接觸。特別係隨著 後側的變薄’通孔或後側接觸的發生代表一種嘗試與測試 (tried-and-tested)的可靠發生方法。 此外，可使材料容器貫穿前侧、後側及連接該前後側的 (4) (4)200302560 發明說明續頁. 至/條晶片側邊。接著，前侧上各接觸焊墊與後側上各 接觸點之間藉由貫穿晶片表面的導體結構產生電性接觸。 在此變更中，可省略通孔。 實施方式 圖1顯示根據本發明的晶片配置之一示範性具體實施例 。兩接觸區12以示範形式配置於基板1〇的接觸側丨丨之上。 4等接觸區12也可置於接觸側丨丨之内，以便利用後者的表 面來對齊。 晶片20具有前側21及後側22。在前侧以内形成至少一整 合組件。因此，前側21可視為晶片的「活動侧」。以傳統方 y成的兩接觸;I：干墊2 3以示範形式配置於前側2 1之上。這 。未著係其上形成接觸焊墊23的一鈍化層與前侧2 1接觸。 接觸：!：干墊23接著貫穿該鈍化層，且在各實施例中與至少一 整合組件接觸。 依照本發明的後側22與基板10的接觸相對 /亚以機械方式牢牢地與後者連接。此種機械連接的實現 係藉由（例如）黏合劑31。為了在接觸焊墊23與基板1G的接觸 2 12之間產生電性接觸，材料容器29需在晶片内形成，該 合裔攸後側22向上延伸至接觸點23遠離前侧2丨的一側。各 材料合③29的側壁27内覆蓋—絕緣材料28。剩餘區域内填 充有一導電接觸材料的接觸材料元件24。接觸材料元件在 後側22上形成接觸焊㈣，就其而言係藉由接觸金屬化u =板接觸區12連接。接觸金屬化25可為(例如)焊錫凸塊或 導包黏^凸塊。由於晶片2Q的接觸烊墊Μ與接觸區】2之 (5) (5)200302560 間的電性連接係藉由接觸材料元件及接觸金屬化”，因此 可應用封裝化合物或黏合劑31以保證該電性接觸的氣密端 卜士上所述’ 封裝化合物或黏合劑3 1還可保證晶 片在基板1 〇上的機械穩定性。 材料容器29與其内的接觸材料元件24還可視為通孔或後 側接觸。在先前技術中，該類接觸通孔為人所孰知’對咳 ^亀說明。因此在該實施例中，材料容器 各 種方式形成： :在晶圓或晶片變薄之前的程式中，在適當位置採取 =刻法。在該實施例中，從前側^通孔對應點處 蝕划一條比後面的組件厚度稍深的溝渠。 :::渠内填充專門導電的接觸材料：並與晶片2。上組件 ^ =料塾23接觸。隨後進行的變薄製程係用於使填 “的内側曝光並在後側形成所需的接觸焊墊。 人b)對晶片20進行處理後’即在前側加形成所有的整 I:應:鈍化，成接觸焊墊23,則晶片-從其 材料六f側22*缚後，在晶片2G内從其後側形成-γ^29’且形成點為接觸焊墊23在前側上的位置。材 科谷益的形成可藉由（例如）#刻法。口 伸出，即可、要接觸料23的後側 壁27内覆罢^為此’首先在材料容器29的側 餘空間：'、、.6緣材科。接著，用-導電接觸材料填充剩 因此接㈣接觸材料的填充係從晶片2G的後侧22進行， 生電 件24在形成於後侧之上的接觸焊塾處可產 接觸。具體而言，此處也可先將—佈線板應用於晶 -10- 200302560 ⑹ 適應 L2=:。2’(例如)為了獲得不同的接觸焊墊配置、 该接觸的完成可藉由倒裝晶片技 技術。 义所知的所有連相 使晶片變薄可藉由蝕刻、拋光、研磨或^ 法。根據不同的工作方法可增強後側的”：材料相 變薄製程(研磨)中受損的位置也可藉由餘刻或：光：料: 除，且產生的石夕表面之斷裂壓力位準較高。L 以'月 裂壓力決定於組件的產生，且通常較低。的最大斷 儘管未在圖i中明確顯示，但是目前晶片 接技術無需—定要在晶片的前側觸及 ^日的連 觸焊墊23可（例如）位於另—絕緣層之下。纟料墊23。接 同^ ’ H由貫穿該晶片表面的導電結構在接觸焊塾_ 側上的接觸點26之間也可產生電性接觸。具體而: P错由貝穿該晶片的接觸通孔無法接觸部分接 ’可實施此變吏。 ^ “月提供一種與先丽技術相比具有車交高斷裂強 又的曰曰片配置’由於該晶片的連接係藉由其後侧，因此採 取各種工作方法可給予其最大的斷裂強度。 圖式簡單說明 本發明根據圖式詳細說明如上，其中·· 圖1顯示根據本發明的晶片配置之一示範性具體實 ’以及 圖2顯示本文首段中所述之先前技術的晶片配置。 200302560 ⑺ 罐卿續頁、、 圖式代表符號說明 10 基板 11 接觸側 12 接觸區 20 晶片 21 前侧 22 後側 23 接觸焊墊 24 接觸材料元件 25 接觸金屬化 26 接觸點 27 (材料容器的）侧壁 28 絕緣材料 29 材料容器 3 0 侧邊 3 1 黏合劑： -12-200302560 玟 发明, description of the invention (the description of the invention should state: the technical field to which the invention belongs, the prior art, the content, the embodiments, and the simple description of the drawings) TECHNICAL FIELD The present invention relates to the arrangement or connection of wafers on a substrate. Technology similar to flip chip technology. In the above configuration, there are a plurality of contact areas (for defining a contact area configuration) on a contact side of the substrate, and the wafer is electrically connected to the wafer. Chip configurations are often installed in support structures, such as in chip cards. In the prior art, in the prior art, it is known to use a flip chip technology to connect a wafer to a substrate. An exemplary embodiment of such a connection is shown in FIG. 2. On the contact side 11 of the substrate W, two contact regions 12 are exemplarily provided. In this specific example, the contact areas 12 can also benefit the surface of the contact 11 to align the moon ij side 21 of the Japanese sunray 20 with a contact pad 23 for contacting the internal integration of the front side. A component; the chip is connected to each contact region 12 on the substrate ι through contact metallization 25, respectively. On the front side 21 of the wafer 20, there is usually a passivation layer (shown in the figure) to protect the integrated components. The contact pads 23 are located in the purification layer or pass through the passivation layer to contact the integrated group formed in the front side of the wafer. In addition, encapsulation is provided between the front side 21 and the substrate contact side n; the object f may be, for example, an adhesive. Its purpose is to protect the organism from moisture and / or improvement.徒 # Inverse / Sun, Moon and Moon Mechanical Stability on the Substrate The eunuch is not shown in Figure 2, but the package is completely enclosed. 'Clothing. If the wafer configuration is fixed in the wafer card, go to 物 Ｍ 田 日 日 片 卡片 or the wafer itself; if the curved load is damaged, use this type of wafer Electrically Contacted Chips (2) 200302560 Invention _ Ming continuation card can be dangerous. In order to avoid this kind of damage, it is known that in the United States, such as straw, the substrate is intentionally softened to ensure the crystal: In the chip configuration constructed by flip chip technology, f is negative and y is the damage caused by Larger than the traditional crystal system, the contact pads on the wafer are used to make sexual contact with the substrate. Therefore, the object of the present invention is to provide a wafer configuration board contact, and the wafer configuration has a chip transfer capability. The four-knife shovel has a relatively heavy load bearing. The achievement of this purpose can be achieved by the patent application scope attached to the patent application scope. According to the invention, according to the present invention, according to the wafer configuration, a side line is broken. ^ Japanese and Japanese films are mainly from the wafer configuration that is connected to the substrate and is connected to the substrate by flip-chip technology. The front side ( The integrated component forms the contact side of the Du Yue 丄 Α Λ yj storm plate. /. Taking a large danger system will cause a break from the front side. The soil-coating will cause damage to the front copper integrated component. 〆 成 Therefore 'the present invention Provide a wafer configuration with a wafer having a front side and a rear side; at least one whole, other side, and rear L 1, y?. ,,,, and 'are formed on the front side or the inner side of the wafer in the front side The contact pad is used to connect the _α positive port assembly. In addition, it is stated that the wafer has a contact material element of a contact material, which stands on the rear side of the contact pad and the wafer. f⑨ ~ A 〃, extending in the material container. ^ " There is a contact side on which contact is formed. The contact area is arranged in the meaning of a contact area. The method of contacting the wafer with the substrate is the crystal 200302560, explaining _ The back side of the sheet is in contact with the contact side of the substrate And the contact area is opposite to the contact point, so an electrical connection is established. That is, Caimu uses a method similar to flip chip technology to contact the substrate with the back side of the wafer. At this time, the position of the integrated component is away from the wafer. The-side of the substrate's contact side therefore the electrical connection must occur (for example) through a conductor track that runs through the surface of the wafer through two or by mistake, then the corresponding contact point on the back side of the wafer can be used for further contact. The result is The contact pads on the front side of the wafer need not necessarily be formed on the front side. In addition, the contact pads for contacting the integrated components may also be arranged in the front [J] to make them thermally contact from the outside. For example, the contact pads may be As mentioned in the first paragraph of this article, it is located under the passivation layer. In two specific embodiments, the contact; c dry is formed by metallization. However, if the contact pads constitute a buried in the front side of the wafer The doped region need not be so. In a preferred embodiment, the backside of the wafer is thinned. Various methods can be used to make the backside thinner, such as engraving or polishing. By selecting the appropriate process: Method can increase the fracture strength of the rear side. However, if the contact pad is formed on the front side of the wafer, it will limit the increase of the fracture strength of the front side. Therefore, thinning the rear side of the wafer can enhance mechanical stability ' And enhance the crack strength of the wafer. In another preferred improvement, the material container penetrates the wafer. Therefore, the contact material elements in the material container constitute a through hole or a backside contact. Especially as the backside becomes thinner, the communication The occurrence of a hole or backside contact represents a reliable method of trial-and-testing. In addition, a material container can be passed through the front side, the back side, and the (4) (4) 200302560 invention connecting the front and back sides The description continues. To / side of the wafer. Next, electrical contact is made between the contact pads on the front side and the contact points on the rear side through the conductor structure penetrating the surface of the wafer. In this modification, the through hole can be omitted. Embodiment FIG. 1 shows an exemplary embodiment of a wafer configuration according to the present invention. The two contact regions 12 are disposed on the contact side of the substrate 10 in an exemplary manner. The fourth-grade contact area 12 can also be placed within the contact side, so that the latter surface can be used for alignment. The wafer 20 has a front side 21 and a rear side 22. Form at least one integrated assembly within the front side. Therefore, the front side 21 can be regarded as the "moving side" of the wafer. Two contacts in a traditional square y; I: The dry pad 2 3 is arranged on the front side 2 1 in an exemplary form. This . A passivation layer on which the contact pad 23 is not formed is in contact with the front side 21. Contact:!: The dry pad 23 then penetrates the passivation layer and is in contact with at least one integrated component in various embodiments. The contact between the rear side 22 and the substrate 10 according to the invention is mechanically firmly connected to the latter. This mechanical connection is achieved by, for example, an adhesive 31. In order to make electrical contact between the contact pad 23 and the contact 2 12 of the substrate 1G, the material container 29 needs to be formed in the wafer, and the rear side 22 extends upward to the side of the contact point 23 away from the front side 2 丨. The inside of each side wall 27 of each material ② 29 is covered with an insulating material 28. The remaining area is filled with a contact material element 24 of a conductive contact material. The contact material element forms a contact pad on the rear side 22, which is connected by means of contact metallization u = plate contact region 12. The contact metallization 25 may be, for example, a solder bump or a lead-in bump. Because the electrical connection between the contact pad M of the wafer 2Q and the contact area] 2 of (5) (5) 200302560 is through contact with the material element and contact metallization, "a packaging compound or an adhesive 31 may be applied to ensure the The encapsulation compound or adhesive 3 1 described on the hermetically sealed end of the electrical contact can also ensure the mechanical stability of the wafer on the substrate 10. The material container 29 and the contact material element 24 inside it can also be regarded as a through hole or Back-side contact. In the prior art, this type of contact through-hole is known as the 'cough ^'. Therefore, in this embodiment, the material container is formed in various ways: before the wafer or wafer is thinned. In the appropriate place, the = engraving method is adopted. In this embodiment, a trench is etched from the corresponding point of the front side ^ through hole slightly deeper than the thickness of the rear component. ::: The trench is filled with a specially conductive contact material: and It is in contact with the wafer 2. The upper element ^ = material 23. The subsequent thinning process is used to expose the inner side of the pad and form the required contact pads on the rear side. Person b) After the wafer 20 is processed, that is, all the whole is formed on the front side: should be: passivated, into contact with the pad 23, then the wafer-from its material six f side 22 * bound, from the wafer 2G from it The rear side forms -γ ^ 29 'and the formation point is the position of the contact pad 23 on the front side. The formation of materials can be formed by, for example, # 刻 法. The mouth is extended, that is, the rear side wall 27 to be contacted with the material 23 is covered. To this end, firstly, in the side space of the material container 29: ',. Next, the remaining conductive contact material is filled from the back side 22 of the wafer 2G with the conductive contact material, and the electrical component 24 can make contact at the contact pad formed on the back side. Specifically, the wiring board can be applied to the crystal first -10- 200302560 ⑹ Adapt to L2 = :. 2 '(for example) in order to obtain different contact pad configurations, the contact can be completed by flip chip technology. All known thin films can be thinned by etching, polishing, grinding, or metallization. According to different working methods, the rear side can be strengthened. The position of the damage in the material thinning process (grinding) can also be achieved by the moment or: light: material: except, and the fracture pressure level of the stone surface Higher. L depends on the generation of the component by the "lunar pressure", and is usually lower. Although the maximum break is not clearly shown in Figure i, the current wafer bonding technology is not required-it is necessary to touch the front side of the wafer The contact pads 23 may, for example, be located under another insulation layer. The pads 23. Following the ^ 'H, a conductive structure penetrating the surface of the wafer may also be produced between the contact points 26 on the contact pad side. Electrical contact. Specifically: P is wrongly connected by the contact through hole of the wafer through which the contact ca n’t be contacted. This change can be implemented. ^ "Provide a method that has a high fracture strength compared with Xianli technology." Chip configuration 'Since the connection of the chip is through its rear side, various working methods can be used to give it the maximum breaking strength. Brief Description of the Drawings The present invention is described in detail above with reference to the drawings, in which: Fig. 1 shows an exemplary embodiment of a wafer configuration according to the present invention 'and Fig. 2 shows a prior art wafer configuration described in the first paragraph of this document. 200302560 ⑺ Can Qing Continuation Sheets, Schematic Symbols Description 10 Substrate 11 Contact Side 12 Contact Area 20 Wafer 21 Front Side 22 Rear Side 23 Contact Pad 24 Contact Material Element 25 Contact Metallization 26 Contact Point 27 (of a material container) Side wall 28 Insulating material 29 Material container 3 0 Side 3 1 Adhesive: -12-

Claims (1)

200302560200302560 拾、申請專利範圍 1. 一種具有一晶片（20)之晶片配置，該晶片（20)具有一前 側（21)及一後側（22)，在該前側（21)形成至少一個整合組 件，在該晶片（20)的前侧（21)上或其内配有接觸焊墊（23) 用以接觸该整合組件；該晶片還具有一接觸材料之接觸 材料元件（24)，其在該接觸焊墊（23)與該晶片（2〇)的該後 側（22)上的接觸點（26)之間的材料容器（29)内延展；該配 置具有一基板（10)，其有一接觸侧（11)，其上形成接觸 區（12)以定義一接觸區域配置，該晶片（2〇)與該基板（1〇) 的配置方法為該晶片（20)的該後側（22)與該基板（1〇)的 該接觸側（11)接觸，且該等接觸區（12)的位置與該等接 觸點（26)相對，藉以建立一電性連接。 2.如申請專利範圍第1項之晶片配置，其中該晶片（2〇)係在 其後側（22)變薄。 3如申請專利範圍第1或2項之晶片配置’其中該材料容器 (29)貫穿該:晶片（2〇)。 . 4.=申請專利範圍第！、2或3項之晶片配置，其中該材料 谷為（29)貫穿該前側（21)、該後側（22)及該晶片（20)連接 該前後侧的至少一侧邊（3〇)。Patent application scope 1. A wafer configuration with a wafer (20), the wafer (20) has a front side (21) and a rear side (22), at least one integrated component is formed on the front side (21), A contact pad (23) is provided on or in the front side (21) of the wafer (20) to contact the integrated component; the wafer also has a contact material element (24) of a contact material, which is on the contact weld The material container (29) between the pad (23) and the contact point (26) on the rear side (22) of the wafer (20) extends; the configuration has a substrate (10) with a contact side ( 11) A contact area (12) is formed thereon to define a contact area configuration, and the method of arranging the wafer (20) and the substrate (10) is the rear side (22) of the wafer (20) and the substrate The contact side (11) of (10) makes contact, and the positions of the contact areas (12) are opposite to the contact points (26), thereby establishing an electrical connection. 2. The wafer configuration according to item 1 of the patent application scope, wherein the wafer (20) is thinned on its rear side (22). 3 The wafer configuration according to item 1 or 2 of the scope of patent application, wherein the material container (29) runs through the: wafer (20). . 4. = No. of patent application scope! The wafer configuration of item 2, 2 or 3, wherein the material valley is (29) penetrating the front side (21), the rear side (22), and the wafer (20) connected to at least one side (30) of the front and rear sides.
TW091135828A 2001-12-12 2002-12-11 Chip arrangement TW594957B (en)

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US5399898A (en) * 1992-07-17 1995-03-21 Lsi Logic Corporation Multi-chip semiconductor arrangements using flip chip dies
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US5973396A (en) * 1996-02-16 1999-10-26 Micron Technology, Inc. Surface mount IC using silicon vias in an area array format or same size as die array
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