EP1623459A1 - Structure a lignes bits et son procede de realisation - Google Patents

Structure a lignes bits et son procede de realisation

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Publication number
EP1623459A1
EP1623459A1 EP04728577A EP04728577A EP1623459A1 EP 1623459 A1 EP1623459 A1 EP 1623459A1 EP 04728577 A EP04728577 A EP 04728577A EP 04728577 A EP04728577 A EP 04728577A EP 1623459 A1 EP1623459 A1 EP 1623459A1
Authority
EP
European Patent Office
Prior art keywords
trench
layer
substrate
bit line
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP04728577A
Other languages
German (de)
English (en)
Other versions
EP1623459B1 (fr
Inventor
Ronald Kakoschke
Franz Schuler
Georg Tempel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1623459A1 publication Critical patent/EP1623459A1/fr
Application granted granted Critical
Publication of EP1623459B1 publication Critical patent/EP1623459B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a bit line structure and to a method for its production and in particular to a sub-100 nm bit line structure and an associated production method as used in a non-volatile SNOR memory circuit for the selective control of source and drain lines can.
  • FIG. 1A shows a simplified representation of a so-called SNOR architecture (Selective NOR), in which, in contrast to the NOR architecture with an “ooramon source” structure, the individual memory elements SEI, SE2,... Selectively via a respective source line S 1 , SL2, ... and can be controlled via a respective drain line DU, DL2, ...
  • This selective control is carried out, for example, via respective bit line controls BLC which, so to speak, the common bit lines BL1, B 2, ... .
  • BLC bit line controls
  • FIG. 1B shows a simplified illustration of a conventional layout of the SNOR architecture according to FIG. 1A.
  • the switching elements or memory elements SEI, SE2,... are formed in active regions AA of a semiconductor substrate which have an essentially straight structure in the form of a strip.
  • the multiplicity of stripe-shaped active areas AA arranged in columns are overlaid row by row by layer stacks or word line stacks WL1, WL2,. Each crossing point or overlap area of such a stripe-shaped active area AA with a stripe-shaped word line stack WL thus represents a multiplicity of switching elements or memory elements SE.
  • contacts are necessary, which are usually formed in the active regions AA, but can often also extend into an adjacent insulation region SII (shallow trench insulation).
  • SII shallow trench insulation
  • Layer which preferably represents a first metallization layer, is now the source lines SL1, SL2, ... and the drain lines DL1, DL2, ... for the respective bit lines BL.
  • the drain lines here are connected via corresponding contacts KD to the associated drain regions D of the active region AA m, n in the same way the source lines SL being connected to the associated source regions S m via corresponding contacts KS.
  • a disadvantage of such a conventional bit line structure is that the additional source line compared to a "common source” architecture there is more than twice as dense metallization, which is a limiting factor for further integration or further shrinking.
  • FIGS. 2A and 2B show a simplified equivalent circuit diagram and a simplified sectional view of a further conventional bit line structure, as is known, for example, from US Pat. No. 6,438,030 B1.
  • the drain line DL1, DL2,... Is again designed as a surface bit line on a surface of a substrate 100, in which p-wells 101, 102,
  • Source line SL1, SL3, ... are formed in the semiconductor substrate.
  • a so-called buried connecting strip BS (Buried.) Is used to contact the respective source regions S and 1114, 1112 with the source line SL and the p-wells 101, 102,
  • Source management is connected. Via a silicide layer 1116, each source region of the switching elements or storage elements SE with the buried connection strip BS or
  • each p-well or buried source line 101 is electrically connected via a p-diffusion region 1010 and an associated contact to a source line SL1 guided on the surface.
  • the integration density can be considerably improved, since at least a large part of the source line is designed as a p-well region “buried” in the semiconductor substrate and the requirements for the metallization above the substrate surface are relaxed accordingly.
  • connection layers 1116 which usually consist of a silicide, have only a slight overlap due to the necessary but not shown spacers on the word line stacks of the memory elements SE and thus a high contact resistance to the p-well 101 or to Cause source line.
  • the conductivity of the p-well 101 or the buried source line is a limiting factor, since either with a low doping of the p-well 101 a conductivity is correspondingly low or with a high doping of the p-well 101 Breakdown voltages of the semiconductor component are deteriorated accordingly
  • a buried bit line is known from the publication US Pat. No. 6,008,522, which is formed in a trench, with respective source and drain regions being formed on their upper edges by means of out-diffusion
  • the invention is based on the object of creating a bit line structure and an associated production method, with a further increase in the integration density being obtained with improved electrical properties. According to the invention, this problem is solved with regard to the bit line structure by the features of patent claim 1 and with regard to the method by the measures of patent claim 9.
  • a trench which is formed in a substrate a first trench isolation layer which is formed on the trench surface, a first trench fill layer which is formed on the surface of the first trench isolation layer and fills a lower portion of the trench, a second trench isolation layer, which is formed on the surface of the first trench fill layer, a second electrically conductive trench fill layer for forming a buried bit line, which is formed on the surface of the second trench isolation layer and at least partially fills an upper portion of the trench up to the substrate surface, at least one first doping region of the first conductivity type , which is formed in the surface of the substrate, at least a first electrically conductive connection layer which is used for electrically connecting the first doping region to the second trench fill layer on the surface of the first doping region first trench insulating layer and the second trench filling layer, at least a second doping region of the first conductivity type, which is formed in the surface of the substrate, a surface dielectric which is formed on the surface of the substrate and the filled trench, a surface bit line
  • the Line resistances, in particular of the buried bit line, are significantly reduced, as a result of which semiconductor arrangements can be implemented with improved speeds or reduced supply voltages. Since no additional lithography levels are required, the bit line structure can be implemented using standard methods. In addition, a large number of the elements are designed to be self-adjusting, which further reduces the requirements for the adjustment accuracy.
  • the second trench fill layer is preferably formed in the upper section of the trench on the side to the first doping region to be connected, while the other side of the trench is filled with a third trench isolation layer and preferably with a shallow trench isolation (SII, shallow trench isolation). In this way, further improved insulating properties are obtained, as a result of which the electrical properties of a semiconductor component to be formed or a memory arrangement can be further improved.
  • SII shallow trench isolation
  • Crystalline silicon is preferably used for the substrate, highly doped polysilicon for the second trench fill layer and a silicide layer for the first connection layer, a silicide blocking layer being formed at least over the second doping regions, as a result of which the buried bit line is self-supporting and with minimal contact resistance to the associated one Allow doping areas to be connected.
  • a dummy or Blmd contact can also be used instead of the silicide layer, a first and a second dielectric layer being formed for the surface dielectric and the dummy contact being formed only in the first dielectric layer.
  • the substrate preferably has a multilayer trough structure, the trench projecting beyond the lowest trough onto the substrate and the second trench insulating layer lying on a level between the substrate surface and an underside of a first trough.
  • the insulation properties between adjacent cells can be further improved, with parasitic transistors, latch-up effects and punch-through effects in particular being reliably prevented by the electrically conductive trench fill layer in the lower section of the trench, and the electrical properties being further improved can be.
  • a substrate is prepared, a trench is formed in the substrate, a first trench isolation layer is formed on a trench surface of the trench, a first electrically conductive trench filling layer is formed on the surface of the trench isolation layer in a lower section of the trench, and a second trench isolation layer formed on the surface of the first trench fill layer, a second electrically conductive trench fill layer is formed as a buried bit line on the surface of the second trench insulation layer, which at least partially fills an upper portion of the trench up to the substrate surface, at least a first and second doping region in the surface of the
  • At least a first electrically conductive connection layer for electrically connecting the at least at least a first doping region is formed with the second trench fill layer, a surface dielectric is formed on the substrate surface, at least one second electrically conductive connection layer is formed in the surface dielectric, and a surface bit line is formed on the surface of the surface dielectric in such a way that it contacts the at least one second connection layer.
  • FIGS. 1A and 1B show a simplified equivalent circuit diagram and a simplified top view of a layout of a conventional bit line structure in an SNOR memory circuit
  • FIGS. 2A and 2B show a simplified equivalent circuit diagram and an associated sectional view of a further conventional bit line structure
  • FIG. 3 shows a simplified plan view of a layout of a semiconductor circuit with a bit line structure according to the invention
  • FIGS. 4A to 4C simplified sectional views of the semiconductor circuit arrangement according to FIG. 3 to illustrate a bit line structure according to a first exemplary embodiment
  • FIG. 5 shows a simplified sectional view of a semiconductor circuit arrangement to illustrate a bit line structure according to a second exemplary embodiment
  • FIGS. 6A to IOC show simplified sectional views of a semiconductor circuit arrangement to illustrate essential method steps in the production of a bit line structure in accordance with a third exemplary embodiment
  • FIGS. 11A to 11C simplified sectional views of a
  • FIG. 3 shows a simplified plan view to illustrate a layout of a bit line structure according to the invention, as can be used, for example, in an SNOR semiconductor memory circuit.
  • the same reference numerals designate the same or corresponding elements or layers as in FIGS. 1 and 2.
  • a multiplicity of strip-shaped active regions AA are formed in a column-like manner in the substrate in a substrate which, for example, has a semiconductor substrate and preferably crystalline silicon, by means of a multiplicity of strip-shaped trench insulations T.
  • word line stacks WL are formed in a cell shape perpendicular to these strip-shaped active regions AA on the surface of the substrate, with a first insulating layer, such as a gate oxide layer or a tunnel layer, for example for the realization of non-volatile memory elements SE , a charge-storing layer, such as a floating gate, a second insulating layer, such as an ONO layer sequence, and a control Have layer as the actual driving word order.
  • Sidewall insulating layers or spacers SP are formed on the rare walls of the word line stacks WL for insulation purposes.
  • a switching element or a non-volatile memory element SE is consequently formed, which, for realizing a field transistor structure, drain regions D and source regions S, as first and second doping regions on the sides have the word line stack.
  • bit line structure consisting of a source line and dram line pair SL and DL is now not only in a metallization level on the surface of the substrate, but on the one hand as a buried bit line or source line SL in the trench T within of the substrate and secondly as a surface bit line or drain line DL, preferably in a first metallization level above the substrate surface.
  • the buried bit line SL is embedded in an upper section of the trench insulation or trench T and is connected to the source regions S to be contacted via locally formed first connection layers 11.
  • the surface bit line or drain line DL formed, for example, in a first metallization level is connected via contacts 13 to associated drain regions D of the switching elements SE.
  • the surface bit line DL is in the form of a strip above the active regions AA. Because of this straightforward stripe design, these can be defined lithographically relatively easily, which is why they are particularly important for sub-100 nm structures. In principle, however, they can also have a different shape.
  • FIG. 4 shows a simplified sectional view along a section A-A according to FIG. 3, the same reference symbols again designating the same elements or layers and a repeated description being omitted below.
  • the layers for the intermediate dielectric and for the drama line, which are further developed on the substrate surface were not shown.
  • a semiconductor substrate has a multi-layer structure or a multi-well structure, a second deep n-well 100 also being formed in the substrate in addition to a first p-well 101 near the surface.
  • a multiple trough structure is particularly advantageous with regard to its shielding effect and its insulation properties, since sufficient insulating layers can also be formed in these regions of the substrate, for example by means of space charge zones, and complex structures can also be implemented.
  • the trenches T are now formed, which protrude at least beyond the first trough 101 and have a trench insulation layer 2 on their trench walls.
  • a first trench filling layer 3 is now formed on the surface of the trench insulating layer 2 such that it completely fills the lower section of the trench.
  • Highly doped polycrystalline semiconductor material is preferably used, with other electrically conductive materials such as metals or electrically nonconductive materials such as undoping.
  • tes semiconductor material or insulating ate ⁇ al (S ⁇ 0 2 ) can be used in principle. In particular, semiconductor materials can be deposited particularly easily and without the formation of undesired gaps or voids in the deep trench.
  • This first trench fill layer 3 therefore essentially serves to improve the insulation or shielding between the adjacent cells and in particular prevents the formation of parasitic transistors along the trench in the direction of the substrate or of parasitic transistors along the trench from one cell field to the neighboring cell field. In the same way, punch-through or latch-up effects are reliably prevented.
  • a second trench insulation layer 4 is formed on its surface, its level or relative height preferably being between the substrate surface and the underside of the first trough 101.
  • the insulation properties can be further improved in this way, particularly in the multiple tub structure shown.
  • a second electrically conductive trench fill layer for forming an actual buried bit line SL is also formed on the surface of the second trench insulation layer 4 such that an upper section of the trench T is at least partially filled up to the substrate surface.
  • highly doped polycrystalline semiconductor material is preferably used as the second trench fill layer 5, although alternative electrically conductive materials and in particular metals can also be formed in the upper section.
  • the second trench fill layer 5 is only half formed in the upper section of the trench T, while the other half of the trench is filled with a third trench insulation layer 6, which is preferably made using an STI method (shallow trench isolation) HDP S1O 2 (high density plasma) exists.
  • STI method shallow trench isolation
  • HDP S1O 2 high density plasma
  • word line stacks WL are also formed on the substrate surface, which, in the case of non-volatile memory elements, have a first insulating layer or tunnel layer 9A, a charge-storing layer 9B, a second insulating layer or ONO layer sequence 9C and a control layer 9D and are structured accordingly ,
  • spacers SP can also be formed on the rare walls of the word line stacks WL in a known manner
  • a silicide blocking layer 10 is formed on the surface of the second doping regions D to form self-aligning first electrically conductive connection layers 11 for electrically connecting the first doping regions S, which silicidization of the exposed one Semiconductor material or silicon reliably prevented.
  • the first electrically conductive connection layers 11 are obtained in a self-adjusting manner for the first doping regions S.
  • the first doping regions S can thus be connected in a self-aligning manner via the first connection layer 11 to the second trench fill layer 5 or the buried bit line with excellent connection contacts.
  • the control layer 9D also consists of a polycrystalline semiconductor material
  • a highly conductive control layer 9E can accordingly also be formed on its surface, as a result of which the conductivity in the word line stack is further improved.
  • the formation of the first and second doping regions S and D is in turn self-adjusting by means of ion implantation.
  • a surface dielectric 12 is then formed on the substrate surface or on the surface of the word line stack, the silicide blocking layer 10 and the first connection layer 11, on the surface of which a surface bit line or a drain line DL is in turn formed.
  • a second connection layer 13 is preferably formed in the form of conventional contacts in the surface dielectric.
  • FIG. 5 shows a simplified sectional view of a semiconductor circuit arrangement for illustrating a bit line structure according to a second exemplary embodiment, the same reference symbols denoting the same or corresponding layers or elements as in FIGS. 1 to 4 and a repeated description being omitted below.
  • a non-self-aligned third trench isolation layer 6 can preferably be formed on the substrate surface in the upper section of the deep trench T by means of shallow trench isolation (STI, shallow trench isolation).
  • STI shallow trench isolation
  • FIGS. 6A to IOC show simplified sectional views along respective sections AA, BB and CC according to FIG. 3 to illustrate essential process steps in the Production of a bit line structure according to a third exemplary embodiment, the same reference numerals again designating the same or corresponding elements or layers as in FIGS. 1 to 5, and a repeated description is omitted below.
  • deep trenches T are first used using a structured first hard mask layer HML and one below lying pad oxide PO formed.
  • the methods for forming deep trenches used in DRAM production are preferably carried out, but these are not locally limited trenches, but rather elongated insulating trenches T.
  • a first trench insulation layer 2 preferably in the form of a so-called lmer oxide, is thermally formed on the trench surface of the trench T, for example.
  • the first hard mask HML has Si a, for example, SiO? Is preferably used for the first trench insulating layer 2 and the pad oxide? used
  • a first electrically conductive or non-conductive trench fill layer 3 is then formed on the surface of the trench insulation layer 2 in a lower section of the trench T, preferably completely filling the trench T with, for example, highly doped or undoped polysilicon or another electrically conductive or non-conductive material and a subsequent reset step is carried out.
  • a second trench insulation layer 4 is formed on the surface of the first trench fill layer 3, with the use of polysilicon for the first trench fill layer 3, preferably an oxide layer growing on it. se is carried out by means of thermal treatment.
  • a further deposition process for filling the second trench fill layer 5 is carried out in the upper portion carried out by means of polysilicon and then etched back to the substrate surface, the first hard mask layer HML, consisting of S13N J , being finally removed or stripped.
  • a part of the trench fill layer that is not required is removed from the upper trench section, the second hard mask layer HM2 again having S1 3 N1 and in particular that for the buried one Trench fill layer 5 provided at the bit line is at least partially covered.
  • a further oxide layer (not shown) can be formed in the exposed areas at this point in time, which results in a further Lmer oxide in the exposed shallow trench.
  • a so-called pull-back etching of the second hard mask layer HM2 now takes place, as a result of which this layer is partially etched back and the edges are rounded off.
  • a third trench isolation layer 6 is then preferably deposited as an shallow trench isolation layer (STI, shallow trench isolation), for example by means of an HDP method (high density plasma), as a result of which the exposed upper section of the trench T is now refilled.
  • STI shallow trench isolation
  • HDP method high density plasma
  • a high-voltage dielectric and, for example, the removal of preferably a first part of this high-voltage dielectric can be carried out on the relevant cell area shown in the figures in a section of the semiconductor substrate (not shown).
  • a first surface insulation layer 7 can then preferably be grown thermally, a second part of the high-voltage dielectric being formed in the high-voltage region and a very thin layer in the relevant line region in question, in particular on the surface of the active regions AA
  • Gate dielectric or a tunnel insulation layer (TOX) can be formed, which at the same time has a much greater thickness in the region of the highly doped trench fill layer 5 (due to the higher growth rates) and thus reliably prevents the formation of active field effect transistor structures.
  • the very thin tunnel oxide layer usually required above the active regions AA is obtained with only one process step, while above the highly doped polysilicon trench fill layer 5, reliable passivation is achieved by means of a much thicker layer thickness.
  • the word line stacks WL with their optionally additionally formed first insulating layer 9A, their charge-storing layer 9B, their second insulating layer or ONO layer sequence 9C and their control layer 9D are formed using conventional methods, and with spacers or side wall iso - Provide lation layers SP.
  • a silicide blocking layer 10 is then formed in the region of the second doping regions D, a silicide blocking layer usually being deposited over the entire surface and then structured lithographically.
  • the silicide blocking layer 10 preferably consists of an S1 3 N / 1 layer.
  • the doping regions 8 are usually formed as a highly doped first or source region S and second or drain region D, preferably by means of ion implantation using the word line stacks WL or the associated spacers SP m of the surface of the substrate ,
  • first electrically conductive connection layer 11 for electrically connecting the first doping regions or source regions S to the second trench fill layer 5 or the buried bit line SL
  • siliconizable material or a siliconizable metal layer such as e.g. Cobalt, nickel or platinum deposited in a very laughable manner.
  • a conversion of the surface layer of the semiconductor material is then carried out, using the siliconizable material to form highly conductive first connection regions 11 and highly conductive control layers 9E of the word line stacks WL, with the surfaces not in contact with semiconductor material (silicon), i.e.
  • a surface dielectric 12 is formed on the substrate surface as an intermediate dielectric and a second electrically conductive connection layer 13 in the form of a conventional contact is generated therein.
  • the contact or the connection layer 13 preferably consists of a contact hole or via to the second doping region D, in which one TiN layer is preferably formed as a barrier layer with a W layer as a filling layer.
  • an electrically conductive layer is deposited over the entire surface of the surface of the surface dielectric 12, ie in the first metallization level, and structured in such a way that a surface bit line or drain line DL results which contacts the second doping regions or drain regions D via the contacts 13.
  • FIGS. 11A to 11C show simplified sectional views of the semiconductor circuit arrangement to illustrate a bit line structure according to a fourth exemplary embodiment, the same reference symbols denoting the same or corresponding elements or layers as in FIGS. 1 to 10 and a repeated description being omitted below.
  • a so-called dummy or blind layer can also be used as the highly conductive first connection layer 11.
  • the first connection layer 13A can be used as the first connection layer 13A. Accordingly, if a silicide blocking layer 10 and the use of siliconizable material are not available in a standard process, the first connection layer can also be realized by a so-called blind contact 13A.
  • the surface dielectric only has to have a first dielectric layer 12A and a second dielectric layer 12B formed thereon, the blind contact 13A being formed by means of conventional methods for producing contacts only in the first dielectric layer 12A at the locations in the semiconductor substrate or the circuit , on which the second trench fill layer 5 is to be electrically connected to the first doping regions S.
  • a TiN barrier layer and a W full layer can be filled in and then a second dielectric layer 12B can be formed over it to avoid short circuits. Any insulating layers 7 that are present are removed, which in turn provides highly conductive contacting using standard methods.
  • the second connection layer 13B is again formed by means of conventional contact methods by forming a contact hole or vias in both the first and second dielectric layers 12A and 12B at the locations of the second doping regions D to be contacted and is filled with electrically conductive material in a known manner.
  • the invention has been described above with reference to a non-volatile SNOR semiconductor memory circuit. However, it is not restricted to this and in the same way comprises further semiconductor circuits which have a corresponding bit line structure. Furthermore, the invention is not limited to the silicon semiconductor substrates and associated materials described, but instead includes alternative semiconductor materials with corresponding doping or isolation options in the same way. In the same way, the source and drain regions as well as the associated source and drain lines can be swapped accordingly.

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

L'invention concerne une structure à lignes bits comportant une ligne bits de surface et une ligne bits enterrée (5, SL), la ligne bits enterrée étant formée dans une partie d'une tranchée (T) et reliée à une première zone de dopage (S) correspondante. Dans une partie inférieure de la tranchée (T) se trouve en outre une première couche de remplissage de tranchée (3) qui est isolée de la ligne bits enterrée (5, SL) par une seconde couche d'isolation de tranchée.
EP04728577.0A 2003-05-14 2004-04-21 Structure de lignes de bit et son procede de realisation Expired - Fee Related EP1623459B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10321739A DE10321739A1 (de) 2003-05-14 2003-05-14 Bitleitungsstruktur sowie Verfahren zu deren Herstellung
PCT/EP2004/050581 WO2004102658A1 (fr) 2003-05-14 2004-04-21 Structure a lignes bits et son procede de realisation

Publications (2)

Publication Number Publication Date
EP1623459A1 true EP1623459A1 (fr) 2006-02-08
EP1623459B1 EP1623459B1 (fr) 2017-01-25

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US (2) US7687842B2 (fr)
EP (1) EP1623459B1 (fr)
JP (1) JP4459955B2 (fr)
CN (1) CN100423238C (fr)
DE (1) DE10321739A1 (fr)
WO (1) WO2004102658A1 (fr)

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EP1623459B1 (fr) 2017-01-25
CN100423238C (zh) 2008-10-01
JP2006526285A (ja) 2006-11-16
US20100129972A1 (en) 2010-05-27
US20060108692A1 (en) 2006-05-25
JP4459955B2 (ja) 2010-04-28
DE10321739A1 (de) 2004-12-09
US8193059B2 (en) 2012-06-05
US7687842B2 (en) 2010-03-30
CN1788343A (zh) 2006-06-14
WO2004102658A1 (fr) 2004-11-25

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