EP1548543B1 - Direkter digitaler Synthesizer mit niedrigem Flimmern - Google Patents

Direkter digitaler Synthesizer mit niedrigem Flimmern Download PDF

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EP1548543B1
EP1548543B1 EP04030701A EP04030701A EP1548543B1 EP 1548543 B1 EP1548543 B1 EP 1548543B1 EP 04030701 A EP04030701 A EP 04030701A EP 04030701 A EP04030701 A EP 04030701A EP 1548543 B1 EP1548543 B1 EP 1548543B1
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digital
clock
signal
output
test system
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EP1548543A1 (de
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Jason c/o Teradyne Inc. Messier
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Teradyne Inc
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Teradyne Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/03—Digital function generators working, at least partly, by table look-up
    • G06F1/0321—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
    • G06F1/0328—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers in which the phase increment is adjustable, e.g. by using an adder-accumulator
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency

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  • This invention relates generally to signal generation and more specifically to generation of periodic signals with high purity.
  • DDS Direct Digital Synthesis
  • Fig. 1 shows a traditional DDS architecture with (DDS) 100 being used to generate a sine wave that is then converted to a two-valued clock.
  • the DDS 100 receives an accumulator clock CLK ACC and a digital input signal ⁇ Inc indicating a phase increment.
  • the DDS outputs an analog signal F OUT .
  • the frequency of F OUT can be set by varying the frequency of CLK ACC and/or varying the phase increment ⁇ Inc .
  • FIG. 2 shows a block diagram of an accumulator, such as is known in the art.
  • the value in accumulator 110 serves as a control input to Sine Unit 112.
  • Sine Unit 112 converts each phase value ⁇ Acc into a corresponding amplitude value.
  • the DDS signal generator is producing a sine wave. Accordingly, the amplitudes are related to the value ⁇ Acc by the function sin ( ⁇ Acc ).
  • Sine Unit 112 might generate the required outputs using a math engine - a circuit configured to produce an output signal having a specific mathematical relationship to an input signal.
  • it is possible to implement a sine unit by pre-computing the required output value for each value of the control input. These pre-computed output values are then stored in a memory at locations addressed by the control input. In operation, the control inputs are applied as addresses to the memory, resulting in the required output value of sin ( ⁇ Acc ) being read from the memory for each of ⁇ Acc applied as an input.
  • Such a look-up table is shown in FIG. 3 .
  • the output of sine unit 112 is periodic. Periodicity is achieved because of overflow in accumulator 110.
  • the value stored in accumulator 110 increases (or decrease if negative values of ⁇ Inc are used) for every cycle of CLK ACC .
  • the value in accumulator 110 overflows (or underflows - if negative values of ⁇ Inc are used).
  • the full scale value of the accumulator is selected to correspond to a phase of 2pi radians. If the addition of ⁇ Inc would cause the value of ⁇ Acc to exceed 2pi radians by an amount x , after the overflow, the accumulator stores only the value x .
  • an overflow of the accumulator has the same effect as starting a new cycle of the periodic waveform, with the appropriate phase relationship maintained between the end of one cycle and the beginning of the next cycle.
  • the duration of one cycle of the waveform F out can be controlled by altering the time it takes for accumulator 110 to overflow. This time can be controlled by changing the frequency of clock CLK ACC . This time can also be controlled by changing the value of ⁇ Inc .
  • Digital values representing sin ( ⁇ Acc ) are then fed to a digital to analog converter, such as DAC 114 which converts them to a quantized analog signal.
  • a filter is attached to the output of the digital to analog converter to smooth out the quantized signal.
  • the filter is likely a bandpass filter because a bandpass filter that includes the desired frequency of the sine wave in its pass band will increase the "spectral purity" of the signal.
  • the analog signal may be fed to a comparator 118 to square off the signal.
  • the DDS signal generator provides a convenient mechanism to generate a clock of controlled frequency. Where the DDS signal generator is being used to generate a clock, spectral purity is also important. Lack of spectral purity in the signal F out appears as "jitter" in the digital clock. For precise measurement applications requiring a clock, low jitter is important. Therefore, it would be highly desirable to provide a DDS signal generator with high spectral purity.
  • FIG. 8 shows in greatly simplified form a block diagram of an automatic test system 800 of the type that might be used to test semiconductor chips.
  • An example of such a system is the Tiger TM test system sold by Teradyne, Inc. of Boston, MA, USA.
  • the test system includes a work station 810 that controls the test system 800.
  • Work station 810 runs test programs that set up the hardware within tester body 812 and reads back results of tests.
  • the work station also provides an interface to a human operator so that the operator can provide commands or data for testing a particular type of semiconductor device. For example a program running on work station 810 might change the frequency of a clock within the test system by changing the value of a register inside tester body 812 holding the value of ⁇ Inc .
  • Pattern generator 816 provides control inputs to the digital pins 820 and the analog instruments 818. These control inputs define both the values and the time at which test signals should be generated or measured. To ensure an accurate test, the actions of the digital pins and the analog instruments often must be synchronized. Timing generator 814 provides timing signals that synchronize operation of the various components within tester body 812.
  • AWG 822 creates a waveform that can be programmed into an almost arbitrary shape using a clock of controllable frequency.
  • a DDS signal generator 100 has been used as the clock for the AWG. The generated waveform would be more accurate if the clock provided to AWG had less jitter.
  • Digitizer 823 also relies on a clock, which should preferably be programmable. Digitizer 823 could also be made more accurate if it were provided with a clock with lower jitter.
  • DAC strongly influences the overall spectral purity of signals produced by a DDS.
  • spectral purity strongly depends on the sampling rate at which the DAC operates.
  • impurities arising from signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) decrease approximately linearly with DAC sampling rate.
  • SNR signal-to-noise ratio
  • SFDR spurious-free dynamic range
  • Disclosures US-A-4 454 498 , US-A-4 958 310 and US-A-5 467 294 illustrate a method of generating a periodic signal, the method comprising the steps of providing a plurality of streams of digital values, each value having a predetermined number of bits, and each stream representing samples of the periodic signal to be generated, of interleaving values derived from the plurality of streams to produce a final stream of digital values and of converting the final stream to an analog signal forming the periodic signal in a digital to analog converter having an input receiving said digital values.
  • the document US-A-4 454 486 relates to a signal synthesizer providing high frequency synthesized waveforms for the user.
  • a signal synthesizer providing high frequency synthesized waveforms for the user.
  • phase information By converting phase information into digital outputs in parallel and by selectively coupling these digital outputs, an ordered digital output is formed to provide the high frequency waveforms.
  • This ordered digital output which represents points on a sine function, is converted to an analog signal for the synthesizer output.
  • frequency and phase modulations of the synthesized waveforms are easily implemented with this signal synthesizer; the modulation information is simply added to the digital outputs prior to selectively coupling.
  • the analog signal contains the modulation information.
  • One aspect of the present invention is a method of generating a low jitter digital clock as defined in independent claim 1.
  • Another aspect of the invention is an automatic testing system incorporating an apparatus for generating a low jitter digital clock as defined in independent claim 11. Further embodiments of the invention are specified in the respective appended dependent claims.
  • the invention inconcerned with a DDS signal generator which generates a sine wave. This sine wave is used to create a low-jitter digital clock.
  • the DDS signal is used to generate a low-jitter digital clock of variable frequency. That clock is used within an automatic test system to clock an arbitrary waveform generator.
  • FIG. 4 shows a synthesizer 400 used to generate a low jitter digital clock.
  • Synthesizer 400 uses a modified form of direct digital synthesis.
  • synthesizer 400 is clocked by a clock CLK ACC .
  • Register 402 stores a value of ⁇ Inc .
  • the value stored in accumulator 410 increases by the value of ⁇ Inc stored in register 402.
  • accumulator fill-in unit 420 The value in accumulator 410 is fed to accumulator fill-in unit 420. Accumulator fill-in unit is shown in more detail in FIG. 5 . For each new value of ⁇ Acc , accumulator fill-in unit 420 produces N new phase values, ⁇ 0 ... ⁇ N-1 . These N phase values represent values between the value in accumulator 410 and the value that will be in the accumulator 410 when the accumulator is incremented the next time accumulator 410 is clocked by CLK ACC .
  • the values of ⁇ 0 ... ⁇ N-1 are formed by a bank of adders, of which 510, 512, 514 and 516 are shown.
  • One of the inputs to each of the adders is the value stored in accumulator 410.
  • the second input to each of the adders is based on the value of the phase increment, ⁇ Inc , stored in register 402.
  • a different fraction of the value of ⁇ Inc is input to each of the adders.
  • the adders are ordered 0...(N-1).
  • the fraction of ⁇ Inc input to each adder is based on the position of the adder in this order.
  • the first adder receives (0/N)* ⁇ Inc .
  • the next adder receives (1/N) * ⁇ Inc .
  • the pattern continues in this fashion, with the final adder in the order receiving an input of (N-1/N)* ⁇ Inc .
  • accumulator fill-in unit outputs N linearly increasing phase values.
  • the signals ⁇ 0 ... ⁇ N-1 are provided to sine bank 412.
  • Sine bank 412 can be implemented as a bank of sine units 112. Each of the sine units in sine bank 412 receives one of the signals ⁇ 0 ... ⁇ N-1 as a phase control input. Each of the sine units within sine bank 412 outputs a digital value representing a point on a sine wave. The specific point on the sine wave is controlled by the phase input applied to the specific sine unit.
  • the first control input ⁇ 0 represents the control input to a sine unit as used in a prior art DDS circuit. Accordingly, the output of the first sine unit is a value of a sine wave as in the prior art DDS circuit.
  • Each of the successive inputs ⁇ 1 ... ⁇ N-1 represents a phase that is shifted relative to ⁇ 0 . Accordingly, the output of each successive sine unit within sine bank 412 represents the value of a sine wave shifted in time relative to the value produced by the preceding sine unit in the sine bank.
  • the outputs of each of the sine units within sine bank 412 is fed to one of the switchable inputs of selector 422.
  • Selector 422 sometimes called a “multiplexer,” connects one of the switchable inputs through to its output based on the value of a control input.
  • counter 426 is a counter that counts at least from 0 to (N-1). Counter 426 either overflows to zero or is reset to zero for each cycle of CLK ACC .
  • Counter 426 is clocked by frequency multiplier 424.
  • Frequency multiplier receives an input from CLK ACC .
  • the output of frequency multiplier 424 is a higher frequency clock with a frequency that is N times the frequency of clock CLK ACC . In this way, for each cycle of clock CLK ACC , N successive values are clocked through selector 422.
  • Accumulator fill-in unit and sine bank 412 can be thought of as multiplying by N the number of samples of a sine wave available in each cycle of CLK ACC . To allow the circuitry to operate at a relatively slow speed, these samples are generated in parallel. Frequency multiplier 424, counter 426 and selector 422 convert these parallel samples of a sine wave into a stream of digital values representing one sine wave. However, the sample rate of that stream of values is increased by a factor of N.
  • DAC 414 is similar to DACs used in prior art DDS circuits. However, it needs to have a higher sampling rate to handle the higher data rate out of selector 422. By providing a data stream with a higher sampling rate to DAC, the output of DAC 414 has much greater spectral purity than signals generated by prior art DDS circuits.
  • the output of DAC 414 is shown in the embodiment of FIG. 4 to be presented to a band-pass filter 416.
  • a band-pass filter 416 can further increase spectral purity of the signal generated by DAC 414.
  • bandpass filter 416 might not be used in all implementations.
  • the output of the bandpass filter 414 is provided to comparator 418.
  • a sine wave with high purity can be used to generate a digital clock with low jitter using a comparator as shown in FIG. 4 .
  • FIG. 6 shows an alternative embodiment in which a different circuit is used to generate phase values, ⁇ 0 ... ⁇ N-1 .
  • Synthesizer 600 uses an accumulator bank 610 in place of accumulator 410 and accumulator fill-in unit 420.
  • accumulator bank 610 includes N accumulators, of which 710, 712, 714 and 716 are shown for simplicity.
  • Each of the accumulators, such as 710, 712, 714 and 716 receives the value of ⁇ Inc as an input. This value is added to the current value stored in the accumulator once for each cycle of CLK ACC .
  • each of the accumulators is initially set to values that are slightly different.
  • accumulator 710 can initially be set to 0.
  • Accumulator 712 can initially be set to (1/N)* ⁇ Inc .
  • Accumulator 714 can initially be set to (2/N)* ⁇ Inc . This pattern continues in order, with accumulator 716 being initially set to (N-1)/N* ⁇ Inc .
  • FIG. 7 shows that each of the accumulators contains a reset line. Each time the accumulators are reset, the initial value should be loaded into the circuit. It should be appreciated that an accumulator having reset circuitry that computes and loads the appropriate initial value could be constructed. The circuitry could be part of each accumulator unit. Alternatively, in a system such as automatic test system 800, a computer controller, such as work station 810, might compute the required value and store it in the accumulator register before synthesizer 600 is enabled to operate. Setup of electronic circuits before enabling them and loading values in accumulator registers are known functions of electronic circuits.
  • DAC 414 have both a high sample rate and relatively large number of bits.
  • DAC 414 will receive at least 2 Giga-values (2*10 9 ) per second. More preferably, DAC 414 will receive 4 Giga-values per second. In a presently contemplated implementation, a 4.8 Giga-Hertz DAC is used.
  • Each digital value input to DAC 414 in a presently preferred embodiment has 10 bits. It is possible, as a way to reduce the effects of computational roundoff, that the circuits generating digital values applied to DAC 414 will generate values with more bits than DAC 414 uses in a conversion. For example, each value will preferably have at least 14 bits of resolution. In a presently contemplated implementation, the generated values have 18 bits of resolution.
  • Frequency multiplier 424, counter 426 and selector 422 have components that operate at the sampling rate of DAC 414. Accordingly, relatively high frequency components are needed to implement these components. Technologies to make circuit components operate at this speed are known. For example, circuits made using an ECL or SiGe processes can operate at the required speeds. In a preferred embodiment, these components will be implemented as a single ASIC or as part of an ASIC in automatic test 800 that is used for other functions. These features could, for example, be implemented as part of the same integrated circuit chip that holds DAC 414.
  • CLK ACC will operate at a frequency less than 500 MHz. In a presently preferred embodiment, CLK ACC will operate at a frequency less than 200 MHz. These clock rates correspond to a value of N that is at least 32. In a presently preferred embodiment, N is 64.
  • CMOS complementary metal-oxide-semiconductor
  • a CMOS ASIC could be used for these components.
  • CMOS gate array could be used to implement these components.
  • the small size and relatively low power consumption of CMOS allows a synthesizer as described to be practically implemented in applications that are sensitive to size, power consumption and/or cost, such as automatic test equipment.
  • a synthesizer generates a signal with high spectral purity by creating a stream of digital values at a high rate. These values represent samples of a sine wave and serve as an input to the DAC. This stream of values is constructed by interleaving, for each period of the low frequency clock, the outputs of multiple sine units. The outputs of the sine units represent samples of sine waves, each having the same frequency as the sine wave in the interleaved data stream. However, the sampling rates of these sine waves is lower. Other implementations of a circuit that generates streams of digital values representing samples of sine waves and interleaving them would also be possible.
  • the invention is described in connection with a synthesizer that generates a sine wave that is then converted to a low jitter digital clock.
  • the invention could be used to generate a sine wave that is used for other applications.
  • the invention is illustrated as used in connection with automatic test equipment. However, the invention is applicable in any other area where sine waves of high spectral purity or digital clocks with low jitter are desired.
  • DDS can be used to generate signals other than sine waves.
  • Sine bank 412 could be replaced by a memory or math engine that implements a function other than a sine function.
  • FIG. 4 shows that each stage of synthesizer 400 is clocked, allowing for the circuit to be pipelined. It is not necessary that the circuit be pipelined.
  • the DDS circuit generates the multiple streams of digital values, each representing a sine wave offset by a uniform phase from sine waves represented by the other streams of digital values.
  • These streams of data were achieved by supplying sine bank 410 with multiple phase inputs, each offset from the other by a uniform amount.
  • the same effect could be achieved by supplying one control input to each sine unit in a sine bank, where each sine unit of the sine bank responded with a sine wave of a slightly different phase.
  • sine bank 412 might contain N memories that each stored values for a sine wave with a different phase.
  • the adders, sine units within the sine bank, and the inputs to the selector are "ordered."
  • This ordering is a "logical" ordering in the sense that the ordering is used, for example, in determining which phase input to connect to which sine unit or which sine unit to connect through to the selector output.
  • Such a logical ordering does not mean that any specific physical ordering is required when a chip containing the unit is constructed. Any convenient construction technique might be used.
  • the ordering may be established by any convenient system. For example, it is not necessary that the control input 0 to selector 422 switch the first value in the order to the output. Any numbering system or convention that preserves the desired ordering of signal may be used.
  • counter 426 is shown to be clocked by a clock that is generated in a frequency multiplier. Any convenient method of generating two clocks with a known frequency relationship might be used. For example, a higher frequency clock might be generated to clock counter 426, with CLK ACC being generated in a frequency divider having the higher frequency clock as an input. Also, though preferable, it is not strictly necessary that the clocks be generated from the same clock.
  • a sine unit could be implemented as either a look-up table or a math engine. It is also possible that a combination of look-up and computation could be used to generate the data streams that are provided by each sine unit.
  • a look-up table might have only 2 9 locations, meaning that the memory is addressed by only 9 address lines.
  • accumulator 410 might have more than 9 bits of resolution. In this case, the high order bits of the accumulator would be used to select a base value from one of the look-up tables. The low order bits of the accumulator could then be used to interpolate between the base value and the value at the next address in the memory.
  • a simple linear interpolation might be used, though other more complicated forms of interpolation could be constructed.
  • a DSS synthesizer is used to generate a sine wave of high spectral purity.
  • the same circuitry could be used to generate a sine wave at a higher frequency than is possible with a traditional DDS circuit.
  • the frequency of a generated sine wave is limited to 1 ⁇ 2 the frequency of CLK ACC .
  • the frequency of the generated sine wave is limited at Nx1/2 the frequency of CLK ACC .

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Claims (26)

  1. Ein Verfahren zum Erzeugen eines digitalen Taktes (FOUT) mit niedrigem Jitter bzw. niedriger Schwankung, wobei das Verfahren Folgendes aufweist:
    a) Vorsehen einer Vielzahl von Strömen von digitalen Werten, wobei jeder Wert eine vorherbestimmte Anzahl von Bits besitzt und jeder Strom Samples bzw. Abtastwerte von einem zu erzeugenden periodischen Signal repräsentiert;
    b) Interleaven bzw. Verschachteln von Werten, die aus der Vielzahl von Strömen abgeleitet sind um einen finalen Strom von digitalen Werten zu erzeugen;
    c) Konvertieren des finalen Stroms in ein analoges Signal in einem Digital-zu-Analog-Konverter (414) der einen Eingang besitzt, der digitale Werte empfängt mit weniger als der vorherbestimmten Anzahl von Bits; und
    d) Erzeugen des digitalen Taktes aus dem analogen Signal.
  2. Verfahren nach Anspruch 1, das zusätzlich Erzeugen einer Vielzahl von Phasensignalen aufweist, wobei jedes Werte besitzt mit einer Periode, die proportional zu der Periode des periodischen Signals ist, wobei jeder Wert in der Vielzahl von Strömen von digitalen Werten ansprechend auf einen Wert von einem Phasensignal von einer Vielzahl von Phasensignalen vorgesehen ist.
  3. Verfahren nach Anspruch 2, das zusätzlich Erzeugen jedes Phasensignals durch wiederholtes Erhöhen jedes Phasensignals von der Vielzahl von Phasensignalen um ein Phaseninkrement aufweist.
  4. Verfahren nach Anspruch 3, das zusätzlich Steuern der Periode des periodischen Signals durch Ändern des Phaseninkrements aufweist.
  5. Verfahren nach Anspruch 1, wobei das Konvertieren des analogen Signals in einen digitalen Takt verarbeiten des analogen Signals in einem Komparator zum Vorsehen des digitalen Taktes aufweist.
  6. Verfahren nach Anspruch 5, das zusätzlich Nutzen des digitalen Taktes für eine Schaltung die eine Wellenform erzeugt, aufweist.
  7. Verfahren nach Anspruch 1, wobei der finale Strom von digitalen Werten mehr als 4 Giga-Werte pro Sekunde aufweist.
  8. Verfahren nach Anspruch 7, wobei jeder der Vielzahl von Strömen von digitalen Werten weniger als 500 Mega-Werte pro Sekunde aufweist.
  9. Verfahren nach Anspruch 7, wobei jeder der digitalen Werte in dem finalen Strom wenigstens 12 Bit an Auflösung besitzt.
  10. Verfahren nach Anspruch 1, wobei die Vielzahl von Strömen von digitalen Werten wenigstens 32 Ströme von digitalen Werten aufweist.
  11. Ein automatisches Testsystem (800), das Folgendes aufweist:
    a) einen Timing- bzw. Zeitsteuerungsgenerator (814) der ein erstes Uhr- bzw. Taktsignal vorsieht;
    b) wenigstens eine digitale Pinschaltung (820), die mit dem Timing-Generator (814) gekoppelt ist, und ein digitales Testsignal zu Zeiten, die durch das erste Taktsignal synchronisiert sind, erzeugt oder misst; und
    c) wenigstens ein analoges Instrument (818), das mit dem Timing-Generator gekoppelt ist, wobei das analoge Instrument ein analoges Signal erzeugt oder misst, und zwar zu Zeiten, die referenziert bzw. bezogen sind, auf einen, einen niedrigen Jitter aufweisenden digitalen Takt von einer programmierbaren Frequenz, die mit dem ersten Taktsignal synchronisiert ist, wobei das analoge Instrument eine Einrichtung aufweist, zum Erzeugen des Taktes mit niedrigem Jitter, wobei die Vorrichtung Folgendes aufweist:
    I) eine Schaltung (424) um aus dem ersten Taktsignal (CLKACC) ein zweites Taktsignal (CLKDAC) zu erzeugen, das eine Frequenz besitzt, die ein Vielfaches von dem ersten Taktsignal ist;
    II) eine Vielzahl von Schaltungen (410, 420, 412, 610, 612) die jeweils einen Steuereingang, einen Takteingang der mit dem ersten Taktsignal getaktet ist und einen Ausgang besitzen, wobei jede Schaltung einen Wert an ihrem Ausgang erzeugt, der ein Sample bzw. eine Tastung von einem analogen Signal repräsentiert und zwar zu einer Zeit, die durch ihren Steuereingang bestimmt ist, wobei jeder Wert eine vorher bestimmte Anzahl von Bits besitzt;
    III) eine Selektorschaltung (422) die eine Vielzahl von schaltbaren Eingängen besitzt, wobei jeder der schaltbaren Eingänge mit dem Ausgang von einer von der Vielzahl von Schaltungen verbunden ist, und einen Steuereingang besitzt, der mit dem zweiten Taktsignal getaktet wird, wobei die Selektorschaltung einen anderen von ihren schaltbaren Eingängen mit ihrem Ausgang verbindet, wenn ihr Steuereingang mit dem zweiten Taktsignal getaktet wird;
    IV) einen Digital-zu-Analog-Konverter (414), der einen digitalen Eingang, der mit dem Ausgang der Selektorschaltung gekoppelt ist und einen analogen Ausgang der repräsentativ für das periodische Signal ist, besitzt, wobei der digitale Eingang digitale Werte mit weniger als der vorher bestimmten Anzahl von Bits empfängt; und
    V) Mittel (418) zum Erzeugen des digitalen Taktes aus dem analogen Signal.
  12. Automatisches Testsystem nach Anspruch 11, wobei das zweite Taktsignal eine Frequenz besitzt, die wenigstens 32 Mal die Frequenz des ersten Taktsignals ist.
  13. Automatisches Testsystem nach Anspruch 11, wobei die Vielzahl von Schaltungen CMOS Schaltungen sind.
  14. Automatisches Testsystem nach Anspruch 11, wobei die Vielzahl von Schaltungen in einem einzelnen Gatter Array Chip implementiert sind.
  15. Automatisches Testsystem nach Anspruch 11, das zusätzlich ein Filter (416) aufweist, das mit dem Ausgang des Digital-zu-Analog-Konverters gekoppelt ist.
  16. Automatisches Testsystem nach Anspruch 15, das zusätzlich einen Komparator (418) aufweist, der mit dem Ausgang des Filters gekoppelt ist.
  17. Automatisches Testsystem nach Anspruch 16, wobei das analoge Instrument einen Arbitrary Waveform Generator bzw. einen Generator für frei wählbare Wellenformen aufweist, wobei der Arbitrary Waveform Generator einen Takteingang besitzt, der von einem Ausgang des Komparators abgeleitet ist.
  18. Automatisches Testsystem nach Anspruch 17, wobei das zweite Taktsignal eine Frequenz besitzt, die wenigstens 4 GHz beträgt.
  19. Automatisches Testsystem nach Anspruch 11, wobei jede von der Vielzahl von Schaltungen, eine Vielzahl von Akkumulatoren aufweist, wobei jeder Akkumulator durch das erste Taktsignal getaktet wird.
  20. Automatisches Testsystem nach Anspruch 19, wobei jeder Akkumulator einen Eingang aufweist, der mit einem programmierbaren Register gekoppelt ist.
  21. Automatisches Testsystem nach Anspruch 11, wobei jede der Vielzahl von Schaltungen einen Speicher aufweist.
  22. Automatisches Testsystem nach Anspruch 21, wobei jeder von den Speichern in der Vielzahl von Schaltungen Samples bzw. Tastungen von einer Sinus-Welle speichert.
  23. Automatisches Testsystem nach Anspruch 11, wobei:
    I) die Schaltung (424) zum Erzeugen einen Frequenz-Multiplizierer (424) aufweist, der angepasst ist und angeordnet ist zum Empfangen des ersten Taktsignals als eine Eingabe und zum Erzeugen des zweiten Taktsignals als eine Ausgabe,
    II) die Vielzahl von Schaltungen eine Vielzahl von Akkumulatoren (410, 420, 610) aufweist, von denen jeder einen Speicherplatz und Schaltkreise besitzt, zum Addieren eines vorher bestimmten Betrags zu dem Wert in dem Speicherplatz während jedes Zykluses von dem ersten Taktsignal; und
    eine Vielzahl von Speichern (412) aufweisen, die einen Adresseingang und einen Datenausgang besitzen, wobei der Adresseingang von jedem von den Speichern mit einem von den Akkumulatoren verbunden ist, jeder von den Speichern, die Ausgabe ansprechend auf den Wert des Adresseingangs für jeden Zyklus von dem ersten Takt erzeugt;
    III) jeder von den schaltbaren Eingängen mit dem Datenausgang von einem von der Vielzahl von Speichern verbunden ist.
  24. Automatisches Testsystem nach Anspruch 23, das zusätzlich ein Filter (416) aufweist, das mit dem Ausgang von dem Digital-zu-Analog-Konverter (414) verbunden ist.
  25. Automatisches Testsystem nach Anspruch 24, wobei die Mittel einen Komparator (418) aufweisen, der mit dem Ausgang des Digital-zu-Analog-Konverters gekoppelt ist, wobei der Komparator einen Ausgang besitzt, der den digitalen Takt vorsieht.
  26. Automatisches Testsystem nach Anspruch 25, wobei das analoge Instrument, ein Arbitrary Waveform Generator (822) bzw. Generator mit freiwählbarer Wellenform ist.
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US7327816B2 (en) 2008-02-05
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CN1638263B (zh) 2010-06-16
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TW200521647A (en) 2005-07-01
JP4808398B2 (ja) 2011-11-02
DE602004011744T2 (de) 2009-02-12
US20050135524A1 (en) 2005-06-23
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JP2005195585A (ja) 2005-07-21
TWI260480B (en) 2006-08-21

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