EP1536482A1 - Transistor à couche mince à profil conique - Google Patents

Transistor à couche mince à profil conique Download PDF

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Publication number
EP1536482A1
EP1536482A1 EP04090476A EP04090476A EP1536482A1 EP 1536482 A1 EP1536482 A1 EP 1536482A1 EP 04090476 A EP04090476 A EP 04090476A EP 04090476 A EP04090476 A EP 04090476A EP 1536482 A1 EP1536482 A1 EP 1536482A1
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EP
European Patent Office
Prior art keywords
thin film
film transistor
gate insulating
insulating layer
lower pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP04090476A
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German (de)
English (en)
Inventor
Eui-Hoon c/o Samsung SDI Co. Ltd. Hwang
Sang-Gul c/o Samsung SDI Co. Ltd. Lee
Deuk-Jong c/o Samsung SDI Co. Ltd. Kim
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Samsung SDI Co Ltd
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Samsung SDI Co Ltd
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Filing date
Publication date
Application filed by Samsung SDI Co Ltd filed Critical Samsung SDI Co Ltd
Publication of EP1536482A1 publication Critical patent/EP1536482A1/fr
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

Definitions

  • the present invention relates to a thin film transistor and, more particularly, to a thin film transistor with improved dielectric strength in a gate insulating layer.
  • a thin film transistor includes a semiconductor layer, a gate electrode, source/drain electrodes and a gate insulating layer interposed between the semiconductor layer and the gate electrode.
  • the threshold voltage of the thin film transistor has a close relationship with the thickness of the gate insulating layer, thus the gate insulating layer should be thinner to reduce the threshold voltage.
  • the dielectric strength of the gate insulating layer refers to the maximum electric field that the gate insulating layer can withstand without breakdown.
  • breakdown may occur. This may cause operational defects in the performance of the thin film transistor, and a corresponding display defect in a display device using the thin film transistor.
  • Korean Patent Application No.1994-035626 discloses a method of depositing an oxide layer by low temperature CVD and then performing heat-oxidization.
  • heat-oxidization in such a case requires a high temperature, thus disadvantageously requiring an expensive quartz substrate.
  • the present invention provides a thin film transistor with improved dielectric strength of a gate insulating layer.
  • the thin film transistor may include a gate insulating layer and a lower pattern placed below the gate insulating layer in contact therewith and having an edge with a taper angle of 80° or less.
  • the taper of the edge of the lower pattern may have an angle of at least 30°. More preferably, the taper of the edge of the lower pattern may have an angle of 60° to 75°.
  • the gate insulating layer be made of a silicon oxide layer. Further, it may be preferable that the gate insulating layer be formed by plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • the lower pattern can be a semiconductor layer.
  • the lower pattern can be a gate electrode.
  • the gate electrode has a thickness of between about 500 and about 3000 A.
  • FIG. 1 is a plan view showing a typical top-gate thin film transistor.
  • FIGs. 2A and 2B are cross-sectional views for illustrating a top-gate thin film transistor during fabrication according to an embodiment of the present invention taken along the lines I-I' and II-II' of FIG. 1, respectively.
  • FIG. 3 is a cross-sectional view for illustrating a bottom-gate thin film transistor and method of fabricating the same according to another embodiment of the present invention.
  • FIGs. 4A, 5A, 6A, and 7A are pictures showing an edge of a semiconductor layer of a thin film transistor according to examples 1 and 2 and comparative examples 1 and 2, respectively.
  • FIGs. 4B, 5B, 6B and 7B are graphs showing dielectric strength properties of a gate insulating layer in a thin film transistor according to examples 1 and 2 and comparative examples 1 and 2, respectively.
  • a semiconductor layer 120 may be placed in one direction, and a gate electrode 140 crossing the semiconductor layer 120 may be placed on the semiconductor layer 120.
  • a gate insulating layer (not shown) may be placed between the semiconductor layer 120 and the gate electrode 140.
  • Source/drain electrodes 160 may be located on both ends of the semiconductor layer 120.
  • a substrate 100 may be provided, and preferably, a buffer layer (not shown) may be formed on the substrate 100.
  • the buffer layer may protect the active portions of the thin film transistor from impurities emitted from the substrate 100 during subsequent processing.
  • the buffer layer can be formed of, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a stacked layer thereof.
  • the amorphous layer may be crystallized by excimer laser annealing (ELA), sequential lateral solidification (SLS), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), or the like.
  • ELA excimer laser annealing
  • SLS sequential lateral solidification
  • MILC metal induced lateral crystallization
  • Such a method may form a polysilicon layer. It may be preferable that the polysilicon is between about 300 and about 1000 ⁇ thick.
  • a photoresist pattern may be formed on the polysilicon layer, and (using the photoresist pattern as a mask) the polysilicon layer may be etched to form a semiconductor layer 120.
  • the semiconductor layer 120 may be formed to have a tapered edge, wherein the taper of the edge may have an angle of 80° or less.
  • the etching of the polysilicon layer may be performed by dry etching, which has an excellent etch uniformity and a low etch CD loss.
  • the semiconductor layer 120 having the tapered edge may be formed using a mixed gas of O 2 and SF 6 as an etch gas.
  • the O 2 may serve to etch the side of the photoresist pattern as the SF 6 etches the silicon. This may accordingly permit the semiconductor layer 120 to be formed with a tapered edge.
  • the taper angle of the edge in the semiconductor layer 120 can be adjusted by the flow rate/volume ratio of the O 2 and the SF 6 .
  • a gate insulating layer 130 that covers the semiconductor layer 120 may be formed on the semiconductor layer 120.
  • the gate insulating layer 130 can be formed of, for example, a silicon oxide layer or a silicon nitride layer. However, it may be preferable that the gate insulating layer 130 be formed of a silicon oxide layer, because of its good dielectric strength.
  • the gate insulating layer 130 is formed by low temperature PECVD, although other techniques may be used.
  • the semiconductor layer 120 may be formed to have a tapered edge of 80° or less. This choice of taper angles may help to prevent the phenomenon in which a deposited gate insulating layer 130 becomes thinner at the sides of the semiconductor layer 120. When the gate insulating layer 130 becomes thinner at the side of the semiconductor layer 120, the gate insulating layer 130 can exhibit dielectric breakdown where it is thin. Consequently, the semiconductor layer 120 may be formed to have a tapered edge of 80° or less, and the gate insulating layer 130 can be uniformly formed on the top and side of the semiconductor layer 120. Therefore, the dielectric strength of the gate insulating layer 130 can be improved.
  • the taper angle of the edge in the semiconductor layer 120 be about 30° or greater.
  • the resistance of the semiconductor 120 may increase due to the thin edge below 30°. This can yield an increase in resistance of a channel formed in the semiconductor layer 120.
  • the taper angle of the edge in the semiconductor 120 may be between about 60° and about 75°.
  • a gate electrode material may be deposited on the gate insulating layer 130, and may be patterned to form a gate electrode 140. Then impurities may be implanted into the semiconductor layer 120 using the gate electrode 140 as a mask. Thus, source/drain regions 120a may be formed in the semiconductor layer 120. A region between the source/drain regions 120a may define a channel region 120b.
  • an interlayer 150 that covers the entire surface of the substrate having the gate electrode 140 may be formed, and source/drain contact holes 150a that each expose one of the source/drain regions 120a may be formed in the interlayer 150.
  • Source/drain electrode materials may be deposited on the substrate where the source/drain contact holes 150a are formed. Patterned this way, source/drain electrodes 160 that respectively contact with the source/drain regions 120a through the source/drain contact holes 150a may be formed.
  • FIG. 3 is a cross-sectional view for illustrating a bottom-gate thin film transistor and a method for fabricating the same according to another embodiment of the present invention.
  • a substrate 300 may be provided.
  • a gate electrode material may be deposited on the substrate 300 and a photoresist pattern (not shown) may be formed on the deposited gate electrode material.
  • the gate electrode material may be etched to form a gate electrode 320.
  • the gate electrode 320 may be formed to have a tapered edge with an angle of about 80° or less.
  • the etching of the gate electrode material may be performed by a dry etching method, with excellent etch uniformity and a low etch CD loss.
  • the O 2 may serve to etch the side of the photoresist pattern. This may permit the layer to have a tapered edge.
  • the taper angle of the edge in the gate electrode 320 can be adjusted by controlling the flow rate/volume ratio of the O 2 and the SF 6 .
  • the gate electrode 320 be between about 500 and about 3000A thick, when balancing resistance properties and etch CD loss of the gate wiring simultaneously formed with the gate electrode 320.
  • a gate insulating layer 330 may be deposited on the gate electrode 320.
  • the gate insulating layer 330 can be formed of, for example, a silicon oxide layer or a silicon nitride layer.
  • the gate insulating layer 330 may be formed using a silicon oxide layer.
  • the gate electrode 320 may be formed to have a tapered edge of about 80° or less. This may alleviate the problem of the gate insulating layer 330 becoming too thin at the edges of the gate electrode 320. When the gate insulating layer 330 becomes thinner at the side of the gate electrode 320, the gate insulating layer 330 can exhibit dielectric breakdown where it is thin. Consequently, the gate electrode 320 may have a tapered edge of 80° or less, so that the gate insulating layer 330 can be uniformly formed on the top and side of the gate electrode 320. Thus, the dielectric strength of the gate insulating layer 330 can be improved.
  • the taper of the edge in the gate electrode 320 has an angle of 30° or more, for the same reasons as in the previous embodiment.
  • a semiconductor layer and an ohmic contact layer may be sequentially formed on the gate insulating layer 330.
  • the semiconductor layer be formed of amorphous silicon, and the ohmic contact layer may be a region of amorphous silicon where impurities are doped.
  • the semiconductor layer may be crystallized by ELA, SLS, MIC, MILC, or the like to form a polysilicon layer.
  • the ohmic contact layer and the semiconductor layer may be sequentially patterned to form a semiconductor layer pattern 340 and an ohmic contact layer pattern 350.
  • the semiconductor layer pattern 340 may be formed to cover the gate electrode 320.
  • source/drain electrode materials may be deposited on the ohmic contact layer pattern 350, and may be patterned to form source/drain electrodes 360.
  • the semiconductor layer pattern 340 may be exposed between the source/drain electrodes 360.
  • An amorphous silicon layer was formed on an insulating substrate, and was patterned to form a polysilicon layer to a thickness of 500 ⁇ .
  • a photoresist pattern was formed on the polysilicon layer.
  • the polysilicon layer was etched using the photoresist pattern as a mask to form the semiconductor layer.
  • the polysilicon was etched using SF 6 /O 2 gas with a ratio of 120/180sccm to form a semiconductor layer.
  • a silicon oxide layer was PECVD deposited to a thickness of 1000 A on the semiconductor layer to form a gate insulating layer.
  • a gate electrode was formed on the gate insulating layer, thereby fabricating the example thin film transistor.
  • a thin film transistor was fabricated in the same manner as the example 1 except that the polysilicon layer was etched using SF 6 /O 2 gas with a ratio of 150/150sccm.
  • the taper R of the edge in the semiconductor layer has an angle of about 78°.
  • the taper S of the edge in the semiconductor layer has an angle of about 60°.
  • the taper T of the edge in the semiconductor layer has an angle of about 82°.
  • the taper U of the edge in the semiconductor layer has an angle of about 90°.
  • FIGs. 4B, 5B, 6B and 7B are graphs showing the dielectric strength of a gate insulating layer in a thin film transistor according to examples 1 and 2 and comparative examples 1 and 2, respectively.
  • the X axis indicates the electric field (MV/cm) between the gate electrode and the semiconductor layer
  • the Y axis indicates the leakage current (A) measured at the gate electrode.
  • the leakage current remains almost constant (at about 1x10 -12 A) until the electric field between the gate electrode and the semiconductor layer reaches about 5MV/cm.
  • the dielectric strength of the gate insulating layer in the thin film transistor according to examples 1 and 2 is well enhanced.
  • the gate leakage current shows a drastic increase when the electric field between the gate electrode and the semiconductor layer exceeds 2MV/cm. This indicates dielectric breakdown in the gate insulating layer. Such a breakdown can lead to a malfunction of the thin film transistor. It can also lead to a display defect in a display device that uses the thin film transistor. The likely defects under such circumstances may include a point defect, a line defect, or brightness nonuniformity.
  • the lower pattern of the gate insulating layer may have an edge with a taper angle 80° or less, so that the dielectric strength of the gate insulating layer can be improved. Consequently, malfunction of the thin film transistor and (when the thin film transistor is employed in a display device) display defects can be prevented.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
EP04090476A 2003-11-28 2004-11-29 Transistor à couche mince à profil conique Ceased EP1536482A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020030085848A KR20050052029A (ko) 2003-11-28 2003-11-28 박막트랜지스터
KR2003085848 2003-11-28

Publications (1)

Publication Number Publication Date
EP1536482A1 true EP1536482A1 (fr) 2005-06-01

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EP04090476A Ceased EP1536482A1 (fr) 2003-11-28 2004-11-29 Transistor à couche mince à profil conique

Country Status (5)

Country Link
US (1) US20050116305A1 (fr)
EP (1) EP1536482A1 (fr)
JP (1) JP2005167207A (fr)
KR (1) KR20050052029A (fr)
CN (1) CN1622341A (fr)

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US7851277B2 (en) 2006-12-05 2010-12-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing same
US7859055B2 (en) 2005-09-16 2010-12-28 Sharp Kabushiki Kaisha Thin film transistor
US7968884B2 (en) 2006-12-05 2011-06-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US8067772B2 (en) 2006-12-05 2011-11-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US8476744B2 (en) 2009-12-28 2013-07-02 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor with channel including microcrystalline and amorphous semiconductor regions
US8575608B2 (en) 2009-12-21 2013-11-05 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor and manufacturing method thereof
US8581260B2 (en) 2007-02-22 2013-11-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including a memory
US8704230B2 (en) 2010-08-26 2014-04-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US8829522B2 (en) 2009-12-21 2014-09-09 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor
US8853782B2 (en) 2006-12-05 2014-10-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9230826B2 (en) 2010-08-26 2016-01-05 Semiconductor Energy Laboratory Co., Ltd. Etching method using mixed gas and method for manufacturing semiconductor device

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JP2006332172A (ja) * 2005-05-24 2006-12-07 Mitsubishi Electric Corp 半導体装置及び半導体装置の製造方法
EP2259294B1 (fr) 2006-04-28 2017-10-18 Semiconductor Energy Laboratory Co, Ltd. Dispositif semiconducteur et son procédé de fabrication
JP5266645B2 (ja) * 2007-01-31 2013-08-21 三菱電機株式会社 薄膜トランジスタと該薄膜トランジスタを用いた表示装置
US8420456B2 (en) 2007-06-12 2013-04-16 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing for thin film transistor
KR101282897B1 (ko) * 2008-07-08 2013-07-05 엘지디스플레이 주식회사 폴리실리콘 박막트랜지스터 및 그 제조방법
US20110227075A1 (en) * 2008-12-05 2011-09-22 Dupont Displays, Inc. Backplane structures for solution processed electronic devices
KR20110106334A (ko) * 2008-12-05 2011-09-28 이 아이 듀폰 디 네모아 앤드 캄파니 용액 처리된 전자 소자용 백플레인 구조물
JP2010245366A (ja) * 2009-04-08 2010-10-28 Fujifilm Corp 電子素子及びその製造方法、並びに表示装置
WO2012008917A1 (fr) * 2010-07-15 2012-01-19 Lip Sing Leng Système piste de distribution d'énergie électrique
CN102646592B (zh) * 2011-05-03 2014-12-03 京东方科技集团股份有限公司 薄膜场效应晶体管器件及其制备方法
US9496415B1 (en) 2015-12-02 2016-11-15 International Business Machines Corporation Structure and process for overturned thin film device with self-aligned gate and S/D contacts
KR20180078018A (ko) * 2016-12-29 2018-07-09 엘지디스플레이 주식회사 전계 발광 표시 장치 및 그 제조 방법

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