EP1518274A1 - Composant electronique presentant une plaque de recablage multicouche et procede pour produire ce composant electronique - Google Patents

Composant electronique presentant une plaque de recablage multicouche et procede pour produire ce composant electronique

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Publication number
EP1518274A1
EP1518274A1 EP03761442A EP03761442A EP1518274A1 EP 1518274 A1 EP1518274 A1 EP 1518274A1 EP 03761442 A EP03761442 A EP 03761442A EP 03761442 A EP03761442 A EP 03761442A EP 1518274 A1 EP1518274 A1 EP 1518274A1
Authority
EP
European Patent Office
Prior art keywords
electronic component
shielding
chip
rewiring plate
structured
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03761442A
Other languages
German (de)
English (en)
Inventor
Jochen Thomas
Ingo Wennemuth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1518274A1 publication Critical patent/EP1518274A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H10W42/281—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their materials
    • H10W42/287—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their materials materials for magnetic shielding, e.g. ferromagnetic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/453—Leadframes comprising flexible metallic tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/077—Connecting of TAB connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/701—Tape-automated bond [TAB] connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/865—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the invention relates to an electronic component with a multilayer rewiring plate, which carries a circuit chip, in particular a magnetic memory chip, and a method for producing the same.
  • Electronic components with a semiconductor chip are particularly at risk from magnetic fields from the area surrounding the electronic components, such as transformers, power supply units, fan motors and the like, and unintended switching processes can be triggered in the circuit chips.
  • Magnetic interference of just a few tenths of Oerstedt can trigger malfunctions, especially since the threshold values for a logical zero and a logical one are constantly minimized with increasing miniaturization of the circuit cells.
  • electronic components based on flat lead frames have a limited protective effect due to the metallic structures, this is completely eliminated in the case of electronic components based on BGA-type housings (ball grid array type).
  • Shields based on Permalloy or Alloy 42 have the disadvantage of a high remanence for shielding large devices, so that these materials behave like a permanent magnet, that is, after they have been exposed to a magnetic field, they form a permanent own magnetic field and can thus impair the long-term functionality of electronic components with a circuit chip. Therefore the use of flat cables Terrahmen made of such materials or shielding housings made of materials with high remanence reverse the intended shielding effect for electronic components with a circuit chip in the opposite way, so that the circuit chip is permanently damaged by a residual magnetic field due to the high remanence of these materials.
  • the object of the invention is to provide an electronic component which has a structure which protects the circuit chip from magnetic interference fields and reduces malfunctions due to magnetic interference in the range of several Oerstedt without restricting the functionality of the electronic component.
  • an electronic component with a multilayer rewiring plate is specified, which one
  • Circuit chip in particular carries a magnetic memory chip.
  • the rewiring plate has rewiring lines that connect contact areas of the chip to external contacts of the electronic component.
  • At least one of the structured layers of the multilayer rewiring plate is a magnetic shielding layer, which has an amorphous metal or an amorphous metal alloy.
  • Such a shielding layer made of an amorphous metal or an amorphous metal alloy is mechanically extremely hard and gives the rewiring plate a high dimensional stability.
  • amorphous magnetic metals or amorphous magnetic metal alloys are soft magnetic, which partly has that these materials can not be polarized by a magnetic field and thus do not form a permanent magnet effect.
  • the arrangement of the amorphous metal or the amorphous metal alloy as a layer of a rewiring plate means that the magnetic shielding layer can be arranged in the immediate vicinity of the circuit chip to be protected without changing or adapting the manufacturing process for the circuit chip itself. Only a further structured layer has to be provided in the multilayer rewiring board.
  • the measure of integrating a magnetically shielding amorphous metal or an amorphous metal alloy as a further layer in a multilayer rewiring plate protects circuit chips with magnetic memory cells from magnetic interference fields in particular.
  • MRAM Magnetic Random Access Memories
  • TMR Tunnelneling Magneto-Resistive
  • GMR Giant-Magneto-Resistive
  • a soft or hard magnetic layer is connected either in parallel or antiparallel, a parallel connection means a low volume resistance and an antiparallel circuit means a high volume resistance, so that the memory function zero and one can be implemented.
  • the soft magnetic layer serves as a switch and the hard magnetic layer as the reference layer.
  • the soft magnetic layer serves as a switch and the hard magnetic layer as the reference layer.
  • only limited high currents are available for switching the soft magnetic layer, so that the coercive field strength must be kept as low as possible.
  • These switching states in the soft magnetic layer are therefore extremely susceptible to faults and malfunctions of such MRAM components are already observed in magnetic fields of a few tenths of Oerstedt.
  • the multilayer rewiring plate according to the invention which has a magnetic shielding layer made of an amorphous ferromagnetic metal or an amorphous ferromagnetic metal alloy, interference fields from several Oerstedt in the vicinity of the electronic component can be caused by transformers, power supply units or blower motors , be shielded.
  • the rewiring plate according to the invention in electronic components with magnetic memory cells is particularly effective and the functionality of such electronic components is only ensured without large shielding housings being provided for such electronic components, such a multilayer rewiring plate can also be advantageous for circuit chips, the conventional memory cells exhibit or are also used for logic chips, especially since due to the electrical conductivity of these amorphous metals there is also a shielding effect against electromagnetic interference fields which can influence the storage and switching functions.
  • the magnetic shielding layer is adapted in its structure to the rewiring plate for the different circuit types.
  • a structured shielding film with a thickness between 20 and 75 micrometers can be used as the shielding layer.
  • Such shielding films of amorphous ferromagnetic Me ⁇ metals or metal alloys are manufactured in strip form and are particularly suitable for laminating to the insulation core of a rewiring. All you have to do is Ribbon can be structured from amorphous metal and can be laminated for several electronic component positions of a rewiring plate of a panel.
  • the shielding layer can also have a plurality of structured shielding foils stacked and laminated on one another. By laminating several shielding foils on top of one another, any desired shielding factor can be achieved, which is between 50 and 100 for the electronic component according to the invention.
  • the amorphous metals have at least one of the ferromagnetic materials cobalt, nickel or iron. Boron serves as an alloy additive, which promotes amorphous solidification of the ferromagnetic metals, so that the crystalline fractions in the magnetic shielding foil are negligible.
  • the saturation induction is achieved at values between 0.5 and 1 Tesla, with a saturation magnet restriction smaller than 0.2 x 10 ⁇ 6 .
  • the magnetic shielding layer of the multilayer rewiring plate is mechanically extremely dimensionally stable and magnetically effective.
  • the Curie temperature is between 200 ° C and 500 ° C, so that the shielding effect is not destroyed even during temperature change tests of the electronic components, which are carried out between -50 ° C and 150 ° C.
  • the structured shielding layer can be arranged on the outside of the rewiring plate, which lies opposite the circuit chip.
  • the shielding layer in the form of a shielding film has at least openings for the external, arranged in a predetermined grid dimension in a ring shape or in a matrix contacts. Even a shielding layer structured in this way prevents interference fields from reaching through to the circuit chip and, because of the soft magnetic properties of the amorphous metal layer, ensures that the electronic component does not function without restrictions.
  • the structured shielding layer can also be arranged closer to the chip side by laminating the structured shielding layer on the chip side of the rewiring board.
  • the structured shielding layer has openings for corresponding bond contact areas.
  • the structured shielding layer can be arranged both on the chip side and on the outside of the rewiring plate without changing the structure, as long as the shielding layer has at least one bond channel opening in the order of magnitude of the bond channel of the circuit or memory chip.
  • additional openings can be provided for exposing external contact areas.
  • the shielding layer on the outside of the rewiring plate has only one bond channel opening and the surface of the shielding layer is covered on the outside by an insulating layer, which in turn contains the rewiring lines and the external contact areas for a connection between the contact surfaces of the circuit chip and has the external contacts.
  • This alternative has a shielding layer directly on the outside of the electronic component Advantage that there are no precise openings for exposing external contact surfaces.
  • the shielding effect of the shielding foils made of amorphous metals or metal alloys can be enhanced by the fact that, in addition to the rewiring plate, the entire surface of the circuit chip has a shielding foil made of amorphous metals or metal alloys on its passive back.
  • a method for producing an electronic component that has a multilayer rewiring plate that carries at least one circuit chip and connects contact areas of the circuit chip via rewiring lines of the rewiring plate to external contacts of the electronic component has the following method steps:
  • a shielding film made of amorphous metal or an amorphous metal alloy is structured for a benefit with multiple component positions.
  • the structured shielding film is then laminated onto the rewiring plate of the panel.
  • circuit chips are applied in the component positions of the rewiring plate of the panel and electrically connected to the rewiring plate.
  • the entire benefit is then covered with a plastic filled house mass by embedding the circuit chips and the electrical connections.
  • the underside or outside, which has external contact surfaces, remains free of plastic housing compound.
  • external contacts can be applied to the external contact surfaces on the entire panel in the respective component positions of the panel. After the external contacts have been attached, the benefits can be separated into individual electronic components. To round off or deburr the edges of the plastic housing compound, profile saws can be used when separating the component positions of the
  • This method has the advantage that individual electronic components are produced, the rewiring plate of which is multi-layered and has at least one shielding layer made of an amorphous metal or an amorphous metal alloy.
  • This amorphous metal or amorphous metal alloy has a magnetic and electromagnetic shielding and protective function for the functions of the circuit chip within the electronic component, without the need for an external shielding housing. Due to the soft magnetic properties of the ferromagnetic amorphous metals or metal alloys, an improved magnetic shielding for alternating fields is achieved.
  • This shielding layer can effectively shield critical magnetic fields from transformers, power supplies or blower motors in the low-frequency range without the magnetic shielding layer made of amorphous metals or amorphous metal alloys itself being magnetized in the long term, since the soft magnetic material of amorphous metals has a low remanence.
  • the shielding film can be structured by punching predetermined patterns of openings. Thus, for each component position in the case of circuit chips or chips with magnetic memory cells, an elongated bond channel can be introduced or punched out in the shielding film, which is adapted to the arrangement of the contact areas on the memory chip. If, on the other hand, the shielding film is applied or arranged on the outermost side of the rewiring plate, additional openings are provided for exposing or releasing the external contact areas, to which external contacts are applied in a later step.
  • the shielding film can also be structured by means of laser ablation or laser ablation, a laser beam being scanned over each of the component positions of a shielding film for a benefit in such a way that correspondingly adapted openings are created.
  • individual openings arranged in a ring are to be provided, which release bond contact areas on the rewiring plate when the shielding layer or shielding film is arranged on the chip side of the rewiring plate. If, on the other hand, the shielding film is provided for the outside of the rewiring plate, openings for a matrix of external contact areas are to be provided accordingly, the
  • edges or walls of these openings must also be protected from short circuits with a solder mask.
  • a shielding film structured and prepared in this way can then either be applied directly to the insulation body of the rewiring plate or if this body already has rewiring lines, a thin insulation layer is first applied or Laminating an insulating adhesive is used so that the applied rewiring lines are not short-circuited by the shielding film.
  • This insulating layer can also have already been deposited on the shielding film, for which purpose magnesium oxides or silicon oxides or silicon nitride are preferably used. This deposition directly on the shielding film can also take place before the structuring of the shielding film in a sputtering system.
  • either the thickness of the shielding film can be varied between 20 and 75 micrometers, or several shielding films can also be laminated onto one another. Since magnetostriction is negligibly small with amorphous metals, laminating shielding foils together is not critical.
  • the effect of the shielding can also be increased by additionally providing either the back of the circuit chip or the active front of the circuit chip with a shielding film. It should be noted, however, that the back can be covered by a shielding film, while the active front of a circuit chip requires a structured shielding film that leaves the contact areas of the circuit chip free.
  • the chip can be shielded directly, a sputter metallization made of magnetically conductive material being applied directly to the chip.
  • This requires a higher level of complexity in chip technology, since materials such as ferromagnetic iron, nickel or cobalt or their alloys are sometimes used that are not normally used in semiconductor technology.
  • package shielding with Permalloy or Alloy 42, which is embedded in the plastic housing compound.
  • Permalloy or Alloy 42 which is embedded in the plastic housing compound.
  • the disadvantage of such a shielding cover in the plastic housing is that these magnetic materials are polarized in the magnetic field and consequently act on the circuit chip like a permanent magnet and thus restrict the function of the component.
  • shields that are used for electromagnetic interference by applying thin copper layers for the electronic component cannot be used successfully in the case of purely magnetic interference in the environment of electronic components, such as transformers, power supplies or blower motors, since these critical magnetic fields in the low frequency Range, while the electromagnetic waves are high-frequency and other shielding mechanisms occur.
  • Such shielding foils can be 20 to 75 micrometers thick and achieve a shielding factor between 50 and 100.
  • This shield according to the invention differs significantly from the electromagnetic shields which are made of copper and also from shields which are based on permalloy foils which have the disadvantages already mentioned above.
  • permalloy films have a high dependence in their shielding effect on the temperature, which is not the case with the shielding film according to the invention with a Curie temperature between 200 ° C. and 500 ° C.
  • these known foils are not mechanically resilient and do not have the suitable hardness, as is provided by the shielding foil according to the invention.
  • a highly permeable amorphous metal is used for the shielding foil, which has a thickness of at least 20 micrometers and at most 75 micrometers, whereby any desired thickness can be achieved by stacking foils, especially since the magnetstriction is negligibly small and thus delamination of the stacked film does not occur.
  • FIG. 1 shows a schematic cross section through an electronic component of a first embodiment of the invention
  • FIG. 2 shows a schematic cross section through an electronic component of a second embodiment of the invention
  • FIG. 3 shows a schematic cross section through an electronic component of a third embodiment of the invention
  • FIG. 4 shows a schematic cross section through an electronic component of a fourth embodiment of the invention
  • FIG. 5 shows a schematic cross section through an electronic component of a fifth embodiment of the invention.
  • FIG. 1 shows a schematic cross section through an electronic component 1 of a first embodiment of the invention.
  • the electronic component 1 has a multilayer rewiring plate 2 which carries a circuit chip 3, the circuit chip 3 with its active top side 18 and an insulating adhesive film 22 being aligned and mounted on the rewiring plate 2.
  • the multilayer rewiring plate 2 has a carrier layer 25 made of cross-linked plastic, which can be reinforced by glass fibers or carbon fibers.
  • the plastic layer 25 carries a magnetic shielding layer 8 made of amorphous metal or an amorphous metal alloy, preferably based on iron, cobalt or nickel with alloy additives, for example made of boron, which despite a high mechanical hardness with an elastic modulus of 150 GPa, a tensile strength between 1000 and 3000 MPa and has a Vickers hardness between 900 and 1100 soft magnetic properties.
  • a magnetic shielding layer 8 made of amorphous metal or an amorphous metal alloy, preferably based on iron, cobalt or nickel with alloy additives, for example made of boron, which despite a high mechanical hardness with an elastic modulus of 150 GPa, a tensile strength between 1000 and 3000 MPa and has a Vickers hardness between 900 and 1100 soft magnetic properties.
  • the soft magnetic properties shield the memory chip 12 from magnetic interference fields, such as can occur due to transformers, power supply units or blower motors in the vicinity of such an electronic memory module. Due to the soft magnetic properties of the shielding layer in a thickness of between 20 and 75 micrometers, the amorphous materials ensure that this layer itself cannot be permanently magnetized, so that the memory chip and its functionality are not impaired.
  • the outside 10 of the rewiring plate 2 is in this case
  • Embodiment of the invention the underside of the electronic component 1 at the same time.
  • the external contacts 7 of the electronic component 1 are arranged on the outside 10 of the rewiring plate 2 Contact surfaces 5 of the memory chip 12 are connected.
  • the outermost layer of the multilayer rewiring plate 2 is formed by a solder resist layer 27, which covers the rewiring lines 6 and leaves the external contacts 7 or the external contact areas 28 free.
  • the bond connections 21 in the bond channel are embedded in a plastic housing compound 19 and are thus protected against mechanical and electrical interference.
  • the layer structure of the multilayer rewiring board seen from the memory chip thus initially has an adhesive film 22, then the magnetic shielding layer 8, which in this case consists of a shielding film 9, is supported by a plastic layer 25, which in turn is clad with a copper structure 26 and, as the final outer layer, a solder resist layer 27 protects the rewiring structure 29 of the rewiring plate 2 before external damage and before electrical short circuits and before wetting by the external contact material of the external contacts 7 when soldering onto a higher-level circuit of a printed circuit board.
  • the memory chip 12 is embedded in a plastic housing compound 19.
  • This plastic housing compound 19 can be applied to the semiconductor chip simultaneously for a plurality of electronic components which are produced on a panel, the plastic housing compound 19 also being introduced into the bond channel opening at the same time.
  • the bond channel opening 13 for the individual layers 22, 8 and 25 can be introduced into each layer individually before the layers are laminated on, if these layers are present as independent films or plates. Another possibility consists in introducing the bond channel opening in one work step after lamination of these three base layers 22, 8 and 25.
  • the materials of an adhesive film 15 for the adhesive layer 24 of the rewiring plate 2 and the materials of the shielding film 9 for the shielding layer 8 as well as the materials of the plastic layer for the carrier plate are pre-structured in foil form and then laminated onto one another.
  • the plastic layer 25 already has the rewiring structure 29, which in turn can already be provided with a solder resist layer 27.
  • protection against magnetic interference fields is provided only by the shielding layer 8 of the multilayer rewiring plate 2, so that the circuit chip 3 is only protected from magnetic interference fields on one side.
  • Figure 2 shows a schematic cross section through an electronic component of a second embodiment of the invention.
  • Components with the same functions as in the previous figures are identified by the same reference symbols and are not discussed separately.
  • the structure of the multilayer rewiring plate 2 of the second embodiment of the invention corresponds to the rewiring plate 2 of the first embodiment of the invention, since here too a memory chip 12, which can also be a magnetic memory chip, for example, is to be protected against magnetic interference fields.
  • this second embodiment of the invention provides that an unstructured shielding film 9 is laminated onto the passive rear side 17 of the memory chip 12.
  • the sensitive active front side 18 of the semiconductor chip is thus enclosed by shielding foils 9, which are arranged on the one hand on the rear side of the semiconductor chip and on the other hand form a layer of the multilayer rewiring plate 2.
  • this second embodiment of the invention differs from the first embodiment of the invention.
  • This bond tape which is less than 10 micrometers thick, is practically an extension of the conductor track 6 of the rewiring structure 29.
  • this electronic component 1 has the further advantage that the bond connection 21 can be made substantially flatter than in the first embodiment of the invention.
  • FIG. 3 shows a schematic cross section through an electronic component 1 of a third embodiment of the invention.
  • a memory chip with electronic memory cells or a memory chip with magnetic memory cells is to be protected from interference fields.
  • Components with the same functions as in the previous figures are identified by the same reference symbols and are not discussed separately.
  • the shielding layer 8 in the form of a shielding film 9 is arranged on the outer contact side of the rewiring plate 2 and the plastic layer 25 is on the chip side 15 of the rewiring plate.
  • the shielding layer 8 has an additional insulating layer 30, for example made of an Ormocer material, which is a few micrometers thick and in turn carries the rewiring structure 29, on which the solder resist layer is in turn applied.
  • shielding foils 9 for magnetic shielding of the memory chip 12 were provided by laminating a non-structured shielding foil 9 on the back 17 of the memory chip 12 and laminating a shielding foil 9 structured with a bond channel opening 13 on the front 18 of the memory chip 12 ,
  • Such additional shielding layers 8 directly on the memory chip are helpful if the shielding factor of the shielding layer 8 made of amorphous metal or a metal alloy in the rewiring plate 2 is not sufficient.
  • the shielding layer 8 in the rewiring plate 2 can also be made in multiple layers by laminating a plurality of shielding foils 9 one above the other.
  • a stack in the rewiring plate 2 cannot protect the memory chip 12 from magnetic interference from the rear side 17, so that the lamination of a stack of shielding foils 9 on the rear side 7 of the memory chip 12 may be necessary in cases of large magnetic interference fields.
  • FIG. 4 shows a schematic cross section through an electronic component 1 of a fourth embodiment of the invention.
  • Components with the same functions as in the previous figures are identified by the same reference symbols and are not discussed separately.
  • the circuit chip 3 to be protected with the fourth embodiment of the invention is a logic chip 14 which, with its active upper side 18, is not directed towards the redistribution board 2, but rather is arranged opposite, so that its passive rear side 17 is connected to the rewiring plate 2 via an electrically conductive adhesive layer 23 in this case.
  • the multilayer rewiring plate 2 has a structured shielding layer 8 in the form of a shielding film 9 towards the chip side 15, which is structured in such a way that it opens openings 11 for bond contact areas 16 of a rewiring structure 29.
  • the shielding layer 8 made of amorphous metal is laminated onto the rewiring structure 29 of the plastic layer with the aid of an insulating adhesive or an insulating adhesive layer 24.
  • the plastic layer 25 has through contacts 31, via which the rewiring structure 29 is electrically connected to the external contacts 7.
  • the rear side 17 of the logic chip 14 can also be connected to an external contact 7, for example for grounding or for connection to the lowest potential of the integrated circuit of the logic chip 14.
  • This electrical connection is made via the redistribution foil 9 on the back 17 of the semiconductor chip, an electrically conductive adhesive layer 23, a further shielding foil 9 made of electrically conductive, magnetically shielding amorphous metal or a corresponding metal alloy and finally via electrical contact surfaces made of copper and corresponding solder surfaces as well Reached to the external contact 7 via a through contact 31 and an external contact surface 28.
  • the underside of the logic chip 14 is thus protected from magnetic interference by two stacked shielding foils 9, which are connected to one another by a conductive adhesive 23, while the active top side 18 is protected from a structured shielding film 9 can be additionally protected.
  • This structured shielding film 9 has openings 11 for exposing the contact areas 5 of the logic chip 14, so that these contact areas 5 of the logic chip 14 are accessible at the edge of the logic chip for a bond connection 21.
  • FIG. 5 shows a schematic cross section through an electronic component 1 of a fifth embodiment of the invention.
  • Components with the same functions as in the previous embodiments are identified by the same reference numerals and are not discussed separately.
  • the difference between the fifth embodiment of the invention and the fourth embodiment of the invention is that a shielding film 9 is arranged on the outside of the electronic component.
  • the structured shielding film 9 has openings 11 for the external contacts 7.
  • the external contacts 7 are surrounded by a solder resist 11, which simultaneously isolates the external contacts 7 from the shielding film 9 on the underside of the electronic component 1.
  • the shielding is used for a logic chip 14 which has contact areas 5 in its edge region which, when the active upper side 18 of the semiconductor chip is shielded with a shielding film 9, must be cut out through corresponding openings 11 in the shielding film.
  • the rear side 17 of the logic chip 14 can be connected to one of the external contacts 7 via a through-contact, but this is not shown in the cross section of FIG. 5 shown here.
  • the redistribution board 2 consists of only three layers, namely a layer which has the rewiring structure 29 with corresponding rewiring lines 6, a plastic layer 25 which carries the rewiring structure and has through contacts 31, and a shielding layer 8 made of a shielding film 9 with corresponding openings 11 for the external contacts 7 of the electronic component.
  • the connection between contact areas 5 of the logic chip 14 and the rewiring structure 29 is achieved via a bond connection 21.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne un composant électronique (1) présentant une plaque de recâblage multicouche (2) qui porte une puce de circuit (3), notamment une puce mémoire magnétique (4), et qui relie des surfaces de contact de la puce (5) à des contacts externes (7) du composant électronique (1) par l'intermédiaire de lignes de recâblage (6). La plaque de recâblage (2) présente au moins une couche de protection magnétique structurée (8) constituée d'un métal amorphe ou d'un alliage de métaux amorphes. La présente invention concerne également un procédé pour produire ce composant électronique (1).
EP03761442A 2002-07-01 2003-06-30 Composant electronique presentant une plaque de recablage multicouche et procede pour produire ce composant electronique Withdrawn EP1518274A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10229542 2002-07-01
DE10229542A DE10229542B4 (de) 2002-07-01 2002-07-01 Elektronisches Bauteil mit mehrschichtiger Umverdrahtungsplatte und Verfahren zur Herstellung desselben
PCT/DE2003/002162 WO2004004006A1 (fr) 2002-07-01 2003-06-30 Composant electronique presentant une plaque de recablage multicouche et procede pour produire ce composant electronique

Publications (1)

Publication Number Publication Date
EP1518274A1 true EP1518274A1 (fr) 2005-03-30

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EP03761442A Withdrawn EP1518274A1 (fr) 2002-07-01 2003-06-30 Composant electronique presentant une plaque de recablage multicouche et procede pour produire ce composant electronique

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US (1) US7294910B2 (fr)
EP (1) EP1518274A1 (fr)
DE (1) DE10229542B4 (fr)
WO (1) WO2004004006A1 (fr)

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Publication number Publication date
DE10229542A1 (de) 2004-01-29
US20060043539A1 (en) 2006-03-02
US7294910B2 (en) 2007-11-13
WO2004004006A1 (fr) 2004-01-08
DE10229542B4 (de) 2004-05-19

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