EP1490901A1 - Procede de formation d'un contact ameliore aux siliciures de metaux sur une regio conductrice contenant du silicium - Google Patents

Procede de formation d'un contact ameliore aux siliciures de metaux sur une regio conductrice contenant du silicium

Info

Publication number
EP1490901A1
EP1490901A1 EP02787066A EP02787066A EP1490901A1 EP 1490901 A1 EP1490901 A1 EP 1490901A1 EP 02787066 A EP02787066 A EP 02787066A EP 02787066 A EP02787066 A EP 02787066A EP 1490901 A1 EP1490901 A1 EP 1490901A1
Authority
EP
European Patent Office
Prior art keywords
metal
layer
silicon
nitrogen
conductive region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02787066A
Other languages
German (de)
English (en)
Inventor
Karsten Wieczorek
Volker Kahlert
Manfred Horstmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10214065A external-priority patent/DE10214065B4/de
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of EP1490901A1 publication Critical patent/EP1490901A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Definitions

  • the present invention relates to the field of fabrication of integrated circuits, and more particularly, to semiconductor devices having metal suicide portions in conductive silicon-containing regions to reduce the sheet resistance of these regions.
  • CD critical dimension
  • the shrinking of the channel length also entails the reduction in size of any conductive lines, such as the gate electrode of the field effect transistor, which is commonly formed of polysilicon, and the contact regions that allow electrical contact to the drain and the source regions of the transistor, so that, consequently, the available cross-section for charge carrier transportation is reduced.
  • the conductive lines and contact regions exhibit a higher resistance unless the reduced cross-section is compensated by improving the electrical characteristics of the material forming the lines and contact regions, such as the gate electrode and the drain and the source contact regions.
  • the individual semiconductor devices such as field effect transistors, capacitors and the like, are primarily based on silicon, wherein the individual devices are connected by silicon lines and metal lines. While the resistivity of the metal lines may be improved by replacing the commonly used aluminum by, for example, copper, process engineers are confronted with a challenging task when an improvement of the electrical characteristics of silicon- containing semiconductor lines and semiconductor contact regions is required.
  • Figure la schematically shows a cross-sectional view of a field effect transistor 100 formed in a substrate 101, which may be a silicon substrate or any other appropriate substrate for carrying the field effect transistor 100.
  • the dimensions of the field effect transistor 100 are defined by a shallow trench isolation 103 that may be formed of an insulating material, such as silicon dioxide.
  • a gate insulation layer 106 comprising, for example, silicon dioxide, separates a gate electrode 109, substantially comprised of pplysilicon, from the well region 102, which may contain N-type and or P-type dopant atoms, depending on the required characteristics of the field effect transistor 100.
  • source and drain regions are provided in the well region 102 and are inversely doped to the well region 102.
  • the surface region of the well region 102 that underlies the gate insulation layer 106 is also referred to as the channel region.
  • the lateral distance in Figure la separating the drain and source regions 105 is referred to as the channel length.
  • Sidewall spacers 107 comprising, for example, silicon dioxide or silicon nitride, are formed in contact with the sidewalls of the gate electrode 109.
  • metal suicide portions 108 are formed, which typically comprise a cobalt suicide (CoSi 2 ) in a low-ohmic state to reduce the resistance of the respective silicon-containing conductive region, such as the gate electrode 109 and the source and drain regions 105.
  • the structure shown in Figure la is typically formed by the following process steps. First, after forming the trench isolation 103 by etching trenches and refilling with silicon dioxide, the gate insulation layer 106 is formed, for example, by an oxidizing process.
  • a polysilicon layer is deposited and patterned to form the gate electrode 109 by sophisticated photolithography techniques. Thereafter, a first implantation step is performed to define lightly doped regions in the source and drain regions 105 and then the sidewall spacers 107 are formed that act as an implantation mask in a subsequent implantation step for defining the source and drain regions 105.
  • a layer of refractory metal for example, including titanium, tantalum, zirconium, cobalt, nickel and the like, is deposited over the structure shown in Figure la. Typically, the metal is deposited by sputter deposition in a sputter tool including a corresponding target to provide the required metal.
  • Figure lb schematically shows an enlarged cross-sectional view of a portion of the drain region 105, including the layer of refractory metal 110, deposited on the drain region 105.
  • a cap layer 111 is located and may typically comprise titanium or titanium nitride, when the refractory metal of the layer 110 is substantially formed of cobalt.
  • the cap layer 111 is typically formed by sputter deposition, wherein the substrate 101 is treated in a separate deposition chamber to form the cap layer 111.
  • a first anneal step at a first average temperature is performed to initiate a chemical reaction between the refractory metal in the layer 110 and the silicon in the drain region 105. It should be noted that a corresponding reaction, of course, also takes place in the gate electrode 109 and the source region 105.
  • the metal of the layer 110 for example cobalt
  • the silicon in the region 105 are subjected to diffusion and form a cobalt monosilicide.
  • the cap layer 111 if substantially comprising titanium, acts as a so-called gettering layer that preferably reacts with any oxygen atoms prevailing in the anneal ambient to form titanium oxide.
  • the titanium cap layer 111 will significantly reduce any oxidation of the underlying cobalt in the layer 110, which could otherwise form a cobalt oxide and would increase the resistance of the finally obtained suicide layer.
  • titanium and cobalt tend to form a compound which does not substantially undergo a reaction with silicon and, thus, does not contribute to a low ohmic suicide portion.
  • the cap layer 111 substantially comprises titanium nitride
  • the cap layer 111 acts as a substantially inert layer during the first annealing step; however, it provides only a moderate capability for protecting the underlying cobalt from being oxidized by residual oxygen in the anneal ambient.
  • grain boundaries build up, in which titanium may accumulate when a titanium cap layer 111 is employed.
  • the cap layer 111 and the non-reacted cobalt of the layer 110 are removed by a selective wet etching process.
  • a second annealing step is carried out at a higher average temperature than in the first annealing step, typically in the range of 650-700°C, if cobalt has been used in the layer 110, to transform the cobalt monosilicide into a more stable cobalt disilicide, which exhibits a remarkably lower sheet resistance than the cobalt monosilicide.
  • the titanium may have accumulated at the grain boundaries of the cobalt monosilicide and, thus, the main diffusion path for the chemical reaction during the second annealing step may significantly be hindered by the accumulated titanium.
  • a cobalt titanium layer 112 may have formed during the initial annealing step and thus a thickness of the suicide portion 108 is reduced. Moreover, due to the accumulated titanium at the grain boundaries, the interface 113 of the finally obtained suicide portion 108 and the underlying silicon-containing region 105 may be relatively rough and, therefore, exhibit an increased electrical resistance owing to increased scattering- of charge carriers. If a titanium nitride layer is used as the cap layer 111, the generation of the cobalt titanium layer 112 may substantially be avoided, but instead the finally obtained suicide portion 108 may comprise a considerable amount of cobalt oxide, thereby also increasing the electrical resistance of the silicide portion 108.
  • the present invention is directed to a method for forming a suicided portion in a silicon- containing conductive region, wherein a stack of layers is provided, in which one or more metal layers provide the metal for forming the metal silicide portion, while other layers in the stack are provided to protect the underlying metal layer during the initiation of a chemical reaction between the metal and the silicon.
  • the complex deposition technique requiring two separate deposition chambers may be remarkably simplified by providing an in situ method for forming the layer stack, thereby allowing the deposition of the metal layer and of the protective layers in a single deposition chamber.
  • a method of forming regions of reduced resistance in a silicon-containing conductive region comprises the provision of a substrate having formed thereon the silicon-containing conductive region and the deposition of a layer stack on the silicon-containing conductive region, wherein the layer stack comprises a first and a second metal layer and a metal nitrogen compound layer positioned between the first and the second metal layer. Additionally, the method comprises heat treating the substrate to form a metal silicide portion in the silicon-containing conductive region.
  • a method of forming a silicide portion in a silicon-containing conductive region formed on a substrate comprises depositing a metal on the silicon-containing conductive region in a reactive plasma ambient. Moreover, a nitrogen-containing gas is supplied to the reactive plasma ambient for subsequently depositing a metal nitrogen compound. Thereafter, the supply of the nitrogen- containing gas is discontinued to deposit the metal again. Additionally, a heat treatment is carried out to form the metal silicide portion, wherein the metal silicide is formed substantially from metal located between the silicon- containing region and the metal nitrogen compound.
  • Figures la-lc schematically show cross-sectional views of a semiconductor device including a suicided portion formed according to a typical prior art process.
  • Figures 2a-2d schematically show cross-sectional views of a semiconductor device during various manufacturing stages pursuant to one illustrative embodiment of the present invention.
  • illustrative embodiments of die present invention will be described by referring to a field effect transistor including silicon-containing conductive regions. It should be understood, however, that the present invention is applicable to any silicon-containing conductive region provided in an integrated circuit.
  • certain die areas or individual semiconductor elements may be connected by polysilicon lines, which may, in accordance with design requirements, have a relatively small cross-sectional area so that any improvement in the conductivity of these lines will significantly contribute to an enhancement of the overall performance of the integrated circuit.
  • Figure 2a shows a schematic cross-sectional view of a semiconductor element 200 in the form of a field effect transistor having essentially the same components and parts as already described in Figure la.
  • the corresponding components and parts are indicated by the same reference numerals except for a leading "2" instead of a leading "1.”
  • the semiconductor element 200 comprises shallow trench isolations 203 formed in a substrate 201, wherein the substrate 201 may be any appropriate substrate including, for example, a silicon substrate, a silicon-on-insulator substrate, and the like.
  • Drain and source regions 205 are separated by a well region 202 having a central portion over which a gate insulation layer 206 is formed that electrically isolates a gate electrode 209 from the well region 202.
  • sidewall spacers 207 are located at the sidewalls of the gate electrode 202.
  • the process flow for forming the semiconductor element 200 may include substantially the same process steps as already described with reference to Figure la. Thus, a corresponding description is omitted.
  • the semiconductor element 200 shown in Figure 2a comprises a layer stack 220 (as described more fully below) that is provided for the subsequent formation of suicided portions in the drain and the source regions 205 and the gate electrode 209.
  • Figure 2b schematically shows an enlarged cross-sectional view of a portion of the semiconductor element 200 including the layer stack 220 and a portion of the underlying silicon-containing region, for example, the region 205.
  • the layer stack 220 comprises three layers, a first metal layer 221, a second layer 222 comprising a metal nitrogen compound, and a third layer 223 in the form of a metal layer.
  • the first metal layer 221 may comprise a refractory metal or any suitable alloy thereof, including, for example, cobalt, titanium, zirconium, tantalum, tungsten, nickel, and the like.
  • the second layer 222 may comprise a metal nitrogen compound, such as a metal nitride, formed from one of the above-cited refractory metals.
  • the third layer 223 may comprise a metal or an alloy of metals including, for example, any of the above- cited metals.
  • the thickness of the individual layers 221, 222 and 223 is selected to meet the specific requirements. That is, the first layer 221 is the material source for the metal silicide portion to be formed in and on the silicon-containing conductive region 205. Thus, the thickness of the first layer 221 is selected to obtain the required thickness of the silicide portions to be formed.
  • the thickness of the second layer 222 which will serve as an inert layer, that is, as a diffusion barrier layer substantially hindering diffusion from the first layer 221 to the second layer 222 and/or to the third layer 223 and a chemical reaction between the first layer 221 and the second layer 222 in the subsequent process steps for forming the metal silicide portions, is selected so as to ensure a sufficient protection of the underlying first layer 221 in the subsequent anneal step.
  • the metal nitride in the second layer 222 is titanium nitride
  • a typical layer thickness is in the range of approximately 10-
  • the thickness of the third layer 223, which will serve in the subsequent anneal step as a gettering layer reacting with oxygen atoms or other reactive byproducts to form a metal oxide or any other compound, is accordingly preferably selected to substantially consume all of the oxygen atoms or molecules hitting the surface ' of the third layer 223.
  • a thickness in the range of approximately 10-30 nm is sufficient to maintain the degree of undesired oxidation in the first layer 221 within a tolerable range.
  • the first layer 221 and the third layer 223 comprise substantially the same metal and the second layer 222 substantially comprises a metal nitride formed from the same metal which forms the first and third layers.
  • the second and the third layers 221, 222 and 223 offers the following advantages.
  • metal layers are deposited by physical vapor deposition, such as sputter deposition, due to the relatively high degree of uniformity that is achievable over the entire substrate surface.
  • the substrate such as the substrate 201
  • a reaction chamber (not shown) containing a target, that is, usually a disk- shaped material that is to be deposited on the substrate, and means for generating a plasma ambient.
  • a plasma is generated using a noble gas, such as argon, to direct ions and electrons to the target material to liberate target atoms. A portion of the liberated atoms then migrates to the substrate and condenses thereon to form a metal layer, such as the first layer 221.
  • the process parameters of the sputter deposition such as chamber pressure, power supplied to the plasma generating means, any DC or AC bias voltage supplied to the substrate, the distance between the target and the substrate, the duration of the deposition process and the like, may be controlled to adjust the thickness of the first layer 221 in accordance with design requirements.
  • chamber pressure power supplied to the plasma generating means, any DC or AC bias voltage supplied to the substrate, the distance between the target and the substrate, the duration of the deposition process and the like, may be controlled to adjust the thickness of the first layer 221 in accordance with design requirements.
  • a nitrogen-containing gas for example, nitrogen (N 2 )
  • nitrogen (N 2 ) is added to the plasma ambient.
  • N 2 nitrogen
  • many refractory metals such as titanium, zirconium, tantalum, tungsten and the like, form nitrogen compounds during sputter deposition in the presence of nitrogen so that the second layer 222 may be formed as a metal nitride layer.
  • the deposition process parameters including the parameters pointed out above, and particularly the flow rate of nitrogen supplied to the reactive plasma ambient, may be controlled to adjust the thickness and the characteristics of the second layer 222.
  • the nitrogen supply is discontinued, wherein the plasma ambient is still maintained so that increasingly more metal than metal nitride is deposited on the substrate. This process progresses until substantially all of the residual nitrogen gas is consumed so that finally a substantially "pure" metal layer 223 is produced.
  • any nitrogen captured in the target material, or any metal nitride deposited on the target and on the chamber walls may be removed during the deposition process without nitrogen supply so that the contamination with metal nitride in a subsequent sputter deposition process is minimized.
  • the deposition process for the third layer 223 is stopped when a required thickness is achieved, or when a required degree of "cleanliness" in the deposition chamber is established. Since the third layer 223 will only act as a sacrificial layer, the thickness is not critical as long as a minimum required effectiveness in gettering oxygen atoms is guaranteed. Consequently, according to this particular embodiment, a layer stack 220 including the three layers 221, 222 and 223 may be formed in an in situ sputter deposition process, thereby significantly improving throughput and tool performance.
  • the first layer 221 may be deposited in a first plasma ambient to form, for example, a cobalt layer 221, and subsequently the substrate 201 is exposed to a second plasma ambient including a second target material, for example, titanium, and a nitrogen-containing gas component.
  • a second target material for example, titanium
  • a nitrogen-containing gas component for example, titanium
  • the supply of the nitrogen-containing gas is discontinued and, as described with reference to the foregoing embodiment, gradually a titanium layer 223 is deposited while at the same time the sputter target is decontaminated, as is explained above.
  • a material composition may be selected wherein the first layer 221 is chosen to yield an optimized silicide portion, and wherein the second and third layers 222 and 223 are selected to provide for an optimum protection of the first layer 221 during the subsequent heat treatment.
  • a heat treatment is carried out to initiate a chemical reaction between the silicon in the silicon-containing conductive region 205 and the first metal layer 221.
  • a first anneal step at a first averaged temperature may be performed so as to initiate the chemical reaction between the metal in the first layer 221 and the underlying silicon and to form a metal silicon compound.
  • the second layer 222 substantially avoids any up and down diffusion of material of the first and third layers 221, 223, which is particularly advantageous when the first and the third layers each comprise a different metal. Furthermore, the second layer 222 does substantially not react with the metal of the first layer 221.
  • any reactive element especially oxygen that may be present in the ambient, is substantially consumed by the third layer 223 by forming a compound, such as an oxide, with these reactive elements.
  • the second and third layers 222 and 223 are selectively removed and also any excess material of the first layer 221 that has not reacted with the underlying silicon is removed. Such removal may be accomplished by performing a variety of known wet etching processes.
  • Figure 2c schematically shows the metal silicon compound 225 formed in and on the silicon-containing conductive region 205 after removal of any excess material. Subsequently, a further heat treatment, such as a second anneal step, at a higher average temperature than in the first heat treatment, is carried out to transform the metal silicon compound into a metal silicide that exhibits a significantly lower resistance than the silicon in the region 205 or the metal silicon compound 225.
  • a further heat treatment such as a second anneal step
  • Figure 2d schematically shows the semiconductor element 200 after completion of the second heat treatment, wherein metal silicide portions 208 are formed in and on the source and drain regions 205 and the gate electrode 209. Due to the provision of the second layer 222 during the first heat treatment, the interface between the silicon and the metal silicide region 208 is significantly improved, even if the metal of the first layer 221 differs from that of the third layer 223, since any diffusion activity between these two layers is substantially avoided.
  • the illustrative embodiments described so far refer to a layer stack 220 having three different layers, the layer stack 220 may comprise any appropriate number of layers to achieve the required diffusion barrier function and the required gettering function.
  • the transition between the second layer 222 and the third layer 223 may be a gradual transition in which the ratio of metal and metal nitride may gradually vary so that the top of the layer stack 220 exhibits an enhanced gettering efficiency, whereas the portion on top of the first metal layer 221 exhibits the required diffusion blocking characteristics.
  • the first layer 221 and the second layer 222 may be deposited in an in situ process to form a metal layer 221 and a corresponding nitride layer 222, whereas the third layer 223 may be formed of a different material in a separate deposition process.
  • the term layer is to describe a layer that is defined essentially by its function rather by its boundary to an overlying or underlying layer.
  • a metal nitride layer that is deposited by sputter deposition with supply of nitrogen and a layer formed, after a certain thickness of metal nitride is obtained, by discontinuing the nitrogen supply may be understood as at least two layers due to the gettering function of the finally formed layer and the inert effect of the former layer, although a clear physical boundary therebetween is difficult to define.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)

Abstract

La présente invention concerne un empilement de couches (200) d'au moins trois couche de matières (221, 222 et 223). Cet empilement est réalisé sur une région conductrice au silicium pour former une portion siliciurée (208) rapportée sur et pénétrant dans la région conductrice au silicium. En l'occurrence, la couche (221) venant contre le silicium fournit les atomes de métal nécessaires à la siliciuration. La couche intermédiaire (222) est un composé métal-azote formé par apport d'un gaz azoté pendant l'opération de dépôt. En outre, pour la formation de la couche supérieure (223), l'apport de ce gaz azoté est interrompu. Ce procédé est réalisable in situ, ce qui améliore de façon importante le rendement et l'effcacité de l'outil de dépôt par rapport aux procédés généralement utilisés jusqu'à présent et nécessitant au moins deux chambres de dépôt.
EP02787066A 2002-03-28 2002-12-20 Procede de formation d'un contact ameliore aux siliciures de metaux sur une regio conductrice contenant du silicium Withdrawn EP1490901A1 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US282665 1994-07-29
DE10214065A DE10214065B4 (de) 2002-03-28 2002-03-28 Verfahren zur Herstellung eines verbesserten Metallsilizidbereichs in einem Silizium enthaltenden leitenden Gebiet in einer integrierten Schaltung
DE10214065 2002-03-28
US10/282,665 US20030186523A1 (en) 2002-03-28 2002-10-29 Method for forming an improved metal silicide portion in a silicon-containing conductive region in an integrated circuit
PCT/US2002/040806 WO2003083936A1 (fr) 2002-03-28 2002-12-20 Procede de formation d'un contact ameliore aux siliciures de metaux sur une regio conductrice contenant du silicium

Publications (1)

Publication Number Publication Date
EP1490901A1 true EP1490901A1 (fr) 2004-12-29

Family

ID=28676031

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02787066A Withdrawn EP1490901A1 (fr) 2002-03-28 2002-12-20 Procede de formation d'un contact ameliore aux siliciures de metaux sur une regio conductrice contenant du silicium

Country Status (6)

Country Link
EP (1) EP1490901A1 (fr)
JP (1) JP2005522035A (fr)
CN (1) CN100380625C (fr)
AU (1) AU2002351407A1 (fr)
TW (1) TWI263266B (fr)
WO (1) WO2003083936A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4819566B2 (ja) 2006-04-28 2011-11-24 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
WO2012086540A1 (fr) * 2010-12-21 2012-06-28 シャープ株式会社 Transistor à couches minces et son procédé de production
DE102012003585A1 (de) * 2012-02-27 2013-08-29 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer einkristallinen Metall-Halbleiter-Verbindung

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5766997A (en) * 1909-11-30 1998-06-16 Nkk Corporation Method of forming floating gate type non-volatile semiconductor memory device having silicided source and drain regions
US5240880A (en) * 1992-05-05 1993-08-31 Zilog, Inc. Ti/TiN/Ti contact metallization
US5365111A (en) * 1992-12-23 1994-11-15 Advanced Micro Devices, Inc. Stable local interconnect/active area silicide structure for VLSI applications
JPH08107087A (ja) * 1994-10-06 1996-04-23 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5738917A (en) * 1995-02-24 1998-04-14 Advanced Micro Devices, Inc. Process for in-situ deposition of a Ti/TiN/Ti aluminum underlayer
US5700718A (en) * 1996-02-05 1997-12-23 Micron Technology, Inc. Method for increased metal interconnect reliability in situ formation of titanium aluminide
US5970370A (en) * 1998-12-08 1999-10-19 Advanced Micro Devices Manufacturing capping layer for the fabrication of cobalt salicide structures
DE19940758A1 (de) * 1999-08-27 2001-03-15 Infineon Technologies Ag Verfahren zur Herstellung eines HF-FET und HF-FET

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO03083936A1 *

Also Published As

Publication number Publication date
CN100380625C (zh) 2008-04-09
TWI263266B (en) 2006-10-01
WO2003083936A1 (fr) 2003-10-09
AU2002351407A1 (en) 2003-10-13
JP2005522035A (ja) 2005-07-21
CN1623227A (zh) 2005-06-01
TW200307988A (en) 2003-12-16

Similar Documents

Publication Publication Date Title
KR100530401B1 (ko) 저저항 게이트 전극을 구비하는 반도체 장치
US6838363B2 (en) Circuit element having a metal silicide region thermally stabilized by a barrier diffusion material
US7229873B2 (en) Process for manufacturing dual work function metal gates in a microelectronics device
US7737015B2 (en) Formation of fully silicided gate with oxide barrier on the source/drain silicide regions
JP2008022027A (ja) 半導体装置のセルフアラインシリサイドの形成方法
JP2007243105A (ja) 半導体装置およびその製造方法
KR20070015004A (ko) 실리사이드화된 게이트의 형성 방법
US7226859B2 (en) Method of forming different silicide portions on different silicon-containing regions in a semiconductor device
US20030186523A1 (en) Method for forming an improved metal silicide portion in a silicon-containing conductive region in an integrated circuit
US8294220B2 (en) Method for forming silicide contacts
US7217657B2 (en) Semiconductor device having different metal silicide portions and method for fabricating the semiconductor device
EP1479102B1 (fr) Procede de formation de differentes parties de silicide sur differentes zones contenant du silicium dans un dispositif a semi-conducteur
WO2003083936A1 (fr) Procede de formation d'un contact ameliore aux siliciures de metaux sur une regio conductrice contenant du silicium
US6893910B1 (en) One step deposition method for high-k dielectric and metal gate electrode
US6063692A (en) Oxidation barrier composed of a silicide alloy for a thin film and method of construction
KR100764341B1 (ko) 반도체소자의 제조방법
WO2003079424A1 (fr) Procede de fabrication d'un dispositif semi-conducteur comportant differentes portions de siliciure metallique
US20080233747A1 (en) Semiconductor Device Manufactured Using an Improved Plasma Etch Process for a Fully Silicided Gate Flow Process
KR100806136B1 (ko) 금속 게이트전극을 구비한 반도체소자의 제조 방법
KR100806138B1 (ko) 금속 게이트전극을 구비한 반도체소자의 제조 방법
JP2000077429A (ja) 半導体装置の製造方法
US7067410B2 (en) Method of forming a metal silicide
JP2007134705A (ja) 半導体素子及びその製造方法
KR100806135B1 (ko) 금속 게이트전극을 갖는 반도체소자의 제조 방법
KR100334866B1 (ko) 반도체소자의트랜지스터형성방법

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20040902

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SI SK TR

AX Request for extension of the european patent

Extension state: AL LT LV MK RO

RIN1 Information on inventor provided before grant (corrected)

Inventor name: HORSTMANN, MANFRED

Inventor name: KAHLERT, VOLKER

Inventor name: WIECZOREK, KARSTEN

17Q First examination report despatched

Effective date: 20090212

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: GLOBALFOUNDRIES INC.

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: GLOBALFOUNDRIES INC.

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20111110