EP1490901A1 - Method for forming an improved metal silicide contact to a silicon-containing conductive region - Google Patents
Method for forming an improved metal silicide contact to a silicon-containing conductive regionInfo
- Publication number
- EP1490901A1 EP1490901A1 EP02787066A EP02787066A EP1490901A1 EP 1490901 A1 EP1490901 A1 EP 1490901A1 EP 02787066 A EP02787066 A EP 02787066A EP 02787066 A EP02787066 A EP 02787066A EP 1490901 A1 EP1490901 A1 EP 1490901A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- metal
- layer
- silicon
- nitrogen
- conductive region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 111
- 239000002184 metal Substances 0.000 title claims abstract description 111
- 238000000034 method Methods 0.000 title claims abstract description 47
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 45
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 45
- 239000010703 silicon Substances 0.000 title claims abstract description 45
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 23
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 23
- 229910017464 nitrogen compound Inorganic materials 0.000 claims abstract description 19
- 230000008569 process Effects 0.000 claims abstract description 17
- 239000007789 gas Substances 0.000 claims abstract description 13
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000011065 in-situ storage Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 31
- 238000000151 deposition Methods 0.000 claims description 21
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 18
- 150000002830 nitrogen compounds Chemical class 0.000 claims description 18
- 239000010936 titanium Substances 0.000 claims description 18
- 229910052719 titanium Inorganic materials 0.000 claims description 18
- 239000010941 cobalt Substances 0.000 claims description 15
- 229910017052 cobalt Inorganic materials 0.000 claims description 15
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 15
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 10
- 238000005247 gettering Methods 0.000 claims description 7
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 6
- 229910052726 zirconium Inorganic materials 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 abstract description 11
- 230000008021 deposition Effects 0.000 abstract description 11
- 239000000463 material Substances 0.000 abstract description 11
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 137
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 17
- 239000004065 semiconductor Substances 0.000 description 14
- 150000004767 nitrides Chemical class 0.000 description 12
- 206010010144 Completed suicide Diseases 0.000 description 10
- 238000004544 sputter deposition Methods 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 9
- 230000005669 field effect Effects 0.000 description 9
- 239000003870 refractory metal Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 7
- 229910052757 nitrogen Inorganic materials 0.000 description 7
- 238000005137 deposition process Methods 0.000 description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
- AIOWANYIHSOXQY-UHFFFAOYSA-N cobalt silicon Chemical compound [Si].[Co] AIOWANYIHSOXQY-UHFFFAOYSA-N 0.000 description 5
- 230000003247 decreasing effect Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 125000004430 oxygen atom Chemical group O* 0.000 description 4
- 150000003377 silicon compounds Chemical class 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 125000004429 atom Chemical group 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 239000013077 target material Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 229910000428 cobalt oxide Inorganic materials 0.000 description 2
- NNSIWZRTNZEWMS-UHFFFAOYSA-N cobalt titanium Chemical compound [Ti].[Co] NNSIWZRTNZEWMS-UHFFFAOYSA-N 0.000 description 2
- IVMYJDGYRUAWML-UHFFFAOYSA-N cobalt(ii) oxide Chemical compound [Co]=O IVMYJDGYRUAWML-UHFFFAOYSA-N 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- -1 for example Chemical class 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052756 noble gas Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Definitions
- the present invention relates to the field of fabrication of integrated circuits, and more particularly, to semiconductor devices having metal suicide portions in conductive silicon-containing regions to reduce the sheet resistance of these regions.
- CD critical dimension
- the shrinking of the channel length also entails the reduction in size of any conductive lines, such as the gate electrode of the field effect transistor, which is commonly formed of polysilicon, and the contact regions that allow electrical contact to the drain and the source regions of the transistor, so that, consequently, the available cross-section for charge carrier transportation is reduced.
- the conductive lines and contact regions exhibit a higher resistance unless the reduced cross-section is compensated by improving the electrical characteristics of the material forming the lines and contact regions, such as the gate electrode and the drain and the source contact regions.
- the individual semiconductor devices such as field effect transistors, capacitors and the like, are primarily based on silicon, wherein the individual devices are connected by silicon lines and metal lines. While the resistivity of the metal lines may be improved by replacing the commonly used aluminum by, for example, copper, process engineers are confronted with a challenging task when an improvement of the electrical characteristics of silicon- containing semiconductor lines and semiconductor contact regions is required.
- Figure la schematically shows a cross-sectional view of a field effect transistor 100 formed in a substrate 101, which may be a silicon substrate or any other appropriate substrate for carrying the field effect transistor 100.
- the dimensions of the field effect transistor 100 are defined by a shallow trench isolation 103 that may be formed of an insulating material, such as silicon dioxide.
- a gate insulation layer 106 comprising, for example, silicon dioxide, separates a gate electrode 109, substantially comprised of pplysilicon, from the well region 102, which may contain N-type and or P-type dopant atoms, depending on the required characteristics of the field effect transistor 100.
- source and drain regions are provided in the well region 102 and are inversely doped to the well region 102.
- the surface region of the well region 102 that underlies the gate insulation layer 106 is also referred to as the channel region.
- the lateral distance in Figure la separating the drain and source regions 105 is referred to as the channel length.
- Sidewall spacers 107 comprising, for example, silicon dioxide or silicon nitride, are formed in contact with the sidewalls of the gate electrode 109.
- metal suicide portions 108 are formed, which typically comprise a cobalt suicide (CoSi 2 ) in a low-ohmic state to reduce the resistance of the respective silicon-containing conductive region, such as the gate electrode 109 and the source and drain regions 105.
- the structure shown in Figure la is typically formed by the following process steps. First, after forming the trench isolation 103 by etching trenches and refilling with silicon dioxide, the gate insulation layer 106 is formed, for example, by an oxidizing process.
- a polysilicon layer is deposited and patterned to form the gate electrode 109 by sophisticated photolithography techniques. Thereafter, a first implantation step is performed to define lightly doped regions in the source and drain regions 105 and then the sidewall spacers 107 are formed that act as an implantation mask in a subsequent implantation step for defining the source and drain regions 105.
- a layer of refractory metal for example, including titanium, tantalum, zirconium, cobalt, nickel and the like, is deposited over the structure shown in Figure la. Typically, the metal is deposited by sputter deposition in a sputter tool including a corresponding target to provide the required metal.
- Figure lb schematically shows an enlarged cross-sectional view of a portion of the drain region 105, including the layer of refractory metal 110, deposited on the drain region 105.
- a cap layer 111 is located and may typically comprise titanium or titanium nitride, when the refractory metal of the layer 110 is substantially formed of cobalt.
- the cap layer 111 is typically formed by sputter deposition, wherein the substrate 101 is treated in a separate deposition chamber to form the cap layer 111.
- a first anneal step at a first average temperature is performed to initiate a chemical reaction between the refractory metal in the layer 110 and the silicon in the drain region 105. It should be noted that a corresponding reaction, of course, also takes place in the gate electrode 109 and the source region 105.
- the metal of the layer 110 for example cobalt
- the silicon in the region 105 are subjected to diffusion and form a cobalt monosilicide.
- the cap layer 111 if substantially comprising titanium, acts as a so-called gettering layer that preferably reacts with any oxygen atoms prevailing in the anneal ambient to form titanium oxide.
- the titanium cap layer 111 will significantly reduce any oxidation of the underlying cobalt in the layer 110, which could otherwise form a cobalt oxide and would increase the resistance of the finally obtained suicide layer.
- titanium and cobalt tend to form a compound which does not substantially undergo a reaction with silicon and, thus, does not contribute to a low ohmic suicide portion.
- the cap layer 111 substantially comprises titanium nitride
- the cap layer 111 acts as a substantially inert layer during the first annealing step; however, it provides only a moderate capability for protecting the underlying cobalt from being oxidized by residual oxygen in the anneal ambient.
- grain boundaries build up, in which titanium may accumulate when a titanium cap layer 111 is employed.
- the cap layer 111 and the non-reacted cobalt of the layer 110 are removed by a selective wet etching process.
- a second annealing step is carried out at a higher average temperature than in the first annealing step, typically in the range of 650-700°C, if cobalt has been used in the layer 110, to transform the cobalt monosilicide into a more stable cobalt disilicide, which exhibits a remarkably lower sheet resistance than the cobalt monosilicide.
- the titanium may have accumulated at the grain boundaries of the cobalt monosilicide and, thus, the main diffusion path for the chemical reaction during the second annealing step may significantly be hindered by the accumulated titanium.
- a cobalt titanium layer 112 may have formed during the initial annealing step and thus a thickness of the suicide portion 108 is reduced. Moreover, due to the accumulated titanium at the grain boundaries, the interface 113 of the finally obtained suicide portion 108 and the underlying silicon-containing region 105 may be relatively rough and, therefore, exhibit an increased electrical resistance owing to increased scattering- of charge carriers. If a titanium nitride layer is used as the cap layer 111, the generation of the cobalt titanium layer 112 may substantially be avoided, but instead the finally obtained suicide portion 108 may comprise a considerable amount of cobalt oxide, thereby also increasing the electrical resistance of the silicide portion 108.
- the present invention is directed to a method for forming a suicided portion in a silicon- containing conductive region, wherein a stack of layers is provided, in which one or more metal layers provide the metal for forming the metal silicide portion, while other layers in the stack are provided to protect the underlying metal layer during the initiation of a chemical reaction between the metal and the silicon.
- the complex deposition technique requiring two separate deposition chambers may be remarkably simplified by providing an in situ method for forming the layer stack, thereby allowing the deposition of the metal layer and of the protective layers in a single deposition chamber.
- a method of forming regions of reduced resistance in a silicon-containing conductive region comprises the provision of a substrate having formed thereon the silicon-containing conductive region and the deposition of a layer stack on the silicon-containing conductive region, wherein the layer stack comprises a first and a second metal layer and a metal nitrogen compound layer positioned between the first and the second metal layer. Additionally, the method comprises heat treating the substrate to form a metal silicide portion in the silicon-containing conductive region.
- a method of forming a silicide portion in a silicon-containing conductive region formed on a substrate comprises depositing a metal on the silicon-containing conductive region in a reactive plasma ambient. Moreover, a nitrogen-containing gas is supplied to the reactive plasma ambient for subsequently depositing a metal nitrogen compound. Thereafter, the supply of the nitrogen- containing gas is discontinued to deposit the metal again. Additionally, a heat treatment is carried out to form the metal silicide portion, wherein the metal silicide is formed substantially from metal located between the silicon- containing region and the metal nitrogen compound.
- Figures la-lc schematically show cross-sectional views of a semiconductor device including a suicided portion formed according to a typical prior art process.
- Figures 2a-2d schematically show cross-sectional views of a semiconductor device during various manufacturing stages pursuant to one illustrative embodiment of the present invention.
- illustrative embodiments of die present invention will be described by referring to a field effect transistor including silicon-containing conductive regions. It should be understood, however, that the present invention is applicable to any silicon-containing conductive region provided in an integrated circuit.
- certain die areas or individual semiconductor elements may be connected by polysilicon lines, which may, in accordance with design requirements, have a relatively small cross-sectional area so that any improvement in the conductivity of these lines will significantly contribute to an enhancement of the overall performance of the integrated circuit.
- Figure 2a shows a schematic cross-sectional view of a semiconductor element 200 in the form of a field effect transistor having essentially the same components and parts as already described in Figure la.
- the corresponding components and parts are indicated by the same reference numerals except for a leading "2" instead of a leading "1.”
- the semiconductor element 200 comprises shallow trench isolations 203 formed in a substrate 201, wherein the substrate 201 may be any appropriate substrate including, for example, a silicon substrate, a silicon-on-insulator substrate, and the like.
- Drain and source regions 205 are separated by a well region 202 having a central portion over which a gate insulation layer 206 is formed that electrically isolates a gate electrode 209 from the well region 202.
- sidewall spacers 207 are located at the sidewalls of the gate electrode 202.
- the process flow for forming the semiconductor element 200 may include substantially the same process steps as already described with reference to Figure la. Thus, a corresponding description is omitted.
- the semiconductor element 200 shown in Figure 2a comprises a layer stack 220 (as described more fully below) that is provided for the subsequent formation of suicided portions in the drain and the source regions 205 and the gate electrode 209.
- Figure 2b schematically shows an enlarged cross-sectional view of a portion of the semiconductor element 200 including the layer stack 220 and a portion of the underlying silicon-containing region, for example, the region 205.
- the layer stack 220 comprises three layers, a first metal layer 221, a second layer 222 comprising a metal nitrogen compound, and a third layer 223 in the form of a metal layer.
- the first metal layer 221 may comprise a refractory metal or any suitable alloy thereof, including, for example, cobalt, titanium, zirconium, tantalum, tungsten, nickel, and the like.
- the second layer 222 may comprise a metal nitrogen compound, such as a metal nitride, formed from one of the above-cited refractory metals.
- the third layer 223 may comprise a metal or an alloy of metals including, for example, any of the above- cited metals.
- the thickness of the individual layers 221, 222 and 223 is selected to meet the specific requirements. That is, the first layer 221 is the material source for the metal silicide portion to be formed in and on the silicon-containing conductive region 205. Thus, the thickness of the first layer 221 is selected to obtain the required thickness of the silicide portions to be formed.
- the thickness of the second layer 222 which will serve as an inert layer, that is, as a diffusion barrier layer substantially hindering diffusion from the first layer 221 to the second layer 222 and/or to the third layer 223 and a chemical reaction between the first layer 221 and the second layer 222 in the subsequent process steps for forming the metal silicide portions, is selected so as to ensure a sufficient protection of the underlying first layer 221 in the subsequent anneal step.
- the metal nitride in the second layer 222 is titanium nitride
- a typical layer thickness is in the range of approximately 10-
- the thickness of the third layer 223, which will serve in the subsequent anneal step as a gettering layer reacting with oxygen atoms or other reactive byproducts to form a metal oxide or any other compound, is accordingly preferably selected to substantially consume all of the oxygen atoms or molecules hitting the surface ' of the third layer 223.
- a thickness in the range of approximately 10-30 nm is sufficient to maintain the degree of undesired oxidation in the first layer 221 within a tolerable range.
- the first layer 221 and the third layer 223 comprise substantially the same metal and the second layer 222 substantially comprises a metal nitride formed from the same metal which forms the first and third layers.
- the second and the third layers 221, 222 and 223 offers the following advantages.
- metal layers are deposited by physical vapor deposition, such as sputter deposition, due to the relatively high degree of uniformity that is achievable over the entire substrate surface.
- the substrate such as the substrate 201
- a reaction chamber (not shown) containing a target, that is, usually a disk- shaped material that is to be deposited on the substrate, and means for generating a plasma ambient.
- a plasma is generated using a noble gas, such as argon, to direct ions and electrons to the target material to liberate target atoms. A portion of the liberated atoms then migrates to the substrate and condenses thereon to form a metal layer, such as the first layer 221.
- the process parameters of the sputter deposition such as chamber pressure, power supplied to the plasma generating means, any DC or AC bias voltage supplied to the substrate, the distance between the target and the substrate, the duration of the deposition process and the like, may be controlled to adjust the thickness of the first layer 221 in accordance with design requirements.
- chamber pressure power supplied to the plasma generating means, any DC or AC bias voltage supplied to the substrate, the distance between the target and the substrate, the duration of the deposition process and the like, may be controlled to adjust the thickness of the first layer 221 in accordance with design requirements.
- a nitrogen-containing gas for example, nitrogen (N 2 )
- nitrogen (N 2 ) is added to the plasma ambient.
- N 2 nitrogen
- many refractory metals such as titanium, zirconium, tantalum, tungsten and the like, form nitrogen compounds during sputter deposition in the presence of nitrogen so that the second layer 222 may be formed as a metal nitride layer.
- the deposition process parameters including the parameters pointed out above, and particularly the flow rate of nitrogen supplied to the reactive plasma ambient, may be controlled to adjust the thickness and the characteristics of the second layer 222.
- the nitrogen supply is discontinued, wherein the plasma ambient is still maintained so that increasingly more metal than metal nitride is deposited on the substrate. This process progresses until substantially all of the residual nitrogen gas is consumed so that finally a substantially "pure" metal layer 223 is produced.
- any nitrogen captured in the target material, or any metal nitride deposited on the target and on the chamber walls may be removed during the deposition process without nitrogen supply so that the contamination with metal nitride in a subsequent sputter deposition process is minimized.
- the deposition process for the third layer 223 is stopped when a required thickness is achieved, or when a required degree of "cleanliness" in the deposition chamber is established. Since the third layer 223 will only act as a sacrificial layer, the thickness is not critical as long as a minimum required effectiveness in gettering oxygen atoms is guaranteed. Consequently, according to this particular embodiment, a layer stack 220 including the three layers 221, 222 and 223 may be formed in an in situ sputter deposition process, thereby significantly improving throughput and tool performance.
- the first layer 221 may be deposited in a first plasma ambient to form, for example, a cobalt layer 221, and subsequently the substrate 201 is exposed to a second plasma ambient including a second target material, for example, titanium, and a nitrogen-containing gas component.
- a second target material for example, titanium
- a nitrogen-containing gas component for example, titanium
- the supply of the nitrogen-containing gas is discontinued and, as described with reference to the foregoing embodiment, gradually a titanium layer 223 is deposited while at the same time the sputter target is decontaminated, as is explained above.
- a material composition may be selected wherein the first layer 221 is chosen to yield an optimized silicide portion, and wherein the second and third layers 222 and 223 are selected to provide for an optimum protection of the first layer 221 during the subsequent heat treatment.
- a heat treatment is carried out to initiate a chemical reaction between the silicon in the silicon-containing conductive region 205 and the first metal layer 221.
- a first anneal step at a first averaged temperature may be performed so as to initiate the chemical reaction between the metal in the first layer 221 and the underlying silicon and to form a metal silicon compound.
- the second layer 222 substantially avoids any up and down diffusion of material of the first and third layers 221, 223, which is particularly advantageous when the first and the third layers each comprise a different metal. Furthermore, the second layer 222 does substantially not react with the metal of the first layer 221.
- any reactive element especially oxygen that may be present in the ambient, is substantially consumed by the third layer 223 by forming a compound, such as an oxide, with these reactive elements.
- the second and third layers 222 and 223 are selectively removed and also any excess material of the first layer 221 that has not reacted with the underlying silicon is removed. Such removal may be accomplished by performing a variety of known wet etching processes.
- Figure 2c schematically shows the metal silicon compound 225 formed in and on the silicon-containing conductive region 205 after removal of any excess material. Subsequently, a further heat treatment, such as a second anneal step, at a higher average temperature than in the first heat treatment, is carried out to transform the metal silicon compound into a metal silicide that exhibits a significantly lower resistance than the silicon in the region 205 or the metal silicon compound 225.
- a further heat treatment such as a second anneal step
- Figure 2d schematically shows the semiconductor element 200 after completion of the second heat treatment, wherein metal silicide portions 208 are formed in and on the source and drain regions 205 and the gate electrode 209. Due to the provision of the second layer 222 during the first heat treatment, the interface between the silicon and the metal silicide region 208 is significantly improved, even if the metal of the first layer 221 differs from that of the third layer 223, since any diffusion activity between these two layers is substantially avoided.
- the illustrative embodiments described so far refer to a layer stack 220 having three different layers, the layer stack 220 may comprise any appropriate number of layers to achieve the required diffusion barrier function and the required gettering function.
- the transition between the second layer 222 and the third layer 223 may be a gradual transition in which the ratio of metal and metal nitride may gradually vary so that the top of the layer stack 220 exhibits an enhanced gettering efficiency, whereas the portion on top of the first metal layer 221 exhibits the required diffusion blocking characteristics.
- the first layer 221 and the second layer 222 may be deposited in an in situ process to form a metal layer 221 and a corresponding nitride layer 222, whereas the third layer 223 may be formed of a different material in a separate deposition process.
- the term layer is to describe a layer that is defined essentially by its function rather by its boundary to an overlying or underlying layer.
- a metal nitride layer that is deposited by sputter deposition with supply of nitrogen and a layer formed, after a certain thickness of metal nitride is obtained, by discontinuing the nitrogen supply may be understood as at least two layers due to the gettering function of the finally formed layer and the inert effect of the former layer, although a clear physical boundary therebetween is difficult to define.
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Abstract
Description
Claims
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
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US282665 | 1994-07-29 | ||
DE10214065A DE10214065B4 (en) | 2002-03-28 | 2002-03-28 | A method of making an improved metal silicide region in a silicon-containing conductive region in an integrated circuit |
DE10214065 | 2002-03-28 | ||
US10/282,665 US20030186523A1 (en) | 2002-03-28 | 2002-10-29 | Method for forming an improved metal silicide portion in a silicon-containing conductive region in an integrated circuit |
PCT/US2002/040806 WO2003083936A1 (en) | 2002-03-28 | 2002-12-20 | Method for forming an improved metal silicide contact to a silicon-containing conductive region |
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EP1490901A1 true EP1490901A1 (en) | 2004-12-29 |
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EP02787066A Withdrawn EP1490901A1 (en) | 2002-03-28 | 2002-12-20 | Method for forming an improved metal silicide contact to a silicon-containing conductive region |
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EP (1) | EP1490901A1 (en) |
JP (1) | JP2005522035A (en) |
CN (1) | CN100380625C (en) |
AU (1) | AU2002351407A1 (en) |
TW (1) | TWI263266B (en) |
WO (1) | WO2003083936A1 (en) |
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JP4819566B2 (en) | 2006-04-28 | 2011-11-24 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
WO2012086540A1 (en) * | 2010-12-21 | 2012-06-28 | シャープ株式会社 | Thin-film transistor and method for manufacturing thin-film transistor |
DE102012003585A1 (en) * | 2012-02-27 | 2013-08-29 | Forschungszentrum Jülich GmbH | Process for producing a monocrystalline metal-semiconductor compound |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
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US5766997A (en) * | 1909-11-30 | 1998-06-16 | Nkk Corporation | Method of forming floating gate type non-volatile semiconductor memory device having silicided source and drain regions |
US5240880A (en) * | 1992-05-05 | 1993-08-31 | Zilog, Inc. | Ti/TiN/Ti contact metallization |
US5365111A (en) * | 1992-12-23 | 1994-11-15 | Advanced Micro Devices, Inc. | Stable local interconnect/active area silicide structure for VLSI applications |
JPH08107087A (en) * | 1994-10-06 | 1996-04-23 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
US5738917A (en) * | 1995-02-24 | 1998-04-14 | Advanced Micro Devices, Inc. | Process for in-situ deposition of a Ti/TiN/Ti aluminum underlayer |
US5700718A (en) * | 1996-02-05 | 1997-12-23 | Micron Technology, Inc. | Method for increased metal interconnect reliability in situ formation of titanium aluminide |
US5970370A (en) * | 1998-12-08 | 1999-10-19 | Advanced Micro Devices | Manufacturing capping layer for the fabrication of cobalt salicide structures |
DE19940758A1 (en) * | 1999-08-27 | 2001-03-15 | Infineon Technologies Ag | Method of manufacturing an HF-FET and HF-FET |
-
2002
- 2002-12-20 AU AU2002351407A patent/AU2002351407A1/en not_active Abandoned
- 2002-12-20 CN CNB028286146A patent/CN100380625C/en not_active Expired - Fee Related
- 2002-12-20 WO PCT/US2002/040806 patent/WO2003083936A1/en active Application Filing
- 2002-12-20 JP JP2003581256A patent/JP2005522035A/en active Pending
- 2002-12-20 EP EP02787066A patent/EP1490901A1/en not_active Withdrawn
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- 2003-03-19 TW TW92105990A patent/TWI263266B/en not_active IP Right Cessation
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TW200307988A (en) | 2003-12-16 |
WO2003083936A1 (en) | 2003-10-09 |
CN100380625C (en) | 2008-04-09 |
CN1623227A (en) | 2005-06-01 |
JP2005522035A (en) | 2005-07-21 |
TWI263266B (en) | 2006-10-01 |
AU2002351407A1 (en) | 2003-10-13 |
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