CN1623227A - Method for forming an improved metal silicide portion in a silicon-containing conductive region in an integrated circuit - Google Patents

Method for forming an improved metal silicide portion in a silicon-containing conductive region in an integrated circuit Download PDF

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CN1623227A
CN1623227A CN 02828614 CN02828614A CN1623227A CN 1623227 A CN1623227 A CN 1623227A CN 02828614 CN02828614 CN 02828614 CN 02828614 A CN02828614 A CN 02828614A CN 1623227 A CN1623227 A CN 1623227A
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metal
layer
substrate
conductive region
plasma environment
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CN100380625C (en
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K·维乔雷克
V·卡勒特
M·霍斯特曼
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GlobalFoundries Inc
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)

Abstract

A layer stack (220) comprising at least three material layers (221, 222, and 223) is provided on a silicon-containing conductive region to form a silicide portion (208) on and in the silicon-containing conductive region, wherein the layer (221) next to the silicon provides the metal atoms for the silicide reaction, the intermediate layer (222) is a metal-nitrogen-compound formed by supplying a nitrogen containing as during deposition, and for formation of the top layer (223), supply for said gas is discontinued. The method may be carried out as an in situ method, thereby significantly improving throughput and deposition tool performance compared to typical prior art processes, in which at least two deposition chambers have to be used.

Description

Siliceous conductive region forms the method for the metal silicide portion of improvement in integrated circuit
Technical field
Generally speaking, the present invention is about making the field of integrated circuit, especially at the semiconductor device that has metal silicide portion on the conductivity silicon-containing regions, to reduce the sheet resistance of these silicon-containing regions.
Background technology
In the integrated circuit of modern super-high density, the physical dimension of device is constantly dwindled to improve device performance and functional.Yet the reduction physical dimension must be born some problem, and these problems may be offseted the advantage of gained after the fractional reduction physical dimension.Generally speaking, dwindle physical dimension, for example, transistor component can cause this transistor component channel length to shorten, thereby and causes this crystal pipe high drive current ability and improve switch speed.But, when dwindling the physical dimension of these transistor components, lead and contact area, that is the zone of power supply property contact around this transistor component, can dwindle along with physical dimension because of the sectional area in these leads and zone and reduce, thereby the resistance that increases, a major issue so become.Yet this sectional area is the resistance of each lead of decision or contact area in conjunction with the material behavior that is included in lead and the contact area.
It seems with this viewpoint, the problems referred to above typical critical feature size of can giving an example, (Critical Dimension CD), for example forms the extension of field-effect transistor channel below gate electrode between transistorized source region and drain region also to be called critical size.Reduce the prolongation of this channel, be commonly referred to as channel length, can reduce, and in transistor component switches, obviously improve about descending and the device performance of rise time because of the less electric capacity of grid and interchannel and than the resistance of short channel.But, shorten channel length and also must bear the reduction problem of any conductor size, the for example field-effect transistor that generally forms with polysilicon, and the contact area that is used for electrically touching transistor drain and source area dwindles so that then will be used for the net sectional area of delivered charge carrier.So, unless the sectional area that dwindles can improve compensating such as the material electric characteristics in gate electrode, drain electrode and source contact area territory, otherwise this lead and contact area still can manifest higher resistance value by forming lead and contact area.
Therefore, improvement comprises as the characteristic of semi-conducting material on conductive region of silicon most important haply.For instance, in modern integrated circuits, individual other semiconductor device, such as main field-effect transistor based on silicon, capacitor and other assembly, wherein each device all is to connect by silicon line and metal wire.Even can improve the resistivity of plain conductor by the aluminium of using always with the displacement as copper, but when needing to improve the electric characteristics in siliceous semiconductor lead and semiconductor contact zone, the process engineer still can face a challenge task.
Generally speaking, even if be in the heavy doping state, when accepting the processing of metal silicide portion, these silicon-containing regions can know that showing than silicon is low sheet resistance.
On siliceous conductive region, form the general existing technology of metal silicide portion, shown in 1a to 1c figure.1a figure is the generalized section that icon one is formed at the field-effect transistor on the substrate 101, and this substrate can be silicon substrate or any other is fit to the substrate of carrying field-effect transistor 100.The size system of this field-effect transistor 100 is by being defined as the formed shallow trench isolation 103 of the insulation material of silicon dioxide.The gate insulator 106 that comprises silicon dioxide is for example isolated the gate electrode 109 that roughly comprises polysilicon according to these field-effect transistor 100 desirable characteristics from the well territory 102 that may contain N type and/or P type foreign atom.And the source electrode of label 105 indications and drain region system provide counter-doping in well territory 102 by well territory 102 again.The surf zone in well territory 102 is positioned at gate insulator 106 belows, also is called channel region.The side wall spacer 107 that separate drain and the lateral separation of source region 105 claim among the 1a figure comprises silicon dioxide for example or silicon nitride for channel length forms with the sidewall of grid 109 and contacts.Form metal silicide portion 108 in this drain electrode and source region 105 and gate electrode 109 top layers, generally comprise the cobalt silicide (CoSi of low ohm state 2), to reduce indivedual siliceous conductive regions, the resistance of gate electrode 109 and this source electrode and drain region 105 for example.
Structure shown in the 1a figure is generally formed by following processing step.At first, form trench isolation 103 by trench etched and backfill silicon dioxide after, form gate insulator 106 with for example oxidation method for making.Then, form gate electrode 109 through complicated little shadow deposition techniques polysilicon and patterning.Then, carry out first implantation step and on this source electrode and drain region 105, define more shallow doped region, form side wall spacer 107 then with implantation cover curtain as the follow-up implantation step that defines this source electrode and drain region 105.Afterwards, deposition comprises fire resistance metal levels such as titanium, tantalum, zirconium, cobalt and nickel on the structure shown in the 1a figure.Generally speaking, this metal system to be comprising the sputter instrument of the corresponding target that required metal can be provided, and makes with sputter-deposited method deposition.
1b figure is the amplification profile of these drain region 105 parts of icon, this figure comprises the refractory metal layer 110 that is deposited on the drain region 105 when refractory metal layer 110 is shown cobalt greatly and formed, and is typically provided with the cap rock 111 that can comprise titanium or titanium nitride in these refractory metal layer 110 top layers.These cap rock 111 general systems form with the sputter-deposited method, and wherein this substrate 101 places separate deposition chamber to handle, to form this cap rock 111.
Then, first annealing steps lies in general under 440 ℃ to 600 ℃ first mean temperature, carries out as refractory metal with cobalt, with the chemical reaction between initial this refractory metal layer 110 and drain region 105 silicon.Certainly, gate electrode 109 also should be noted that with the corresponding reaction that source region 105 is produced.During first annealing steps, for example the metal level 110 of cobalt and source region 105 silicon are spread and are formed cobalt list silicide.When this reaction took place, if essence comprises the cap rock 111 of titanium, being used as so-called was the absorbed layer that main preferable reaction forms titanium oxide with any oxygen atom in anneal environment.Then this titanium cap rock 111 will obviously weaken the oxidation reaction of refractory metal layer 110 bottom cobalts, and form cobalt oxide and strengthen the resistance value of final gained silicon layer with other method.Yet, diffusion up during first annealing steps, the formation of titanium and cobalt tendency roughly needn't with the compound of pasc reaction, so, there is no effect for low ohm silicide regions.
On the other hand, if cap rock 111 roughly comprises titanium nitride, the roughly inert layer of this cap rock 111 during then as first annealing steps; Yet the bottom cobalt that this cap rock 111 only is provided in the anneal environment avoids by the due care ability of residual oxygen oxidation.And, during annealing and cobalt list silicide form, when using titanium cap rock 111, possible hyperplasia titanium and constitute the crystal grain edge.
Thereafter, the non-reacted cobalt in cap rock 111 and the refractory metal layer 110 can remove by the selectivity wet etch process.Then, in higher than the mean temperature of first annealing steps, generally implement second annealing steps down between 650 ℃ to 700 ℃, if refractory metal layer 110 is to transform cobalt list silicide with cobalt to become more stable cobalt disilicide, then cobalt disilicide can obviously show than the lower sheet resistance value of cobalt list silicide.Carry as the front, can be as for the titanium of titanium cap rock 111 in the crystal grain edge hyperplasia of cobalt list silicide, and the main the evolving path that is used for chemical reaction during second annealing steps can be covered by this hyperplasia titanium significantly.
Moreover, as shown in 1c figure, during initial annealing steps, can form cobalt titanium layer 112, reduce the thickness of silicide portions 108 then.And because crystal grain edge hyperplasia has titanium, the interface 113 of relatively final gained silicide portions 108 and bottom silicon-containing regions 105 is more coarse, thereby, owing to increasing, the charge carrier dissipation role shows that resistance value strengthens.If cap rock 111 is the use titanium nitride, then roughly can avoid cobalt titanium layer 112 to produce, but the silicide portions 108 of final gained may comprise the cobalt oxide of suitable volume on the contrary, causes the resistance value of this silicide portions 108 also can improve.
Be with, though existing technology must so with the optimized viewpoint of technology, still have it to improve the space about the silicide portions quality by form the overall resistance that silicide portions obviously improve these siliceous conductive regions on siliceous conductive region.
Summary of the invention
Generally speaking; the present invention means a kind of method that forms silicide portions on siliceous conductive region; this method system provides the storehouse of multilayer; wherein the one layer or more metal level is used to provide the metal that forms this metal silicide portion; when in initial chemistry between this metal and the silicon between the stage of reaction, other layer of storehouse can be used for protecting bottom metal layer.Moreover, according to a viewpoint,, can obviously simplify the complicated deposition technique that needs two kinds of separate deposition chamber by in original position method cambium layer storehouse, therefore, can deposit this metal level and protective layer with single dislodger.
According to an embodiment of the present invention, on siliceous conductive region, form the method that reduces resistance region, this method comprises preparation one substrate, be formed with siliceous conductive region on this substrate, and deposit layer stack on this siliceous conductive region, wherein, this layer stack comprises the first metal layer, second metal level and the metal nitride layer between this first and second metal level.In addition, this method comprises the heat treatment substrate to form the metal nitride part on this siliceous conductive region.
Another embodiment of the present invention lies in the method that forms silicide portions on the formed siliceous conductive region of substrate, and the siliceous conductive region that this method is contained in the reactive plasma environment deposits a metal.And, provide nitrogenous gas to the reactive plasma environment that is used for the plated metal nitride haply.Thereby the nitrogenous gas supplied of plated metal can interrupt once more.In addition, implement heat treatment and form in the metal silicide portion, this metal silicide can roughly form from the metal between this silicon-containing regions and metal nitride.
Description of drawings
1a to 1c figure system illustrates according to general existing technology and forms, and has the generalized section of the semiconductor device of silicide portions; And
2a to 2d figure system illustrates according among the present invention one explanation embodiment, and semiconductor device places the generalized section of each operation stage.
Embodiment
Explanation embodiment of the present invention is as described below.Present emphasis for clear, this specification is not addressed actual all structures of finishing kenel.Certainly should be appreciated that, when the real embodiment of any this kind of exploitation, must make many decisions relevant,, for example meet relevant with system and the relevant restrictive condition that changes to some extent with commerce along with the difference of embodiment so that reach inventor's specific objective with enforcement.In addition, we should understand, and this kind development may be complicated and consuming time, yet, will be a kind of those of ordinary skills to be disclosed the regular works that thing can be engaged in after described consulting the present invention.
Below, the present invention illustrates that embodiment will narrate the field-effect transistor of the siliceous conductive region of a tool.The present invention of right notice can be applicable to anyly provide integrated circuit used siliceous conductive region.For example, available polycrystalline silicon conducting wire connects grained region or each semiconductor subassembly of some, also can design according to need, has relative small cross sections to improve the conductivity of polycrystalline silicon conducting wire, in order to do the overall efficiency that obviously helps to promote integrated circuit.
2a figure system illustrates the generalized section of semiconductor subassembly 200, and this semiconductor subassembly cording has and necessary assembly shown in the 1a figure or the identical form of field-effect transistors of part essence.Numeral 2 divided by the front replaces outside the numeral 1, and other corresponding assembly and part are all with the same components symbolic representation.Therefore, this semiconductor subassembly 200 comprises the shallow trench isolation 203 that is formed on the substrate 201, and wherein this substrate 201 can be any suitable substrate and comprises for example silicon substrate, silicon on insulator substrate and similar substrate etc.Drain electrode separates with well territory 202 with source region 205, and this well territory 202 has central part, is formed with the gate insulator 206 that gate electrode 209 and well territory 202 electricity are isolated on this central part.And the sidewall that is positioned at this gate electrode 209 is provided with side wall spacer 207.
The making flow process that is used to form this semiconductor subassembly 200 comprises the same steps as that has illustrated in 1a figure as haply.So each corresponding step is omitted.And the semiconductor subassembly 200 shown in 2a figure comprises a stack layer 220 (following meeting is detailed descriptionthe more), and this stack layer can form silicide portions afterwards on this drain electrode and source region 205 and this gate electrode 209.
2b figure system illustrates this semiconductor subassembly 200 part amplification sectional views, and this semiconductor subassembly 200 comprises this stack layer 220 and a part of bottom silicon-containing regions that for example should zone 205.According to a specific embodiment of the present invention, this stack layer 220 comprises three layers: the second layer 222 of the first metal layer 221, containing metal nitride, and the 3rd layer 223 of metal level form.This first metal layer 221 can comprise refractory metal or its suitable alloy comprises for example cobalt, titanium, zirconium, tantalum, tungsten, nickel etc.This second layer 222 can comprise metal nitride, such as with the formed metal nitride of one of above-mentioned refractory metal of quoting as proof.Comprise a metal or metal alloy for the 3rd layer 223 and comprise for example above-mentioned any of metal of quoting as proof.Each layer 221,222 and 223 thickness system are selected according to specific needs.That is, this ground floor 221 be be formed within this siliceous conductive region 205 and on metal silicide portion be material source.Therefore, the thickness of this ground floor 221 system is selected according to the thickness that needs that this silicide portions of formation obtains.This second layer 222 is used as inert layer; that is to say to be used as and hinder the diffused barrier layer that ground floor 221 diffuses to the second layer 222 and/or the 3rd layer 223 haply; and hinder in being used to form the subsequent process steps of this metal silicide portion; between the chemical reaction of 222 of this ground floor 221 and the second layers, the protection of filling part with these bottom ground floor 221 tools under the guarantee subsequent anneal step is selected by the thickness of this second layer 222 system.For example, if the metal nitride of the second layer 222 is a titanium nitride, generally this layer thickness approximately between 10 how rice to 100 how between the rice.Be used for subsequent annealing step for the 3rd layer 223 and react with formation metal oxide or any other compound with oxygen atom or other reactive time product, so preferable being chosen as of the 3rd layer 223 thickness consumes oxygen atom or the oxygen molecule that all collide the 3rd layer of 223 surface haply as absorbed layer.Generally speaking, thickness between about 10 how rice to 30 how rice can keep in this ground floor 221 unexpected degree of oxidation fully in the acceptable scope.
In a specific embodiment, this ground floor 221 and the 3rd layer 223 have same metal haply, and this second layer 222 comprises haply by forming this first and the 3rd layer of formed metal nitride of same metal.Make this first, second and third layer 221,222 and 223 with same metal following advantage can be provided.
Because it is higher relatively to reach the homogeneity degree on deposition whole base plate surface, preferably, on the major diameter substrate, make the super-high density integrated circuit, with as physical vaporous deposition depositing metal layers such as sputter-deposited methods.During sputter-deposited, insert (not shown) in the reactive tank that contains subject matter such as the substrate of substrate 201, this subject matter that is be deposited on and be generally discoidal material on this substrate, this reactive tank also contains the mechanism that produces plasma environment.Generally speaking, use noble gas to produce plasma, disengage the target atom to the subject matter material with guiding ion and electronics as argon.Treat that the target atom that disengages of part migrates the metal level that forms on the capacitor to substrate and the substrate such as this ground floor 221.The technological parameter of this sputter-deposited method, as the power supply of groove pressure, plasma generating equipment, any interchange or the spacing distance between direct voltage, subject matter and the substrate, the delayed action of depositing operation etc. of supply substrate, all can be according to the control of design needs to adjust the thickness of this ground floor 221.Sputter-deposited instrument and technology have been set up appropriate in this skill aspect, so the detailed description of sputter is omitted.
After treating that this ground floor 221 depositions reach desired thickness, the nitrogenous gas of for example nitrogen is added to plasma environment.Can find many refractory metals,, during the sputter-deposited that nitrogen oxygen manifests, form nitride, to form the second layer 222 as metal nitride layer such as titanium, zirconium, tantalum, tungsten etc.Moreover this deposition process parameters comprises the parameter of above-mentioned indication, and thickness and the characteristic of nitrogen flow rate may command to adjust this second layer 222 that is used in particular for supplying reactive plasma environments.After the thickness of wishing to get when reaching, interrupt nitrogen supply (NS) and still keep border, plasma border, making increases more metal deposition on this substrate than this metal nitride.This technology continues to all approach exhaustions roughly of whole remaining nitrogen always, with in the final generation metal level 223 of " purely " roughly.
Person very, any nitrogen that the target material absorbs also or the metal nitride that deposits on subject matter or cell wall, all can remove during the depositing operation of no nitrogen supply (NS), drops to minimum with the metal nitride pollution with follow-up sputter deposition process.When deposition reaches the thickness that needs, or dislodger is when reaching the degree of " desire cleaning ", and the 3rd layer 223 depositing operation can be stopped.Owing to only is used as and sacrifices for the 3rd layer 223, so its thickness is not as long as influencing minimizing as much as possible under the situation of bringing into play the required benefit that absorbs oxygen atom, strict restriction.Thereby, according to this specific embodiment, comprise three layer 221,222 and 223 stack layer 220 can form in the sputter deposition process original position, with obvious productivity and the tool performance improved.
According to another embodiment explanation, this ground floor 221 can be deposited in first plasma environment forming for example cobalt layer 221, and substrate 201 roughly is exposed to comprises the second target material, in second plasma environment as titanium and nitrogenous gas composition.Explanation as above, treat titanium nitride layer deposition after, interrupt the nitrogenous gas supply, and embodiment is described as described above, still the untainted while progressively deposits titanium layer 223 in this sputter subject matter.Mode according to this, the selection of material composite can select for use ground floor 221 generating suitable silicide portions, and select the second layer and the 3rd layer 222 and 223 for use, being that ground floor 221 provides due care during subsequent heat treatment.
Then next step be implement heat treatment with initial between the silicon of this siliceous conductive region 205 and the chemical reaction between the first metal layer 221.For this purpose, according to an embodiment, press the contained metal kenel of ground floor 221, first mean temperature system when first annealing steps is implemented is used for initial metal on ground floor 221 and the chemical reaction between the bottom silicon, with the formation metal silicide.During this annealing steps, the second layer 222 is roughly avoided the fluctuating diffusion of any first and the 3rd layer of 221,223 material, and is especially more favourable when comprising different metal respectively for first and the 3rd layer.Moreover the second layer 222 can't react with the metal of ground floor 221 haply really.And any reactive element, the particularly oxygen atom that can manifest in this environment are to be subjected to forming the 3rd layer 223 of compound jointly as a little therewith reactive elements of oxygen roughly to exhaust haply.
Afterwards, optionally remove the second layer and the 3rd layer 222 and 223, and in the ground floor 221 not with any excess material of bottom pasc reaction.These remove step and can various existing wet etch process implement to finish.
After 2c figure system slightly is shown in any excess material and removes, be formed among the siliceous conductive region 205 and on metal silicide 225.Thereafter, further implement heat treatment as second annealing steps, the used mean temperature of this second annealing steps is higher than first heat treatment, use enforcement this metal silicide is changed into metal silicide, the resistance value of metal silicide is starkly lower than the resistance value of the silicon or the metal silicide 225 in this zone 205.
2d figure system illustrates the semiconductor subassembly for the treatment of after second heat treatment is finished 200, is formed with metal silicide portion 208 on wherein reaching among this source electrode and drain region 205 and the gate electrode 209.Because the second layer 222 prepares during lying in first heat treatment, therefore obviously improve the interface in silicon and 208 in metal silicide zone, even if the metal of ground floor 221 is different with the 3rd layer 223 metal, the proliferation activity between thought is times two-layer still can roughly be avoided.
Though up to the present the described stack layer 220 of embodiment only has three layers of dissimilar layer, only for reaching necessary diffusion barrier function and necessary absorption function, this stack layer 220 can comprise any suitable number of plies.Particularly, transition system between the second layer 222 and the 3rd layer 223 gradually changes according to the ratio of metal and metal nitride and transformation gradually, therefore stack layer 220 top layers manifest the absorption enhancing efficiency, and the top layer of this first metal layer part presents the characteristic of necessary diffusion hindered on the contrary.This phenomenon supports embodiment to adopt in-situ deposition technology to be correct especially, and wherein nitrogen supply (NS) can be controlled the metal configuration in the required metal nitride wished to get and the second layer and the 3rd layer.Simultaneously, this ground floor 221 and the second layer 222 can form metal level 221 and corresponding nitride layer 222 with in-situ deposition technology respectively in an embodiment, and the 3rd layer 223 tie up in the separation depositing operation and form with different material.
In what other embodiment must notice be, obtain required protective layer for making the metal that forms on the silicide, this stack layer 220 can comprise more than three layers.In other embodiment, particularly this stack layer lies in the two-layer or three layers of person of in-situ deposition, and this layer is that its function of mat but not its covering or bottom border define in essence.For example, sputter-deposited method plated metal nitride layer with the supply of nitrogen, and behind the metal nitride that obtains certain thickness, the layer that forms by interrupting nitrogen supply, can understand and have two layers at least, system is owing to final cambial absorption function and inactive effect, though the very difficult physical boundary of knowing that defines therebetween.
More than the special embodiment of Jie Luing is only in order to explanation the present invention, and the present invention can do to modify and enforcement in a different manner, but for the those skilled in the art of this skill aspect, after reading this specification of acquistion, can many equivalent way implement when understanding the present invention.For example, order that can be different is implemented the processing step of the above-mentioned proposition of the present invention.Moreover the explanation, desire does not limit the thin portion that is configured to design shown in it in following claim.Therefore, but the specific embodiment that discloses more than clear proof can be done change or modification, and all change system's consideration within the spirit and scope of the present invention.Thus, the present invention proposes following claim and asks for protection.

Claims (13)

1. one kind forms the method that reduces resistance region on siliceous conductive region, and this method comprises:
One substrate (201) is provided, is formed with this siliceous conductive region on this substrate;
Deposition layer stack (220) is to this siliceous conductive region, and this layer piles up and comprises the first metal layer (221), second metal level (223) and the metal nitride layer (222) between this first and second metal level; And
This substrate of heat treatment (201) is to form metal silicide portion (208) on this siliceous conductive region.
2. the method for claim 1, wherein this ground floor (221), the second layer (223) and this metal nitride layer (222) comprise same metal.
3. the method for claim 1, wherein depositing this layer stack (220) is to implement on original position.
4. the method for claim 1 wherein deposits this layer stack (220) and comprises:
This first metal layer of sputter-deposited (221) in plasma environment;
The supply nitrogenous gas to this plasma environment to deposit this metal nitride layer (223); And
Interrupt the nitrogenous gas supply of this second metal level (223) of deposition.
5. the method for claim 1 wherein deposits this layer stack (220) and comprises:
Expose this substrate (201) to first plasma environment to deposit this first metal layer (221);
When the supply nitrogenous gas to this second plasma environment when depositing this metal nitride layer (222), expose this substrate to the second plasma environment; And
Interruption is to the nitrogenous gas supply of this second plasma environment, to deposit this second metal level (223).
6. the method for claim 1 wherein deposits this layer stack (220) and comprises:
Expose this substrate (201) to first plasma environment to deposit this first metal layer (221);
The supply nitrogenous gas to this first plasma environment to deposit this metal nitride layer (222); And
Expose this substrate (201) to second plasma environment to deposit this second metal level (223).
7. the method for claim 1, wherein this substrate of heat treatment (201) is contained in and carries out first annealing process under first mean temperature and be to carry out second annealing process under high second mean temperature than this first mean temperature.
8. method as claimed in claim 7, also be included in this second annealing process before, remove the non-reactive metal on this second metal level (223), this metal nitride layer (222) and this first metal layer (221).
9. the method for claim 1, wherein this first metal layer (221) comprises one of them of cobalt, titanium, zirconium, tantalum, nickel and tungsten.
10. the method for claim 1, wherein this second metal level (223) comprises one of them of cobalt, titanium, zirconium, tantalum, nickel and tungsten.
11. the method for claim 1, wherein this metal nitride layer (222) comprises one of them of titanium, zirconium, tantalum, nickel and tungsten.
12. form the method for silicide portions in the siliceous conductive region that forms on substrate, this method comprises:
Deposition one metal on the siliceous conductive region of in plasma environment this;
The supply nitrogenous gas to this plasma environment with on this plated metal the deposition one metal nitride;
The supply of interrupting this nitrogenous gas is with this metal of deposition on this metal nitride; And
This substrate of heat treatment (201) is to form this metal silicide portion (208), and wherein this metal silicide roughly is to form from the metal that is positioned between this siliceous conductive region and metal nitride.
13. method as claimed in claim 12, wherein on this siliceous conductive region plated metal to produce ground floor (221), deposit this metal nitride and act as the second layer (222) of inert layer, and plated metal act as the 3rd layer (223) of absorbed layer with production on this metal nitride with production.
CNB028286146A 2002-03-28 2002-12-20 Method for forming an improved metal silicide portion in a silicon-containing conductive region in an integrated circuit Expired - Fee Related CN100380625C (en)

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DE10214065A DE10214065B4 (en) 2002-03-28 2002-03-28 A method of making an improved metal silicide region in a silicon-containing conductive region in an integrated circuit
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US10/282,665 US20030186523A1 (en) 2002-03-28 2002-10-29 Method for forming an improved metal silicide portion in a silicon-containing conductive region in an integrated circuit

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US5766997A (en) * 1909-11-30 1998-06-16 Nkk Corporation Method of forming floating gate type non-volatile semiconductor memory device having silicided source and drain regions
US5240880A (en) * 1992-05-05 1993-08-31 Zilog, Inc. Ti/TiN/Ti contact metallization
US5365111A (en) * 1992-12-23 1994-11-15 Advanced Micro Devices, Inc. Stable local interconnect/active area silicide structure for VLSI applications
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US5738917A (en) * 1995-02-24 1998-04-14 Advanced Micro Devices, Inc. Process for in-situ deposition of a Ti/TiN/Ti aluminum underlayer
US5700718A (en) * 1996-02-05 1997-12-23 Micron Technology, Inc. Method for increased metal interconnect reliability in situ formation of titanium aluminide
US5970370A (en) * 1998-12-08 1999-10-19 Advanced Micro Devices Manufacturing capping layer for the fabrication of cobalt salicide structures
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