DE10214065B4 - A method of making an improved metal silicide region in a silicon-containing conductive region in an integrated circuit - Google Patents
A method of making an improved metal silicide region in a silicon-containing conductive region in an integrated circuit Download PDFInfo
- Publication number
- DE10214065B4 DE10214065B4 DE10214065A DE10214065A DE10214065B4 DE 10214065 B4 DE10214065 B4 DE 10214065B4 DE 10214065 A DE10214065 A DE 10214065A DE 10214065 A DE10214065 A DE 10214065A DE 10214065 B4 DE10214065 B4 DE 10214065B4
- Authority
- DE
- Germany
- Prior art keywords
- metal
- layer
- silicon
- metal layer
- nitrogen compound
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 170
- 239000002184 metal Substances 0.000 title claims abstract description 170
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 50
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 50
- 239000010703 silicon Substances 0.000 title claims abstract description 50
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 26
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title description 8
- 238000000034 method Methods 0.000 claims abstract description 48
- 229910017464 nitrogen compound Inorganic materials 0.000 claims abstract description 37
- 150000002830 nitrogen compounds Chemical class 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000000151 deposition Methods 0.000 claims abstract description 25
- 230000008569 process Effects 0.000 claims abstract description 24
- 238000011065 in-situ storage Methods 0.000 claims abstract description 9
- 230000002829 reductive effect Effects 0.000 claims abstract description 8
- 230000007704 transition Effects 0.000 claims abstract description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 31
- 239000010936 titanium Substances 0.000 claims description 31
- 229910052719 titanium Inorganic materials 0.000 claims description 31
- 230000008021 deposition Effects 0.000 claims description 18
- 239000010941 cobalt Substances 0.000 claims description 17
- 229910017052 cobalt Inorganic materials 0.000 claims description 17
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 17
- 238000004544 sputter deposition Methods 0.000 claims description 13
- 239000007789 gas Substances 0.000 claims description 10
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 8
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 5
- 229910052726 zirconium Inorganic materials 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 163
- 239000000463 material Substances 0.000 description 20
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 17
- 239000004065 semiconductor Substances 0.000 description 14
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 12
- 150000004767 nitrides Chemical class 0.000 description 12
- 230000005669 field effect Effects 0.000 description 10
- 238000000137 annealing Methods 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 9
- 239000003870 refractory metal Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052757 nitrogen Inorganic materials 0.000 description 7
- 238000005137 deposition process Methods 0.000 description 6
- 125000004429 atom Chemical group 0.000 description 4
- AIOWANYIHSOXQY-UHFFFAOYSA-N cobalt silicon Chemical compound [Si].[Co] AIOWANYIHSOXQY-UHFFFAOYSA-N 0.000 description 4
- 230000006872 improvement Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 150000003377 silicon compounds Chemical class 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 125000004430 oxygen atom Chemical group O* 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910000428 cobalt oxide Inorganic materials 0.000 description 2
- NNSIWZRTNZEWMS-UHFFFAOYSA-N cobalt titanium Chemical compound [Ti].[Co] NNSIWZRTNZEWMS-UHFFFAOYSA-N 0.000 description 2
- IVMYJDGYRUAWML-UHFFFAOYSA-N cobalt(ii) oxide Chemical compound [Co]=O IVMYJDGYRUAWML-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 238000005247 gettering Methods 0.000 description 2
- -1 metal nitride Chemical class 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052756 noble gas Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Verfahren
zur Bildung eines Gebiets mit verringertem Widerstand in einem Silizium
enthaltenden leitenden Gebiet, wobei das Verfahren umfasst:
Bereitstellen
eines Substrats mit dem darauf gebildeten Silizium enthaltenden
leitenden Gebiet;
Abscheiden eines Schichtstapels auf dem Silizium
enthaltenden leitenden Gebiet, wobei der Schichtstapel eine erste
Metallschicht, eine zweite Metallschicht, die als eine Opferschicht
dient, und eine Metallstickstoffverbindungsschicht, die zwischen
der ersten und der zweiten Metallschicht angeordnet ist, aufweist,
wobei zumindest das Abscheiden der zweiten Metallschicht und der
Metallstickstoffverbindungsschicht in-situ unter Verwendung des
gleichen Metalls und unter Bildung eines graduellen Überganges zwischen
der zweiten Metallschicht und der Metallstickstoffverbindungsschicht
ausgeführt
wird;
Wärmebehandeln
des Substrats, um einen Metallsilizidbereich in dem Silizium enthaltenden
leitenden Gebiet zu bilden; und ganzflächiges Entfernen der zweiten
Metallschicht. A method of forming a reduced resistance region in a silicon-containing conductive region, the process comprising:
Providing a substrate having the conductive region containing silicon thereon;
Depositing a layer stack on the silicon-containing conductive region, the layer stack comprising a first metal layer, a second metal layer serving as a sacrificial layer, and a metal nitrogen compound layer disposed between the first and second metal layers, wherein at least depositing the second Metal layer and the metal nitrogen compound layer is performed in situ using the same metal and forming a gradual transition between the second metal layer and the metal nitrogen compound layer;
Heat treating the substrate to form a metal silicide region in the silicon-containing conductive region; and full-surface removal of the second metal layer.
Description
Im Allgemeinen betrifft die vorliegende Erfindung das Gebiet der Herstellung integrierter Schaltungen und betrifft insbesondere Halbleiterelemente mit Metallsilizidbereichen in leitenden Silizium enthaltenden Gebieten, um den Schichtwiderstand dieser Gebiete zu reduzieren.in the In general, the present invention relates to the field of manufacture integrated circuits and in particular relates to semiconductor elements with Metal silicide regions in conductive silicon containing regions, to reduce the sheet resistance of these areas.
In modernen integrierten Schaltungen mit äußerst hoher Packungsdichte werden die Bauteilstrukturen ständig kleiner, um die Leistungsfähigkeit und Funktionalität des Bauteils zu steigern. Das Schrumpfen der Strukturgrößen zieht jedoch gewisse Probleme nach sich, die teilweise die mittels der reduzierten Strukturgrößen gewonnenen Vorteile aufheben können. Im Allgemeinen führt die Reduzierung der Strukturgrößen von beispielsweise einem Transistorelement zu einer geringeren Kanallänge in dem Transistorelement und führt damit zu einer höheren Stromtreiberfähigkeit und einer verbesserten Schaltgeschwindigkeit des Transistors. Beim Verringern der Strukturgrößen dieser Transistorelemente wird jedoch der ansteigende elektrische Widerstand von Leitungen und Kontaktgebieten, d.h. von Gebieten, die einen elektrischen Kontakt zur Peripherie des Transistorelements herstellen, ein dominierender Aspekt, da die Querschnittsfläche dieser Leitungen und Gebiete mit geringer werdenden Strukturgrößen ebenfalls kleiner wird. Die Querschnittsfläche bestimmt jedoch in Kombination mit den in den Leitungen und Kontaktgebieten enthaltenen Material u.a. den Widerstand der entsprechenden Leitung oder des Kontaktgebiets.In modern integrated circuits with extremely high packing density become the component structures constantly less to the power and functionality to increase the component. The shrinking of the structure sizes pulls However, there are certain problems, some of which are caused by the gained reduced structural sizes Can lift benefits. In general leads the reduction of structure sizes of For example, a transistor element to a smaller channel length in the transistor element and leads thus to a higher Stromtreiberfähigkeit and an improved switching speed of the transistor. At the Decrease the structure sizes of this However, transistor elements become the rising electrical resistance of lines and contact areas, i. of areas that have a make electrical contact to the periphery of the transistor element, a dominant aspect because the cross-sectional area of these conduits and areas becomes smaller with decreasing feature sizes. The cross-sectional area but in combination with those in the lines and contact areas contained material u.a. the resistance of the corresponding line or the contact area.
Die zuvor genannten Probleme können beispielhaft für eine typische kritische Strukturgröße in dieser Hinsicht, die auch als kritische Dimension (CD) bezeichnet wird, etwa die Ausdehnung des Kanals eines Feldeffekttransistors, der sich unter einer Gateelektrode zwischen einem Sourcegebiet und einem Draingebiet des Transistors bildet, dargestellt werden. Das Verringern dieser Ausdehnung des Kanals, die für gewöhnlich als Kanallänge bezeichnet wird, kann deutlich die Bauteilleistungsfähigkeit hinsichtlich der Abfall- und Anstiegszeiten während des Schattens des Transistorelements aufgrund der geringeren Kapazität zwischen der Gateelektrode und dem Kanal und aufgrund des verringerten Widerstands des kürzeren Kanals verbessern. Das Reduzieren der Kanallänge zieht jedoch die Verringerung der Größe von Leitungen, etwa der Gateelektrode des Feldeffekttransistors, die für gewöhnlich aus Polysilizium gebildet ist, und der Kontaktgebiete, die elektrischen Kontakt zu den Drain- und Sourcegebieten des Transistors liefern, nach sich, so dass folglich der verfügbare Querschnitt für den Ladungsträgertransport verringert ist. Folglich zeigen die Leitungen und die Kontaktgebiete einen höheren Widerstand, sofern der reduzierte Querschnitt nicht durch Verbessern der elektrischen Eigenschaften des Materials, das die Leitungen und die Kontaktgebiete, etwa die Gateelektrode und die Drain- und die Sourcekontaktgebiete, bildet, kompensiert wird.The previously mentioned problems exemplary for a typical critical feature size in this regard, the also referred to as the critical dimension (CD), such as the extent of the channel of a field effect transistor extending under a gate electrode between a source region and a drain region of the transistor forms are presented. Reducing this extent of the Channels for usually as channel length can be clearly indicated, the component performance in terms of fall and rise times during shadowing of the transistor element due to the lower capacity between the gate electrode and the channel and due to the reduced Resistance of the shorter Improve channels. Reducing the channel length, however, reduces the reduction in the Size of lines, about the gate electrode of the field effect transistor, which usually out Polysilicon is formed, and the contact areas, the electrical Provide contact to the drain and source regions of the transistor, by itself, so consequently the available cross section for the carrier transport is reduced. Consequently, the lines and the contact areas a higher one Resistance provided the reduced cross section is not improved by the electrical properties of the material that the wires and the contact areas, such as the gate electrode and the drain and the source contact areas, forms, is compensated.
Es ist daher von besonderer Bedeutung, die Eigenschaften von leitenden Gebieten zu verbessern, die im Wesentlichen aus Halbleitermaterial, etwa Silizium, aufgebaut sind. Beispielsweise sind in modernen integrierten Schaltungen die einzelnen Halbleiterelemente, etwa Feldeffekttransistoren, Kondensatoren und dergleichen hauptsächlich auf der Basis von Silizium aufgebaut, wobei die einzelnen Bauelemente durch Siliziumleitungen und Metallleitungen verbunden sind. Während der Widerstand der Metallleitungen verbessert werden kann, indem das üblicherweise verwendete Aluminium durch beispielsweise Kupfer ersetzt wird, sind Prozessingenieure mit einer herausfordernden Aufgabe konfrontiert, wenn eine Verbesserung der elektrischen Eigenschaften von Silizium enthaltenden Halbleiterleitungen und Halbleiterkontaktgebieten erforderlich ist.It is therefore of particular importance, the properties of conductive To improve areas consisting essentially of semiconductor material, such as Silicon, are constructed. For example, in modern integrated Circuits the individual semiconductor elements, such as field effect transistors, capacitors and the like mainly built on the basis of silicon, with the individual components connected by silicon lines and metal lines. During the Resistance of the metal lines can be improved by the usual used aluminum is replaced by, for example, copper Process engineers faced with a challenging task if an improvement in the electrical properties of silicon required semiconductor lines and semiconductor contact areas required is.
Typischerweise werden diese Silizium enthaltenden Gebiete so behandelt, um einen Metallsilizidbereich darauf zu erhalten, der einen deutlich kleineren Schichtwiderstand als Silizium aufweist, selbst wenn dieses stark dotiert ist.typically, These silicon-containing regions are treated as one Metal silicide on it to get a much smaller Has sheet resistance as silicon, even if this is strong is doped.
Mit
Bezug zu
Die
in
Anschließend wird
ein erster Ausheizschritt bei einer ersten Durchschnittstemperatur,
typischerweise im Bereich von 440–600°C für Kobalt als das hochschmelzende
Metall, durchgeführt,
um eine chemische Reaktion zwischen dem hochschmelzenden Metall
in der Schicht
Wenn
andererseits die Deckschicht
Ferner
bauen sich während
des Ausheizens und der Bildung des Kobaltmonosilizids Korngrenzen auf,
in denen sich Titan ansammeln kann, wenn eine Titandeckschicht
Schließlich werden
die Deckschicht
Wie
in
Die
Patentschrift
Die
Patentschrift
Folglich gibt es, obwohl der konventionelle Prozessablauf eine deutliche Verbesserung des Gesamtwiderstandes eines Silizium enthaltenden leitenden Gebiets durch Herstellung von Silizidbereichen in diesen Gebieten erlaubt, dennoch Raum für Verbesserungen hinsichtlich der Qualität des silizidierten Bereichs und hinsichtlich der Prozessoptimierung.consequently There is, although the conventional process flow a clear Improvement of the total resistance of a silicon-containing conductive area by making Silizidbereichen in these Areas allowed, yet room for Improvements in the quality of the silicided area and in terms of process optimization.
Im Allgemeinen richtet sich die vorliegende Erfindung an ein Verfahren zur Herstellung eines silizidierten Bereichs in einem Silizium enthaltenden leitenden Gebiet, wobei ein Stapel aus Schichten vorgesehen ist, in dem eine oder mehrere Metallschichten das Metall zur Bildung des Metallsilizidbereichs tiefem, während andere Schichten in dem Stapel vorgesehen sind, um die darunter liegende Metallschicht während der Ingangsetzung einer chemischen Reaktion zwischen dem Metall und dem Silizium zu schützen. Ferner kann gemäß einem Aspekt das komplexe Abscheideverfahren, das zwei separate Abscheidekammern erfordert, deutlich vereinfacht werden, indem ein In-Situ-Verfahren zur Herstellung des Schichtstapels bereitgestellt wird, wodurch das Abscheiden der Metallschicht und der schützenden Schichten in einer einzelnen Abscheidekammer möglich ist.in the In general, the present invention is directed to a method for producing a silicided area in a silicon-containing area conductive area, where a stack of layers is provided, in which one or more metal layers form the metal of the metal silicide region deep, while other layers in the Stacks are provided to the underlying metal layer during the Initiation of a chemical reaction between the metal and to protect the silicon. Furthermore, according to a Aspect the complex separation process, the two separate separation chambers requires significantly simplified by an in situ procedure is provided for producing the layer stack, whereby the deposition of the metal layer and the protective layers in one individual deposition chamber possible is.
Gemäß einer anschaulichen Ausführungsform der vorliegenden Erfindung umfasst ein Verfahren zur Herstellung von Gebieten mit reduziertem Widerstand in einem Silizium enthaltenden leitenden Gebiet das Bereitstellen eines Substrats mit dem darauf gebildeten Silizium enthaltenden leitenden Gebiet und das Abscheiden eines Schichtstapels auf dem Silizium enthaltenden leitenden Gebiet, wobei der Schichtstapel eine erste und eine zweite Metallschicht, die als eine Opferschicht dient und eine Metallstickstoffverbindungsschicht aufweist, die zwischen der ersten und der zweiten Metallschicht angeordnet ist, wobei zumindest das Abscheiden der zweiten Metallschicht und der Metallstickstoffverbindungsschicht in-situ unter Verwendung des gleichen Metalls und unter Bildung eines graduellen Überganges zwischen der zweiten Metallschicht und der Metallstickstoffverbindungsschicht ausgeführt wird. Ferner umfasst das Verfahren das Wärmebehandeln des Substrats, um einen Metallsilizidbereich in dem Silizium enthaltenden leitenden Gebiet zu bilden, und das ganzflächige Entfernen der Opferschicht.According to one illustrative embodiment The present invention comprises a process for the preparation of areas of reduced resistance in a silicon containing conductive area providing a substrate with the on formed silicon-containing conductive region and the deposition a layer stack on the silicon-containing conductive region, wherein the layer stack comprises a first and a second metal layer, serving as a sacrificial layer and a metal nitrogen compound layer having, between the first and the second metal layer is arranged, wherein at least the deposition of the second metal layer and the metal nitrogen compound layer in situ using of the same metal and forming a gradual transition between the second metal layer and the metal nitrogen compound layer accomplished becomes. Furthermore, the method comprises heat treating the substrate, around a metal silicide region in the silicon-containing conductive Area to form, and the whole area Removing the sacrificial layer.
Weitere Vorteile, Aufgaben und Ausführungsformen der vorliegenden Erfindung sind in den angefügten Patentansprüchen definiert und gehen deutlicher aus der folgenden detaillierten Beschreibung hervor, wenn diese mit Bezug zu den begleitenden Zeichnungen studiert wird; es zeigen:Further Advantages, tasks and embodiments The present invention is defined in the appended claims and go more clearly from the following detailed description when studying with reference to the accompanying drawings becomes; show it:
Anzumerken
ist, dass die
Obwohl die vorliegende Erfindung mit Bezug zu den Ausführungsformen beschrieben ist, wie sie in der folgenden detaillierten Beschreibung sowie in den Zeichnungen dargestellt sind, beabsichtigen die detaillierte Beschreibung und die Zeichnungen nicht, die vorliegende Erfindung auf die speziellen offenbarten Ausführungsformen einzuschränken, sondern die beschriebenen Ausführungsformen stellen lediglich beispielhaft die diversen Aspekte der vorliegenden Erfindung dar, deren Schutzbereich durch die angefügten Patentansprüche definiert ist.Even though the present invention is described with reference to the embodiments, as in the following detailed description as well as in the following Drawings are intended to provide a detailed description and the drawings do not, the present invention to the specific disclosed embodiments restrict but the described embodiments merely exemplify the various aspects of the present invention whose scope is defined by the appended claims is.
Im Folgenden werden anschauliche Ausführungsformen der vorliegenden Erfindung im Hinblick auf einen Feldeffekttransistor mit Silizium enthaltenden leitenden Gebieten beschrieben. Es sollte jedoch selbstverständlich sein, dass die vorliegende Erfindung auf ein beliebiges Silizium enthaltendes leitendes Gebiet, das in einer integrierten Schaltung vorgesehen ist, anwendbar ist. Beispielsweise können gewisse Chipflächen oder einzelne Halbleiterelemente durch Polysiliziumleitungen verbunden sein, die entsprechend zu den Entwurfserfordernissen eine relativ geringe Querschnittsfläche aufweisen können, so dass eine Verbesserung der Leitfähigkeit dieser Leitungen deutlich zu einer Verbesserung der Gesamtleistungsfähigkeit der integrierten Schaltung beiträgt.in the The following are illustrative embodiments of the present invention Invention with regard to a field effect transistor with silicon containing conductive areas described. It should, of course, be that the present invention to any silicon-containing conductive area, which is provided in an integrated circuit is, is applicable. For example, certain chip areas or individual semiconductor elements connected by polysilicon lines be a relative to the design requirements a relative small cross-sectional area can have so that an improvement in the conductivity of these lines significantly to improve the overall performance of the integrated circuit contributes.
Der
Prozessablauf zur Herstellung des Halbleiterelements
Ferner
umfasst das in
In
einer speziellen Ausführungsform
umfassen die erste Metallschicht
Vorzugsweise
werden bei der Herstellung integrierter Schaltungen mit äußerst hoher
Packungsdichte auf Substrate mit großem Durchmesser Metallschichten
durch physikalische Dampfabscheidung abgeschieden, etwa der Sputterabscheidung,
aufgrund des relativ hohen Grades an Gleichförmigkeit, der über die
gesamte Substratoberfläche
hinweg erreicht werden kann. Während
der Sputterabscheidung wird das Substrat, etwa das Substrat
Nachdem
die erste Metallschicht
Ferner
wird Stickstoff, der in dem Abscheidematerial eingefangen ist, oder
ein beliebiges Metallnitrid, das auf dem Abscheidematerial und an
den Kammerwänden
abgeschieden wird, während
des Abscheidevorgangs ohne Stickstoffzufuhr entfernt, so dass die
Kontamination mit Metallnitrid in einem anschließenden Sputterabscheideprozess
minimal ist. Der Abscheideprozess für die zweite Metallschicht
Gemäß einer
weiteren anschaulichen Ausführungsform
kann die erste Metallschicht
Als
ein nächster
Prozessschritt wird eine Wärmebehandlung
ausgeführt,
um eine chemische Reaktion zwischen dem Silizium in dem Silizium
enthaltenden leitenden Gebiet
Anschließend werden
die Metallstickstoffverbindungsschicht
Anschließend wird
eine weitere Wärmebehandlung,
etwa ein zweiter Ausheizschritt, bei einer höheren Durchschnittstemperatur
als die erste Wärmebehandlung
durchgeführt,
um die Metallsiliziumverbindung in ein Metallsilizid überzuführen, das
einen deutlich geringeren Widerstand als das Silizium in dem Gebiet
Obwohl
die bisher beschriebenen anschaulichen Ausführungsformen sich auf einen
Schichtstapel
Anzumerken
ist, dass in anderen Ausführungsformen
mehr als drei Schichten in dem Schichtstapel
In anderen Ausführungsformen soll, insbesondere wenn eine In-Situ-Abscheidung für zwei oder drei Schichten verwendet wird, der Begriff Schicht eine Schicht beschreiben, die im Wesentlichen durch ihre Funktion anstatt durch ihre Grenze zu einer darüber liegenden oder darunter liegenden Schicht definiert ist. Beispielsweise soll eine Metallnitridschicht, die durch Sputterabscheiden mit Zufuhr von Stickstoff abgeschieden wird, und eine Schicht, die nach Erreichen einer gewissen Dicke des Metallnitrids durch Unterbrechen der Stickstoffzufuhr gebildet wird, als zumindest zwei Schichten aufgrund der Getter-Funktion der schließlich gebildeten Schicht und der Inert-Wirkung der vorhergehenden Schicht aufgefasst werden, obwohl eine deutliche physikalische Grenze dazwischen nur schwierig zu definieren ist.In other embodiments, particularly when in-situ deposition is used for two or three layers, the term layer is intended to describe a layer which is essentially defined by its function rather than by its boundary to an overlying or underlying layer. For example, a metal nitride layer deposited by sputter depositing with nitrogen supply and a layer formed after reaching a certain thickness of the metal nitride by interrupting the supply of nitrogen should be at least two layers due to the Gettering function of the final layer formed and the inerting effect of the previous layer, although a distinct physical boundary between them is difficult to define.
Weitere Modifikationen und Variationen der vorliegenden Erfindung werden für den Fachmann auf diesem Gebiet angesichts dieser Beschreibung offenkundig. Daher ist diese Beschreibung als lediglich anschaulich gedacht und dient dem Zwecke, den Fachmann die allgemeine Art des Ausführens der vorliegenden Erfindung nahe zu bringen. Selbstverständlich sind die hierin gezeigten und beschriebenen Formen der Erfindung als die gegenwärtig bevorzugten Ausführungsformen aufzufassen.Further Modifications and variations of the present invention will become for the One skilled in the art will be apparent in light of this description. Therefore, this description is intended to be illustrative only and For the purpose of serving the purpose, one skilled in the art will be aware of the general way of carrying out the present invention To bring the invention. Of course, those shown herein are and described forms of the invention as the presently preferred embodiments specific.
Claims (15)
Priority Applications (9)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10214065A DE10214065B4 (en) | 2002-03-28 | 2002-03-28 | A method of making an improved metal silicide region in a silicon-containing conductive region in an integrated circuit |
US10/282,665 US20030186523A1 (en) | 2002-03-28 | 2002-10-29 | Method for forming an improved metal silicide portion in a silicon-containing conductive region in an integrated circuit |
CNB028286146A CN100380625C (en) | 2002-03-28 | 2002-12-20 | Method for forming an improved metal silicide portion in a silicon-containing conductive region in an integrated circuit |
EP02787066A EP1490901A1 (en) | 2002-03-28 | 2002-12-20 | Method for forming an improved metal silicide contact to a silicon-containing conductive region |
PCT/US2002/040806 WO2003083936A1 (en) | 2002-03-28 | 2002-12-20 | Method for forming an improved metal silicide contact to a silicon-containing conductive region |
AU2002351407A AU2002351407A1 (en) | 2002-03-28 | 2002-12-20 | Method for forming an improved metal silicide contact to a silicon-containing conductive region |
KR10-2004-7014933A KR20040104533A (en) | 2002-03-28 | 2002-12-20 | Method for forming an improved metal silicide contact to a silicon-containing conductive region |
JP2003581256A JP2005522035A (en) | 2002-03-28 | 2002-12-20 | Method for forming an improved metal silicide contact to a conductive silicon-containing region |
TW92105990A TWI263266B (en) | 2002-03-28 | 2003-03-19 | Method for forming an improved metal silicide portion in a silicon-containing conductive region in an integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10214065A DE10214065B4 (en) | 2002-03-28 | 2002-03-28 | A method of making an improved metal silicide region in a silicon-containing conductive region in an integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
DE10214065A1 DE10214065A1 (en) | 2003-10-23 |
DE10214065B4 true DE10214065B4 (en) | 2006-07-06 |
Family
ID=28050962
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10214065A Expired - Fee Related DE10214065B4 (en) | 2002-03-28 | 2002-03-28 | A method of making an improved metal silicide region in a silicon-containing conductive region in an integrated circuit |
Country Status (3)
Country | Link |
---|---|
US (1) | US20030186523A1 (en) |
KR (1) | KR20040104533A (en) |
DE (1) | DE10214065B4 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100529675B1 (en) * | 2003-12-31 | 2005-11-17 | 동부아남반도체 주식회사 | Manufacturing process for semiconductor device |
DE102006019836B4 (en) * | 2006-04-28 | 2016-09-01 | Globalfoundries Inc. | A method of reducing silicide defects by removing contaminants prior to drain / source activation |
US8980382B2 (en) | 2009-12-02 | 2015-03-17 | Applied Materials, Inc. | Oxygen-doping for non-carbon radical-component CVD films |
US9285168B2 (en) | 2010-10-05 | 2016-03-15 | Applied Materials, Inc. | Module for ozone cure and post-cure moisture treatment |
US10283321B2 (en) | 2011-01-18 | 2019-05-07 | Applied Materials, Inc. | Semiconductor processing system and methods using capacitively coupled plasma |
US9404178B2 (en) | 2011-07-15 | 2016-08-02 | Applied Materials, Inc. | Surface treatment and deposition for reduced outgassing |
US8889566B2 (en) | 2012-09-11 | 2014-11-18 | Applied Materials, Inc. | Low cost flowable dielectric films |
US9018108B2 (en) | 2013-01-25 | 2015-04-28 | Applied Materials, Inc. | Low shrinkage dielectric films |
US9412581B2 (en) | 2014-07-16 | 2016-08-09 | Applied Materials, Inc. | Low-K dielectric gapfill by flowable deposition |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5451545A (en) * | 1992-12-23 | 1995-09-19 | Advanced Micro Devices, Inc. | Process for forming stable local interconnect/active area silicide structure VLSI applications |
US5874342A (en) * | 1997-07-09 | 1999-02-23 | Lsi Logic Corporation | Process for forming MOS device in integrated circuit structure using cobalt silicide contacts as implantation media |
Family Cites Families (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5766997A (en) * | 1909-11-30 | 1998-06-16 | Nkk Corporation | Method of forming floating gate type non-volatile semiconductor memory device having silicided source and drain regions |
US3912559A (en) * | 1971-11-25 | 1975-10-14 | Suwa Seikosha Kk | Complementary MIS-type semiconductor devices and methods for manufacturing same |
US4107835A (en) * | 1977-02-11 | 1978-08-22 | Bell Telephone Laboratories, Incorporated | Fabrication of semiconductive devices |
KR920002350B1 (en) * | 1987-05-21 | 1992-03-21 | 마쯔시다덴기산교 가부시기가이샤 | Method of manufacturing semiconductor |
US5248892A (en) * | 1989-03-13 | 1993-09-28 | U.S. Philips Corporation | Semiconductor device provided with a protection circuit |
US5034348A (en) * | 1990-08-16 | 1991-07-23 | International Business Machines Corp. | Process for forming refractory metal silicide layers of different thicknesses in an integrated circuit |
JP3285934B2 (en) * | 1991-07-16 | 2002-05-27 | 株式会社東芝 | Method for manufacturing semiconductor device |
US5240880A (en) * | 1992-05-05 | 1993-08-31 | Zilog, Inc. | Ti/TiN/Ti contact metallization |
US5352631A (en) * | 1992-12-16 | 1994-10-04 | Motorola, Inc. | Method for forming a transistor having silicided regions |
JPH07135317A (en) * | 1993-04-22 | 1995-05-23 | Texas Instr Inc <Ti> | Self-aligned silicide gate |
JPH08107087A (en) * | 1994-10-06 | 1996-04-23 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
JPH08186085A (en) * | 1994-12-28 | 1996-07-16 | Nec Corp | Manufacture of semiconductor device |
US5738917A (en) * | 1995-02-24 | 1998-04-14 | Advanced Micro Devices, Inc. | Process for in-situ deposition of a Ti/TiN/Ti aluminum underlayer |
US5962923A (en) * | 1995-08-07 | 1999-10-05 | Applied Materials, Inc. | Semiconductor device having a low thermal budget metal filling and planarization of contacts, vias and trenches |
JP2874626B2 (en) * | 1996-01-23 | 1999-03-24 | 日本電気株式会社 | Method for manufacturing semiconductor device |
US6297135B1 (en) * | 1997-01-29 | 2001-10-02 | Ultratech Stepper, Inc. | Method for forming silicide regions on an integrated device |
US5902129A (en) * | 1997-04-07 | 1999-05-11 | Lsi Logic Corporation | Process for forming improved cobalt silicide layer on integrated circuit structure using two capping layers |
US5851891A (en) * | 1997-04-21 | 1998-12-22 | Advanced Micro Devices, Inc. | IGFET method of forming with silicide contact on ultra-thin gate |
JP2980057B2 (en) * | 1997-04-30 | 1999-11-22 | 日本電気株式会社 | Method for manufacturing semiconductor device |
US6156630A (en) * | 1997-08-22 | 2000-12-05 | Micron Technology, Inc. | Titanium boride gate electrode and interconnect and methods regarding same |
US6020242A (en) * | 1997-09-04 | 2000-02-01 | Lsi Logic Corporation | Effective silicide blocking |
US5937325A (en) * | 1997-11-07 | 1999-08-10 | Advanced Micro Devices, Inc. | Formation of low resistivity titanium silicide gates in semiconductor integrated circuits |
US5998252A (en) * | 1997-12-29 | 1999-12-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of salicide and sac (self-aligned contact) integration |
KR100257075B1 (en) * | 1998-01-13 | 2000-05-15 | 김영환 | Semiconductor device and method for manufacturing the same |
US6072222A (en) * | 1998-05-18 | 2000-06-06 | Advanced Micro Devices, Inc. | Silicon implantation into selective areas of a refractory metal to reduce consumption of silicon-based junctions during salicide formation |
US6100173A (en) * | 1998-07-15 | 2000-08-08 | Advanced Micro Devices, Inc. | Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process |
US6204103B1 (en) * | 1998-09-18 | 2001-03-20 | Intel Corporation | Process to make complementary silicide metal gates for CMOS technology |
US6136705A (en) * | 1998-10-22 | 2000-10-24 | National Semiconductor Corporation | Self-aligned dual thickness cobalt silicide layer formation process |
US6133130A (en) * | 1998-10-28 | 2000-10-17 | United Microelectronics Corp. | Method for fabricating an embedded dynamic random access memory using self-aligned silicide technology |
US6040606A (en) * | 1998-11-04 | 2000-03-21 | National Semiconductor Corporation | Integrated circuit structure with dual thickness cobalt silicide layers and method for its manufacture |
US6238986B1 (en) * | 1998-11-06 | 2001-05-29 | Advanced Micro Devices, Inc. | Formation of junctions by diffusion from a doped film at silicidation |
US5970370A (en) * | 1998-12-08 | 1999-10-19 | Advanced Micro Devices | Manufacturing capping layer for the fabrication of cobalt salicide structures |
US6759315B1 (en) * | 1999-01-04 | 2004-07-06 | International Business Machines Corporation | Method for selective trimming of gate structures and apparatus formed thereby |
TW428231B (en) * | 1999-01-16 | 2001-04-01 | United Microelectronics Corp | Manufacturing method of self-aligned silicide |
JP3235583B2 (en) * | 1999-01-19 | 2001-12-04 | 日本電気株式会社 | Method for manufacturing semiconductor device |
JP3394927B2 (en) * | 1999-06-29 | 2003-04-07 | 沖電気工業株式会社 | Method for forming metal silicide layer |
US6187617B1 (en) * | 1999-07-29 | 2001-02-13 | International Business Machines Corporation | Semiconductor structure having heterogeneous silicide regions and method for forming same |
US6383906B1 (en) * | 1999-08-19 | 2002-05-07 | Advanced Micro Devices, Inc. | Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption |
US6281067B1 (en) * | 1999-11-12 | 2001-08-28 | United Microelectronics Corp. | Self-aligned silicide process for forming silicide layer over word lines in DRAM and transistors in logic circuit region |
KR20010066122A (en) * | 1999-12-31 | 2001-07-11 | 박종섭 | Method for forming polycide dual gate of semiconductor device |
US6268255B1 (en) * | 2000-01-06 | 2001-07-31 | Advanced Micro Devices, Inc. | Method of forming a semiconductor device with metal silicide regions |
TW497120B (en) * | 2000-03-06 | 2002-08-01 | Toshiba Corp | Transistor, semiconductor device and manufacturing method of semiconductor device |
US6451679B1 (en) * | 2000-04-03 | 2002-09-17 | Taiwan Semiconductor Manufacturing Company | Ion mixing between two-step titanium deposition process for titanium salicide CMOS technology |
US6268257B1 (en) * | 2000-04-25 | 2001-07-31 | Advanced Micro Devices, Inc. | Method of forming a transistor having a low-resistance gate electrode |
US6306698B1 (en) * | 2000-04-25 | 2001-10-23 | Advanced Micro Devices, Inc. | Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same |
US6238984B1 (en) * | 2000-05-05 | 2001-05-29 | United Microelectronics Corp. | Integrating high voltage and low voltage device with silicide block mask |
US6261898B1 (en) * | 2000-09-01 | 2001-07-17 | United Microelectronics Corp. | Method for fabricating a salicide gate |
KR100360410B1 (en) * | 2000-11-14 | 2002-11-13 | 삼성전자 주식회사 | Method for MDL semiconductor device including DRAM device having self-aligned contact structure and logic device having dual gate structure |
US6403423B1 (en) * | 2000-11-15 | 2002-06-11 | International Business Machines Corporation | Modified gate processing for optimized definition of array and logic devices on same chip |
TW480663B (en) * | 2001-02-15 | 2002-03-21 | Winbond Electronics Corp | Method for combining self-aligned contact processing and salicide processing |
US6528422B1 (en) * | 2001-03-16 | 2003-03-04 | Taiwan Semiconductor Manufacturing Company | Method to modify 0.25μm 1T-RAM by extra resist protect oxide (RPO) blocking |
US6468904B1 (en) * | 2001-06-18 | 2002-10-22 | Taiwan Semiconductor Manufacturing Company | RPO process for selective CoSix formation |
KR20030002867A (en) * | 2001-06-30 | 2003-01-09 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
US6534402B1 (en) * | 2001-11-01 | 2003-03-18 | Winbond Electronics Corp. | Method of fabricating self-aligned silicide |
-
2002
- 2002-03-28 DE DE10214065A patent/DE10214065B4/en not_active Expired - Fee Related
- 2002-10-29 US US10/282,665 patent/US20030186523A1/en not_active Abandoned
- 2002-12-20 KR KR10-2004-7014933A patent/KR20040104533A/en not_active Application Discontinuation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5451545A (en) * | 1992-12-23 | 1995-09-19 | Advanced Micro Devices, Inc. | Process for forming stable local interconnect/active area silicide structure VLSI applications |
US5874342A (en) * | 1997-07-09 | 1999-02-23 | Lsi Logic Corporation | Process for forming MOS device in integrated circuit structure using cobalt silicide contacts as implantation media |
Also Published As
Publication number | Publication date |
---|---|
KR20040104533A (en) | 2004-12-10 |
US20030186523A1 (en) | 2003-10-02 |
DE10214065A1 (en) | 2003-10-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE4342047B4 (en) | Semiconductor component with a diffusion barrier layer arrangement and method for its production | |
DE10245607B4 (en) | A method of forming circuit elements having nickel silicide regions thermally stabilized by a barrier diffusion material and methods of making a nickel monosilicide layer | |
DE69029595T2 (en) | Semiconductor devices with a tungsten contact and its manufacturing process | |
DE102008007001B4 (en) | Increasing the resistance to electromigration in a connection structure of a semiconductor device by forming an alloy | |
DE69427959T2 (en) | Integrated circuit with improved contact barrier | |
DE102007052050B4 (en) | A semiconductor device and method for increasing the etch selectivity during patterning a contact structure of the semiconductor device | |
DE102010064288B4 (en) | Semiconductor device having contact elements with silicided sidewall regions | |
DE102005057075B4 (en) | Semiconductor device having a copper alloy as a barrier layer in a Kupfermetallisierungsschicht and method for its preparation | |
DE102005052052B4 (en) | Electrodeposition layer for metallization layer with improved adhesion, etch selectivity and density and method for producing a dielectric layer stack | |
DE10335101B4 (en) | A method of making a polysilicon line having a metal silicide region that enables linewidth reduction | |
DE3311635A1 (en) | SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF | |
DE102005030584B4 (en) | A process for producing nickel silicide by depositing nickel from a gaseous precursor material | |
DE102008054075B4 (en) | Semiconductor device having a lowered drain and source region in conjunction with a method of complex silicide fabrication in transistors | |
DE102005052001B4 (en) | A semiconductor device having a copper-based contact plug and a method for producing the same | |
DE102010002411B4 (en) | Method for producing contact bars with reduced marginal zone capacity in a semiconductor device | |
DE10208904B4 (en) | Method for producing different silicide areas on different silicon-containing areas in a semiconductor element | |
DE10214065B4 (en) | A method of making an improved metal silicide region in a silicon-containing conductive region in an integrated circuit | |
DE19615692A1 (en) | Semiconductor device containing an element separation film with a flat upper surface and manufacturing method thereof | |
DE10056866C2 (en) | Process for forming an etch stop layer during the manufacture of a semiconductor device | |
DE10208728B4 (en) | A method for producing a semiconductor element having different metal silicide regions | |
DE102009055433B4 (en) | Contact elements of semiconductor devices, which are made on the basis of a partially applied activation layer, and corresponding manufacturing methods | |
DE10345374A1 (en) | Semiconductor device having a nickel / cobalt silicide region formed in a silicon region | |
DE60037337T2 (en) | MANUFACTURE OF A TUNGSTEN GATE ELECTRODE | |
DE102010028458A1 (en) | Semiconductor device having contact elements and Metallsilizidgebieten, which are made in a common process sequence | |
DE10250899B4 (en) | A method of removing sidewall spacers of a semiconductor device using an improved etch process |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: GLOBALFOUNDRIES INC., GRAND CAYMAN, KY |
|
8328 | Change in the person/name/address of the agent |
Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER, |
|
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |
Effective date: 20121002 |