Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
  • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
  • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
  • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
  • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components

Definitions

• the invention relates to a method for masking a recess in a structure, in particular a semiconductor structure, with a large aspect ratio.
• Photoresists are usually used for the selection of areas, which are applied to a semiconductor wafer, are then chemically changed by means of structured exposure in selected areas, so that the photoresist layer in the selected areas can be removed from the non-selected areas.
• the surface of the semiconductor wafer in the selected areas is thus used for further processes, such as the application of a layer or ionization of the selected area is exposed.
• the known method has the disadvantage that an adjustment of an exposure mask is required for the exposure of the photoresist in the selected areas. This is particularly the case with small dimensions, e.g. relatively complex to manufacture a dynamic semiconductor memory.
• the object of the invention is to provide a method for masking a recess of a structure with a large aspect ratio, which is self-adjusting.
• Cavitation is used for the selective selection of the recess with the large aspect ratio.
• the geometric shape of the structure is thus used directly, so that a special adjustment of a mask is not necessary.
• the method according to the invention is thus simple to carry out.
• An isotropic etching method is preferably used as the etching method.
• a further improvement of the method is achieved in that a sacrificial layer is applied to the surface of the structure.
• the aspect ratio of the structure is additionally increased by the sacrificial layer. This allows structures to be masked whose natural aspect ratio does not allow selection. The scope of the method according to the invention is thus expanded.
• a filling layer is preferably removed up to a predetermined distance from the surface of the structure. This ensures that areas that lie outside the selected area are not affected by a subsequent etching process. This means that the filler layer in the areas not selected is not etched below the height of the structures.
• the defined distance is preferably greater than twice the maximum thickness of the filling material, which is formed between a cavity and an adjacent structure. This ensures that the filling material is completely removed in the selected recess during the subsequent etching process and which does not affect the filler material in unselected areas.
• the invention can be used in a variety of structures. However, a preferred area of application is the use in semiconductor structures, in particular in structures which are formed from a silicon material.
• a silicon oxide layer is preferably applied as filler material and is deposited using a TEOS process.
• the use of the TEOS process enables the safe formation of voids between structures that exceed a specified aspect ratio.
• Silicon oxide is preferably deposited as the sacrificial layer.
• the use of silicon oxide has the advantage that silicon oxide is easy to deposit and can be reliably and selectively removed after the deposition.
• FIG. 1 shows a schematic representation of structures with a large and a small aspect ratio
• FIG. 2 shows a filled structure with cavities
• FIG. 3 shows an arrangement for depositing a filling layer
• FIG. 4 shows a structure with a cavity and a partially removed filling layer
• FIG. 5 shows a mask for selected areas and FIG. 6 shows a structure with a sacrificial layer.
• FIG. 1 schematically shows a partial section of a structure that has been worked out of a silicon wafer 3, for example.
• the structure has a first area with webs 4 and first recesses 1, which have a large aspect ratio.
• the structure has a second area with webs 4 and a second recess 2, which have a small aspect ratio.
• the aspect ratio is determined by the width W in relation to the depth T of the recess.
• the structure has four webs 4 of the same height, but the distance between a first and a second web 4a, 4b and between the second and a third web 4b, 4c is of the same size and smaller than between the third web 4c and a fourth web 4d.
• first recesses 1 are designed with a large aspect ratio and second recesses 2 with a small aspect ratio.
• the webs 4 are formed from a silicon wafer 3, for example using an etching process. Furthermore, it is also possible for both the webs 4 and a plate from which the webs 4 protrude to be formed from different materials. For example, the webs 4 can also be formed from a different material on a silicon wafer. For example, the webs 4 can be made from silicon oxide or silicon nitride, but also from a metallic alloy.
• FIG. 2 shows the silicon wafer 3 after the deposition of a filling layer 5, which in the exemplary embodiment shown is represented by a silicon oxide that was deposited in a TEOS process.
• a silicon oxide that was deposited in a TEOS process.
• any other type of material can be deposited, which causes a void formation when a certain aspect ratio is exceeded and can be removed again in a subsequent process.
• the deposition process is defined in such a way that cavities 6 form in the first recesses 1, which have a large aspect ratio. In the illustrated embodiment, a cavity 6 is formed in each first recess 1.
• the deposition process can also be used in such a way that a plurality of cavities 6 are formed in a first recess 1. It is important that no cavity is formed in the second recess 2, which has a smaller aspect ratio.
• the formation of cavities 6 depends on the aspect ratio of the filled structure.
• the filler material used and the one used is represented by a silicon oxide that was deposited in a TEOS process
• Deposition processes are to be adapted to the existing aspect ratios of the structure in such a way that cavities 6 are created in the desired recesses 1.
• the TEOS method used has the advantage that the edge structure of the present structure, onto which the TEOS material is deposited, also simulates the edge structure to a certain extent. In this way, cavities 6 are formed in structures with a large aspect ratio that is above a specified value.
• the specified value depends on the deposition method used.
• FIG. 3 shows a schematic illustration of a device for depositing a layer in a TEOS process.
• An organic liquid serves as the silicon source for the deposition.
• the oxide formed from the vapor of the liquid has a high electrical stability in addition to the conformal step covering.
• silicon oxide is deposited using the following formula:
• FIG. 3 schematically shows a quartz tube in which a large number of silicon wafers 3 are arranged.
• the quartz tube is connected via a line to a gas space which is formed via a liquid gas source 7.
• the liquid gas source 7 is kept at a fixed temperature by a heating source 8.
• both the liquid gas and the quartz tube are supplied with nitrogen oxide.
• the quartz tube is connected to a vacuum pump system 10 via a vacuum valve 9. The vacuum pump system ensures a fixed pressure in the quartz tube.
• the quartz tube is surrounded by a three-zone furnace 11, which is also used for a fixed temperature
• Quartz tube ensures.
• the deposition of TEOS silicon is a known method, so that details are not discussed here.
• the TEOS process is described, for example, in “silicon semiconductor technology” Hilleringmann, Teubner, 1999, ISBN 3-519-10149-1 in chapter 7.1.2.2 “Low Pressure CVD process”.
• An essential feature of the deposition method used is that the cavities 6 extend to an area that lies above the upper edge of the webs 4.
• the filler layer 5 is to be removed planarly into the region of the cavities 6.
• the filling layer 5 is preferably removed until the cavities 6 are open. Depending on the form of application, however, it can be advantageous to leave a certain residual thickness above the cavities 6.
• the filling layer 5 is removed in the planar removal process, for example by a chemical, mechanical polishing process.
• the filler layer 5 is preferably removed up to a distance ⁇ with respect to the upper edge of the webs 4.
• the distance is preferably selected in such a way that is greater than or equal to twice the maximum distance ⁇ between a cavity boundary and the surrounding structure.
• FIG. 3 shows the distance ⁇ between a surface of a cavity 6 and a corner region between a web 4 and the plate of the silicon wafer 3. The choice of the specified distance ensures that the filling material 5 is completely removed from the first recesses 1 in a subsequent etching process without the webs 4, which delimit the second recess 2, being undercut on the side.
• the filling layer 5 is etched off by an etching process, preferably an anisotropic etching process.
• the etching solution used e.g. Alkaline lye or dry etching methods such as plasma etching in the area of the cavities 6 and etches the filling layer 5 out of the first recesses 1.
• the etching solution also acts on the top of the filling layer 5 in the region of the second recess 2. Due to the selected distance, however, only the surface of the filling layer 5 is etched off. The distance was chosen in such a way that the webs in the area of the second recesses 2 are not under-etched. The etching process is stopped when the filler layer 5 is removed from the first recess 1.
• the surfaces which are arranged in the first recesses 1 have been exposed. Areas of other recesses, such as the second recess 2, are still covered by the filler layer 5.
• the filling layer 5 thus forms a mask for unselected areas of the semiconductor wafer 3.
• the exposed areas, in this case the first recesses 1, can be used in the following method, for example for an implantation, for further etching, for a selective growth of a material, such as silicon, silicon oxide or silicon nitride.
• the mask is adjusted on the basis of the use of the geometry of the structure and the formation of cavities in the deposition method used, without an adjustment being necessary.
• FIG. 6 shows a further development of the method according to the invention, in which a sacrificial layer 12 having a predetermined thickness ⁇ is applied to the webs 4.
• the sacrificial layer 12 can be designed, for example, in the form of silicon oxide or silicon nitride. Only after the sacrificial layer 12 has been applied is the structure filled with the filling layer 5.
• the sacrificial layer 12 offers the advantage that the height of the webs 4 is increased and the aspect ratio is therefore greater.
• the aspect ratio can thus be set in such a way that the cavity formation for cavities 6 takes place in the desired manner in the first recesses 1.
• the other methods such as removing the filler layer 5 and removing the filler layer 5, are used in accordance with the previously described method.
• FIG. 6 shows the structure with the sacrificial layer 12, in which the filling layer 5 has already been removed down to the cavities 6.
• the filler layer 5 can preferably be removed down to the top of the sacrificial layer 12. This makes it easy to guide the removal process, since the depth of removal of the filler layer 5 is determined by the height of the sacrificial layer 12. In this application form too, there is a distance between the upper edge of the sacrificial layer 12 and an upper edge of the removed sacrificial layer 12, as shown in FIG. 6, is advantageous.
• the distance ⁇ is to be selected in the manner: ⁇ 2 2 ⁇ - ⁇ , with ⁇ the maximum distance between a cavity boundary of a cavity 6 and the structure of the silicon wafer 3 or a web 4 and Y the height of the sacrificial layer 12.
• the sacrificial layer 12 is removed again using, for example, a selective etching process.

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• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Inorganic Chemistry (AREA)
• Chemical & Material Sciences (AREA)
• Weting (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Drying Of Semiconductors (AREA)

Applications Claiming Priority (3)

Publications (1)

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Family Applications (1)

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• 2002
  • 2002-01-15 DE DE10201178A patent/DE10201178A1/de not_active Withdrawn
  • 2002-12-24 TW TW091137127A patent/TW200305969A/zh unknown
• 2003
  • 2003-01-08 KR KR1020047010873A patent/KR100620978B1/ko not_active IP Right Cessation
  • 2003-01-08 EP EP03701495A patent/EP1466351A1/de not_active Withdrawn
  • 2003-01-08 US US10/501,464 patent/US7261829B2/en not_active Expired - Fee Related
  • 2003-01-08 WO PCT/EP2003/000087 patent/WO2003060966A1/de not_active Application Discontinuation

Non-Patent Citations (1)

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