EP1437002A2 - System und verfahren zum übertragen digitaler daten - Google Patents
System und verfahren zum übertragen digitaler datenInfo
- Publication number
- EP1437002A2 EP1437002A2 EP02776771A EP02776771A EP1437002A2 EP 1437002 A2 EP1437002 A2 EP 1437002A2 EP 02776771 A EP02776771 A EP 02776771A EP 02776771 A EP02776771 A EP 02776771A EP 1437002 A2 EP1437002 A2 EP 1437002A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- evaluation unit
- satellite
- synchronization
- clk
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/20—Adaptations for transmission via a GHz frequency band, e.g. via satellite
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/18—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
- H04N7/181—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast for receiving images from a plurality of remote sources
Definitions
- the invention relates to a system for transmitting digital data with an evaluation unit, a plurality of satellite systems, which are connected to the evaluation unit for transmitting data, and a serial interface between the evaluation unit and the satellite systems.
- the invention further relates to a method for transmitting digital data from a plurality of satellite systems to an evaluation unit which is connected to the satellite systems, in which data are transmitted from the satellite systems to the evaluation unit via a serial interface.
- the invention further relates to uses of systems for transmitting digital data.
- Generic systems and generic methods are used, for example, for the transmission of digital image data.
- camera systems are provided as satellite systems, and the image data are transmitted from the individual camera systems via line connections to a central evaluation unit. It is often desirable to transmit data over a greater distance, for example over several meters.
- standards have been developed, such as LVDS ("Low Voltage Differential Signaling").
- LVDS Low Voltage Differential Signaling
- a disadvantage of such systems is that a large number of lines is required, since one pair of lines is required per channel.
- the invention builds on the generic system in that synchronization units for synchronizing Transmission clocks of the data transmissions from the satellite systems to the evaluation unit are provided such that a synchronization unit is assigned to each satellite system and that the synchronization units individually synchronize the transmission clocks of the satellite systems recorded by the evaluation unit based on a system clock of the evaluation unit.
- synchronization of the satellite systems with one another and the satellite systems with the evaluation unit is a difficult undertaking.
- synchronization would be carried out in such a way that the evaluation unit sends its clock to the satellite systems and they work with the same clock.
- the system clock of the evaluation unit must be passed on to the satellite systems over a certain cable route and via transmitter and receiver modules.
- the cable length and environmental conditions such as the temperature
- there are again phase shifts which can sometimes be of the order of a cycle period.
- the data transmitted from the satellite systems to the evaluation unit that is to say for example the image data, also experience additional phase shifts due to the transmission over the cable route.
- the result is an undetermined phase shift that can lead to system failure.
- the present invention eliminates all of these problems. It is provided that a synchronization unit is assigned to each satellite system, so that an individual synchronization of the satellite systems can take place on the basis of the system clock of the evaluation unit.
- This system differs from the mere passing on of the system clock to the satellite systems in that the transmission clocks of the satellite systems recorded by the evaluation unit are individually synchronized. So it will not only pass on a system clock to the satellite systems. Rather, on the basis of the actually individual clock synchronization of the satellite systems.
- the system is based on the invention in an advantageous manner in that the synchronization units are arranged spatially at or in the evaluation unit. In this way, the synchronization takes place in the spatial area in which the system clock is available on the one hand and where on the other hand the transmission clocks of the satellite systems detected by the evaluation unit are present. Therefore, the clock that is decisive for the construction of the parallel data is compared directly with the system clock.
- each synchronization unit receives the clock received from the evaluation unit of the satellite system assigned to it as an input signal, that each synchronization unit receives the system clock of the evaluation unit as an input signal, and that each synchronization unit receives an output signal for influencing the phase position of the transmission clock of the satellite system assigned to it.
- the output signal can provide the phase position individually for each satellite system as a function of the transmission clock detected by the evaluation unit and the system clock.
- the invention is developed in a particularly advantageous manner in that the evaluation unit for each satellite system has a transmitter, that the evaluation unit for each satellite system has a receiver, that each
- Satellite system has a receiver that is connected to a transmitter of the evaluation unit, that each satellite system has a transmitter that is connected to a receiver of the evaluation unit that transmits data to be evaluated via the connection between the transmitter of a satellite system and the assigned receiver of the evaluation unit and that about the connection between a transmitter of the Evaluation unit and the receiver of the assigned satellite system signals for synchronization of the transmission clocks of the satellite systems are sent.
- the system can transmit data from the satellite systems to the evaluation unit. Unaffected by this, the signals required for synchronization can be sent via a further connection between the evaluation unit and the satellite systems.
- each satellite system is connected to the evaluation unit via two line pairs.
- One pair of lines is provided for sending the signals required for synchronization.
- the other pair of lines is used to transfer data.
- LVDS Low Voltage Differential Signaling
- LVDS Low Voltage Differential Signaling
- the connection technology can be used as the connection technology, the number of lines being able to be reduced due to the use of a serial interface.
- the serial data can be reconstructed into parallel data without any problems due to the synchronization of the individual satellite systems with the system clock.
- control signals for influencing functions of the satellite systems are sent via the connection between a transmitter of the evaluation unit and the receiver of the assigned satellite system.
- the connections for transmitting the signals required for the synchronization can therefore be sent via the same connecting lines as control signals, for example for setting the exposure time of cameras.
- These control signals do not necessarily have to be transmitted in synchronized fashion since the data rate of the control signals is considerably lower than that of the transmitted data.
- control signals can be sent at rates of 200 kHz, while data rates between 10 MHz and 80 MHz are possible.
- the evaluation unit has a microcontroller. Such a microcontroller processes the received data, the processing taking place on the basis of a system clock. This system clock is still used for the synchronization of the satellite systems.
- the invention is developed in a particularly advantageous manner in that the synchronization units are implemented as PLL circuits (“phase locked loops”).
- PLL circuits phase locked loops
- the transmission clocks of the satellite systems can be locked to the system clock depending on the clock detected by the evaluation unit.
- An individual synchronization of the satellite systems to a common cycle can thus advantageously be carried out.
- the invention can also advantageously be developed in such a way that the evaluation unit has an FPGA ("Field Programmable Gate Array”) and that the FPGA has DLL circuits ("Delay Locked Loop”) which are used as synchronization units.
- FPGA-type circuits often include interlocking integrated circuits so that synchronization can be provided without the need for additional components using these DLL circuits.
- the invention is particularly advantageous in that the satellite systems are camera systems.
- a synchronization of the large occurring data to be transmitted is particularly useful in image data transmission.
- the present invention also has its advantages in the case when the satellite systems are sensor systems. Numerous different sensors are conceivable that deliver their information to a central evaluation unit. Whenever a synchronous detection of the If transmitted data is desired, the advantages of the present invention come into play.
- the invention builds on the generic method in that transmission clocks of the data transmissions from the satellite systems are synchronized to the evaluation unit and that the transmission clocks of the satellite systems are individually synchronized on the basis of a system clock of the evaluation unit by synchronization units.
- the advantages of the system according to the invention also come into effect in the context of a method. This also applies to the preferred embodiments of the method according to the invention described below.
- the method can advantageously be further developed in that the synchronization takes place spatially at or in the evaluation unit.
- each synchronization unit receives the clock of the satellite system assigned to it from the evaluation unit as an input signal, that each synchronization unit receives the system clock of the evaluation unit as an input signal, and that each synchronization unit receives an output signal to influence the Outputs phase of the transmission clock of the satellite system assigned to it.
- the evaluation unit has a transmitter for each satellite system, that the evaluation unit has a receiver for each satellite system, that each satellite system has a receiver that is connected to a transmitter of the evaluation unit, that each satellite system Has transmitter which is connected to a receiver of the evaluation unit, that data to be evaluated are transmitted via the connection between the transmitter of a satellite system and the assigned receiver of the evaluation unit and that signals are connected via the connection between a transmitter of the evaluation unit and the receiver of the assigned satellite system to synchronize the transmission clocks of the satellite system.
- control signals for influencing functions of the satellite systems are sent via the connection between a transmitter of the evaluation unit and the receiver of the assigned satellite system.
- PLL phase locked loop
- the evaluation unit has an FGPA ("Field Programmable Gate Array”) and that the FGPA has DLL circuits ("Delay Locked Loop”) that are used as synchronization units.
- FGPA Field Programmable Gate Array
- DLL circuits Double Locked Loop
- the method according to the invention is also advantageously developed in that in addition to the system clock the evaluation unit further clock information of the satellite systems is taken into account.
- the invention further relates to the use of a system according to the invention for monitoring blind spots in a motor vehicle. This can be accomplished, for example, by inserting a camera in each of the two exterior mirrors. The cameras are supplied with the clock and the configuration signals that are specifically adapted in their phase via an LVDS line pair. About a second
- LVDS line pairs are then transmitted, for example, 8-bit gray values.
- the invention also consists in the use of a system according to the invention for seat position detection in a motor vehicle.
- a seat position detection can likewise advantageously be carried out by two or more cameras, so that the information can advantageously be implemented by an evaluation unit.
- the invention further relates to the use of a system for lane detection according to the invention.
- image data or, for example, radar data can be evaluated.
- the invention is based on the finding that, due to the individual synchronization of the individual satellite systems with respect to the system clock of an evaluation unit, the configuration of the connected satellites is possible via a serial interface. For example, SPI or I 2 C interfaces are possible. It is possible for all satellites to deliver data to the evaluation unit synchronously with the clock of the evaluation unit, which means that expensive FIFO buffers in particular are unnecessary. It is possible to do any To connect the satellite system to the evaluation unit via two line pairs, whereby line pairs of up to 10 m in length can be used using LVDS line technology.
- Figure 1 is a schematic block diagram of a system according to the invention.
- FIG. 1 shows a schematic block diagram of a system according to the invention. This is described by way of example with the aid of such a system in which the satellite systems are camera systems, in which image data are read out serially by an evaluation unit 10 and are made available by the camera systems 12, 14.
- the first camera system 12 comprises a camera 50, an LVDS receiver 32 and an LVDS transmitter 36.
- the second camera system 14 comprises a camera 52, an LVDS receiver 34 and an LVDS transmitter 38.
- For communication with the ge - Named receivers 32, 34 and transmitters 36, 38 are in the evaluation unit 10 an LVDS transmitter 24 and an LVDS receiver 28 for communication with the first camera system 12 and an LVDS transmitter 26 and an LVDS receiver 30 for communication provided with the second camera system 14.
- An interface 16 is made available by the transmitter and receiver mentioned.
- the data transmission Datal from the first camera system 12 to the evaluation unit 10 takes place via an LVDS line pair 40.
- the data transmission Data2 from the second camera system 14 to the evaluation unit 10 takes place via a further LVDS line pair 42.
- control signal Cntrll are transmitted from the evaluation unit 10 to the first camera system 12.
- Ü Control signals Cntrl2 are sent from the evaluation unit 10 to the second camera system 14 via a further pair of LVDS lines 46.
- Line pair 44 continues to send a clock signal clk_tranl to the first camera system 12.
- a clock signal clk_tran2 is sent to the second camera system via the LVDS line pair 46.
- These clock signals clk_tranl, clk_tran2 are output signals from two synchronization units 18, 20, a first synchronization unit 18 being assigned to the first camera system 12 and a second synchronization unit 20 being assigned to the second camera system 14.
- a clock signal clk_recl detected by the evaluation unit 10 is transmitted from the receiver 28 to the synchronization unit 18.
- the synchronization unit 18 also receives the system clock 22 as a signal clk_ref.
- the synchronization unit 18 can effect a targeted phase adaptation of the clock clk_recl received by the evaluation unit 10 to the system clock clk_ref.
- the evaluation unit 10 receives a clock signal clk_rec2, which is forwarded by the receiver 30 to the synchronization unit 20.
- the synchronization unit 20 also receives the system clock clk_ref.
- the clock clk_rec2 can thus also be adapted to the system clock clk_ref by a targeted phase shift.
- the synchronization units 18, 20 are preferably implemented as PLL circuits, so that the phases of the signals detected by the evaluation unit 10 can be locked with respect to the system clock.
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Astronomy & Astrophysics (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10148878 | 2001-10-04 | ||
DE10148878A DE10148878B4 (de) | 2001-10-04 | 2001-10-04 | System und Verfahren zum Übertragen digitaler Daten |
PCT/DE2002/003739 WO2003032641A2 (de) | 2001-10-04 | 2002-10-02 | System und verfahren zum übertragen digitaler daten |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1437002A2 true EP1437002A2 (de) | 2004-07-14 |
Family
ID=7701321
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP02776771A Withdrawn EP1437002A2 (de) | 2001-10-04 | 2002-10-02 | System und verfahren zum übertragen digitaler daten |
Country Status (6)
Country | Link |
---|---|
US (1) | US20050105636A1 (ko) |
EP (1) | EP1437002A2 (ko) |
JP (1) | JP2005506006A (ko) |
KR (1) | KR100895351B1 (ko) |
DE (1) | DE10148878B4 (ko) |
WO (1) | WO2003032641A2 (ko) |
Families Citing this family (4)
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US20050046458A1 (en) * | 2003-08-28 | 2005-03-03 | Schroeder Charles G. | Digital delay elements constructed in a programmable logic device |
US7675336B1 (en) * | 2004-12-17 | 2010-03-09 | Altera Corporation | Clock duty cycle recovery circuit |
DE102012108696B4 (de) | 2012-09-17 | 2020-08-06 | Wago Verwaltungsgesellschaft Mbh | Datenbusteilnehmer und Verfahren zur Synchronisation von Datenbusteilnehmern |
JP2020167634A (ja) * | 2019-03-29 | 2020-10-08 | ソニーセミコンダクタソリューションズ株式会社 | 送信装置、受信装置、及び伝送システム |
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-
2001
- 2001-10-04 DE DE10148878A patent/DE10148878B4/de not_active Expired - Fee Related
-
2002
- 2002-10-02 US US10/491,535 patent/US20050105636A1/en not_active Abandoned
- 2002-10-02 EP EP02776771A patent/EP1437002A2/de not_active Withdrawn
- 2002-10-02 KR KR1020047004996A patent/KR100895351B1/ko not_active IP Right Cessation
- 2002-10-02 WO PCT/DE2002/003739 patent/WO2003032641A2/de active Application Filing
- 2002-10-02 JP JP2003535469A patent/JP2005506006A/ja active Pending
Non-Patent Citations (1)
Title |
---|
See references of WO03032641A2 * |
Also Published As
Publication number | Publication date |
---|---|
JP2005506006A (ja) | 2005-02-24 |
DE10148878A1 (de) | 2003-04-24 |
WO2003032641A2 (de) | 2003-04-17 |
KR20040039487A (ko) | 2004-05-10 |
WO2003032641A8 (de) | 2005-03-24 |
KR100895351B1 (ko) | 2009-04-29 |
WO2003032641A3 (de) | 2003-07-17 |
US20050105636A1 (en) | 2005-05-19 |
DE10148878B4 (de) | 2006-03-02 |
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