EP1428261A1 - Ensemble d'elements de memoire a semi-conducteurs - Google Patents

Ensemble d'elements de memoire a semi-conducteurs

Info

Publication number
EP1428261A1
EP1428261A1 EP02754443A EP02754443A EP1428261A1 EP 1428261 A1 EP1428261 A1 EP 1428261A1 EP 02754443 A EP02754443 A EP 02754443A EP 02754443 A EP02754443 A EP 02754443A EP 1428261 A1 EP1428261 A1 EP 1428261A1
Authority
EP
European Patent Office
Prior art keywords
layer
trenches
insulating layer
gate electrode
tunnel barrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02754443A
Other languages
German (de)
English (en)
Inventor
Franz Hofmann
Richard Johannes Luyken
Michael Specht
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1428261A1 publication Critical patent/EP1428261A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the invention relates to a method for producing a semiconductor memory element arrangement, a method for operating a semiconductor memory element arrangement and a semiconductor memory element arrangement.
  • Essential parameters of a semiconductor memory element arrangement are the hold time for which the memory content stored in the individual semiconductor memory elements is retained, the write time required for programming the memory content and the write voltages necessary for programming the memory content.
  • RAM Random Access Memory
  • EPROM Electrically Programmable Read Only Memory
  • the tunnel barriers are not, as usual, in the form of a rectangular potential with a constant height of the potential barrier, but are profiled by means of "peaks" or "spikes".
  • such a “crested barrier” semiconductor memory element can achieve relatively fast write times.
  • the write voltages required for writing are relatively large, since to build up the “crested barrier” structure, layer structures with nanocrystals that are distributed over a large area and are arranged at a relatively large distance of approximately 3-5 nm are required, in which the coupling between adjacent layers is relative is weak.
  • PLED Planar Localized Electron Device
  • PLED Planar Localized Electron Device
  • the PLED memory element has a write transistor and a read transistor.
  • the substrate of the write transistor is formed by the multiple tunnel barrier and the gate of the write transistor by the second word line.
  • the floating gate itself forms the gate of the read transistor.
  • a floating gate (memory node) is first selectively formed on a substrate covered by a gate insulation layer, whereupon its side walls are covered by an insulating layer.
  • a first gate electrode is formed by first applying a polysilicon layer over the entire surface. Then, photoresist is applied where the first gate electrode is to be formed and an anisotropic etching step is carried out. Since the anisotropic etching does not take place in the horizontal direction, the polysilicon also remains on the side wall of the floating gate, with which the first gate electrode is formed.
  • a multiple tunnel barrier is then formed on the structure thus obtained, and a second gate
  • the electrode is formed adjacent to the multiple tunnel barrier and in a manner corresponding to the first gate electrode by applying a polysilicon layer over the entire area, selectively applying a photoresist and anisotropically etching the polysilicon layer.
  • [3] also describes a highly integrated flash memory, each memory cell containing four vertical floating gate transistors. Two mutually orthogonal gate lines enable the control gates to be addressed. First source / drain connections can be addressed line by line by means of connecting lines which are arranged parallel to the first gate lines. Second source / drain connections can be addressed line by line by means of connecting lines which are arranged parallel to the second gate lines.
  • [4] describes a highly integrated semiconductor memory with a columnar EPROM cell with a floating gate and a control gate. The EPROM cell is completely depleted. The control gate of the EPROM cell consists of p + -doped semiconductor material.
  • [5] describes a vertical floating gate transistor with a variety of tunnel barriers.
  • [6] describes a storage device with a storage node, into which the charge is written by means of a tunnel barrier arrangement.
  • the stored charge influences the conductivity of the source / drain path.
  • the tunnel barrier arrangement has a multiplicity of tunnel barriers, the tunnel barrier arrangement alternately having a 3 nm thick polysilicon layer and a 1 nm thick silicon nitride layer.
  • the invention is therefore based on the problem of creating a method for producing a semiconductor memory element arrangement, a method for operating a semiconductor memory element arrangement and a semiconductor memory element arrangement which enable easier production while ensuring trouble-free operation.
  • a first electrically insulating layer is applied to a substrate.
  • a layer system comprising a floating gate and a tunnel barrier arrangement applied to the floating gate is applied to the first electrically insulating layer.
  • a first gate electrode is formed adjacent to the floating gate, via which electrical charge can be supplied to or removed from the floating gate.
  • a second gate electrode is formed adjacent to the tunnel barrier arrangement, via which the electrical charge transmission of the tunnel barrier arrangement can be controlled.
  • the first and the second gate electrodes are arranged in a first trench structure formed in the layer system, consisting of first trenches arranged parallel to one another and extending to the first insulating layer, and in a second trench structure formed in the layer system consisting of parallel to one another and perpendicular to the first trenches. second trenches extending to the first insulating layer.
  • the manufacturing method according to the invention is considerably simplified compared to the known method.
  • the two gate electrodes are designed as self-adjusting spacers.
  • data is written or erased by applying a positive electrical voltage to the second gate electrode and applying a negative or positive electrical voltage to the data line.
  • the positive voltage applied to the second gate electrode increases the electrical charge transmission of the tunnel barrier arrangement during the write or erase process and enables the supply or discharge of electrical charge to and from the floating gate and thus an inverting of the between and drain region in the channel located in the substrate.
  • the reading process is carried out by applying a positive voltage to the first gate electrode in order to test the threshold voltage of the reading transistor formed by the floating gate and the source or drain connection.
  • a current flow in the channel is detected or not, depending on the inverted or non-inverted state of the channel, with an electrical voltage present between the source and drain regions.
  • the electrical charge on the floating gate is reduced over the multiple tunnel barrier during of the reading process is prevented, so that the reading can take place without interference.
  • a second electrically insulating layer is applied to the tunnel barrier arrangement in order to form the first and second trench structure and structured in accordance with the first and second trench structure.
  • the structuring of the second electrically insulating layer applied to the tunnel barrier arrangement preferably has the following steps:
  • first Trench spacers are formed on the second electrically insulating layer.
  • the first trenches preferably have a smaller width than the second trenches.
  • the first and the second gate electrodes are preferably formed as spacers in the second trenches of the second trench structure.
  • the step of forming the first gate electrode in the first and second trench structure has the following steps:
  • the step of forming the second gate electrode in the first and second trench structure has the following steps:
  • the first, second, third and fourth insulating layers can be formed from silicon nitride or silicon dioxide, for example.
  • the first and second gate electrodes are preferably formed from polysilicon.
  • the tunnel barrier arrangement is preferably designed as a layer stack with an alternating layer sequence of semiconducting and insulating layers to form a multiple tunnel barrier.
  • the semiconducting layers of the layer stack are preferably formed from undoped polysilicon, whereas the insulating layers of the layer stack are preferably formed from silicon nitride or silicon dioxide.
  • the semiconducting layers of the layer stack are formed with a thickness in the range from 30 to 50 nm and the insulating layers with a thickness in the range from 2 to 4 nm.
  • the semiconducting layers of the layer stack are formed with a thickness and a grain size of at most 2 nm and the insulating layers with a thickness of at most 1.5 nm.
  • the conductive layers form very thin layers of fine-grained crystals (for example polysilicon crystals).
  • Such a thin layer of polycrystalline silicon can be regarded as a two-dimensional lattice of conductive islands which are connected to one another by very small capacitances.
  • the distances between the polysilicon nanocrystals can be easily controlled.
  • a Coulomb blockage can thus be used in a targeted manner, so that the write time of the memory cell is further shortened.
  • the semiconducting layers can also be formed from amorphous silicon.
  • Semiconductor memory element arrangement having a first insulating layer applied to a substrate and a layer system comprising a floating gate and a tunnel barrier arrangement applied to the first insulating layer, the electrical charge transmission of the tunnel barrier arrangement to the floating gate is via a second Gate electrode controlled, wherein the first and second gate electrodes in a first trench structure formed in the layer system of mutually parallel first trenches extending to the first insulating layer and in a second trench structure formed in the layer system of parallel to each other and perpendicular to are arranged in the first trenches and extend to the first insulating layer.
  • an electrical voltage is preferably applied to the first gate electrode when the second gate electrode is de-energized.
  • an electrical voltage is preferably applied to the second gate electrode when the first gate electrode is de-energized.
  • each semiconductor memory element has
  • a layer system applied to the first electrically insulating layer comprising a floating gate and a tunnel barrier arrangement applied to the floating gate;
  • a first gate electrode adjacent to the floating gate which is used to read the state of the floating gate transistor
  • a second gate electrode adjacent to the tunnel barrier arrangement, via which the charge transmission of the tunnel barrier arrangement can be controlled; wherein the first and the second gate electrodes in a first trench structure formed in the layer system of first trenches arranged parallel to one another and extending to the first insulating layer and in a second trench structure formed in the layer system made parallel to one another and perpendicular to the first trenches arranged second trenches extending to the first insulating layer.
  • FIGS. 2a-2g cross sections of the semiconductor memory element arrangement from FIG. 1 to corresponding states during their production in the cutting direction perpendicular to FIG. 1;
  • Figures 3a - 3c are schematic representations of the at
  • Figure 4 is a schematic representation of a semiconductor memory element arrangement according to the invention in plan view.
  • Figure 5 shows a programming example of the
  • FIG. 4 Semiconductor memory element arrangement from FIG. 4.
  • the method according to the invention for producing a semiconductor memory element arrangement according to a preferred exemplary embodiment is first explained with reference to Fig.la-g and Fig. 2a-g, the cross-sectional views shown in Fig.la-g and Fig. 2a-g respectively for each other vertical sectional planes are shown.
  • a layer system comprising a floating gate and a tunnel barrier arrangement applied to the floating gate is first formed on a substrate.
  • a silicon substrate 101 is covered in a first step by means of an implantation mask, whereupon one
  • Source or drain regions 102, 103 is carried out in the silicon substrate 101.
  • the implantation mask 203 used here is shown schematically in FIG. 3c and has a pattern of strip-shaped openings 203a,... 203n arranged parallel to one another, the spacing of which corresponds to the desired spacing of the source and drain regions 102, 103.
  • An electrically insulating layer 104 made of silicon dioxide with a thickness of approximately 6-10 nm is then grown on the silicon substrate.
  • Layer 105 is used for Formation of a floating gate of the semiconductor memory element arrangement 100.
  • Electrically insulating barrier layers 106, 108 and 110 are formed on layer 105 in an alternating layer sequence
  • the layer stack formed from the electrically insulating or semiconducting layers 106-110 serves to form a multiple tunnel barrier of the semiconductor memory element arrangement 100.
  • the polysilicon layers 107 and 109 have a thickness of approximately 40 nm
  • the polysilicon layer 111 has a thickness of approximately 50 nm
  • the barrier layers 106, 108 and 110 have a thickness of approximately 2 nm.
  • a second electrically insulating layer 112 made of silicon nitride is applied to the polysilicon layer 111 according to FIGS.
  • a first photolithography step using a first photomask 201, shown schematically in FIG. 3a, etches parallel to one another with a width of approximately 150 nm are etched into the second electrically insulating layer 112.
  • the photomask 201 has a multiplicity of strip-shaped openings 201a,..., 201n arranged parallel to one another, the spacing of which corresponds to the minimum structure size (e.g. 150 nm).
  • first trenches 114 with a width of approximately 50 nm are formed.
  • a second photolithography step is carried out using a second photomask 202, shown schematically in FIG. 3b.
  • the photomask 202 has a multiplicity of strip-shaped openings 202a,..., 202n arranged parallel to one another, the spacing of which corresponds to the minimum structure size (e.g. 150 nm).
  • the second photo mask is positioned perpendicular to the first photo mask. Now the silicon nitride is etched dry, so that according to FIG. 2b perpendicular to the first trenches shown in FIG. 1b, second trenches 115 are formed with a width of approximately 150 nm. The photoresist is then removed.
  • the areas of the layer structure of polysilicon layer 111, multiple tunnel barrier 106-110 and floating gate 105 that are not covered by silicon nitride are etched according to FIGS. 1c and 2c, so that a first trench structure 116 with trenches 117 parallel to one another, see. Fig.lc, and a second trench structure 118 with parallel to each other and perpendicular to the first trenches 117 arranged second trenches 119, cf. Fig.2c, are formed.
  • the first and second trenches 117, 119 each extend parallel to the stacking direction of the Layer stack 106-110 up to the electrically insulating silicon dioxide layer 104.
  • a third electrically insulating layer 120 made of silicon dioxide is then applied to the side walls of the first or second trench structure 116, 118.
  • a polysilicon layer 121 is applied to the third electrically insulating layer 120.
  • the polysilicon layer 121 has a layer thickness of approximately 50 nm, so that polysilicon spacers 122 are formed in the second trench structure 118.
  • the polysilicon layer 121 or the polysilicon spacers 122 serve to form the first gate electrode, which is used to read the state of the floating gate transistor, i.e. for determining the electrical charge carriers stored in the floating gate.
  • a fourth electrically insulating layer 123 made of silicon dioxide is applied in a next step according to FIGS. 2D and 2D and then etched back, the regions between being shown in FIG. 2D the polysilicon spacers 122 are completely filled with silicon dioxide and the polysilicon layer 121 and the polysilicon spacer 122 still remain covered by the fourth electrically insulating layer 123 made of silicon dioxide.
  • a polysilicon layer 124 is in turn applied to the insulating layer 123 made of silicon dioxide according to FIGS. Like the polysilicon layer 121, the polysilicon layer 124 has a layer thickness of approximately 50 nm, so that in the second trench structure 118 polysilicon spacers 125 are trained. The height of the polysilicon layer 124 and the polysilicon spacers 125 form an at least partial lateral overlap with the polysilicon layer 111.
  • the polysilicon layer 124 or the polysilicon spacers 125 serve to form the second gate electrode, the electrical charge transmission of the multiple tunnel barrier being controllable by applying an electrical voltage to the second gate electrode.
  • the height of the floating gate 105 protrudes slightly beyond the area of the insulating layer 123, so that the floating gate 105 on the one hand and the polysilicon layer 124 or the polysilicon spacer 125 on the other hand for formation the second gate electrode overlap in the vertical direction.
  • care must be taken to ensure that this overlapping area is as small as possible in order to prevent the second gate electrode from interacting with the floating gate 105 when data is being written or erased in the semiconductor memory element - Prevent arrangement 100.
  • CMP chemical mechanical polishing
  • a trench is etched into layer 126 using photolithography.
  • the data line 127 is structured using chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • FIG. 300 A top view of a semiconductor memory element arrangement 300 produced by the method described above is shown schematically in FIG.
  • the semiconductor memory element arrangement 300 has a total of sixteen semiconductor memory elements arranged in a matrix
  • F 2 has a floating gate, on each of which a multiple tunnel barrier is applied.
  • a first trench structure 301 extends in the vertical direction between the semiconductor memory elements F ⁇ , F12, •• -, F44 and a second trench structure 302 in the horizontal direction.
  • the first and second gate electrodes are in the regions 304 hatched in FIG educated .
  • the first and second gate electrodes extend perpendicular to the plane of the drawing in the first and second trench structures 301, 302, the first gate electrodes adjacent to the floating gates and the second gate electrodes adjacent to the multiple tunnel barriers the
  • Semiconductor memory elements F ⁇ , F12, ..., F44 are formed ..
  • this can be done by applying an electrical voltage to the first gate electrode Contents of each memory cell can be read.
  • the electrical charge transmission of the multiple tunnel barrier of each memory cell can be controlled by applying an electrical voltage to the second gate electrode.
  • the direction of the source or drain regions and the data line is shown by arrow 303.
  • the first and the second trench structures 301, 302 have a different width. While in the first trench structure 301 the entire width of the trenches formed is filled with polysilicon to form the first and second gate electrodes, in the second trench structure 302 the first and second gate electrodes are formed as spacers. Two first and second gate electrodes are thus formed in the second trench structure, which are separated from one another by an electrically insulating layer running between the respective spacers.
  • the semiconductor memory element arrangement 300 thus forms a high-density raster structure.
  • the arrangement of the individual memory cells corresponds to a so-called “virtual ground array”.
  • a programming example of the semiconductor memory element arrangement 300 from FIG. 4 is explained with reference to FIG.
  • data is written in the semiconductor memory element arrangement 300 by applying a positive voltage of +3 volts to the second gate electrode and applying a negative voltage of -3 volts to the data line 210.
  • Data is deleted accordingly by applying a positive voltage of +3 volts to the second gate electrode and applying a positive voltage of +3 volts to the data line.
  • the voltage of +3 volts applied to the second gate electrode increases the electrical charge transmission of the multiple tunnel barrier during the write or erase process and enables the supply or discharge of electrical charge to and from the floating gate 105 and thus an inverting of the channel located between the source and drain regions.
  • data is read in the semiconductor memory element arrangement 300 by applying a positive voltage of +3 volts to the first gate electrode and applying a lower positive voltage, for example +2 volts, to all drain lines, while all sources -Lines are set to 0 volts.
  • the writing of data in the semiconductor memory element arrangement 300 corresponds to the setting of a logical “1” and the deletion to the setting of a logical “0”. These logical values are always set on the entire addressed word line using the corresponding data lines.
  • the fact that only the first gate electrode is used for reading data from the semiconductor memory element arrangement according to the invention and only the second gate electrode for writing data means that a reduction in the electrical charge on the floating gate is achieved via the multiple tunnel barrier of the reading process is prevented, so that the reading process can take place without interference.
  • EP 0 908 954 A2 (Semiconductor memory device and manufacturing method thereof"; note: Hitachi Ltd.)

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un procédé pour produire un ensemble d'éléments de mémoire à semi-conducteurs. Ce procédé consiste à appliquer sur un substrat une couche isolante et un système de couches constitué d'une grille flottante et d'un ensemble barrière tunnel appliqué sur la grille flottante. Une première électrode de grille est formée de manière adjacente à la grille flottante et une deuxième électrode de grille de manière adjacente à l'ensemble barrière tunnel. Les électrodes de grille sont formées, dans une première structure de tranchées, par des premières tranchées parallèles, et, dans une deuxième structure de tranchées, par des deuxièmes tranchées parallèles les unes aux autres et perpendiculaires aux premières tranchées.
EP02754443A 2001-09-19 2002-07-25 Ensemble d'elements de memoire a semi-conducteurs Withdrawn EP1428261A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10146215A DE10146215A1 (de) 2001-09-19 2001-09-19 Verfahren zum Herstellen einer Halbleiterspeicherelement-Anordnung, Verfahren zum Betreiben einer Halbleiterspeicherelement-Anordnung und Halbleiterspeicherelement-Anordnung
DE10146215 2001-09-19
PCT/DE2002/002742 WO2003028107A1 (fr) 2001-09-19 2002-07-25 Ensemble d'elements de memoire a semi-conducteurs

Publications (1)

Publication Number Publication Date
EP1428261A1 true EP1428261A1 (fr) 2004-06-16

Family

ID=7699576

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02754443A Withdrawn EP1428261A1 (fr) 2001-09-19 2002-07-25 Ensemble d'elements de memoire a semi-conducteurs

Country Status (4)

Country Link
US (1) US20040252576A1 (fr)
EP (1) EP1428261A1 (fr)
DE (1) DE10146215A1 (fr)
WO (1) WO2003028107A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7183161B2 (en) * 2004-09-17 2007-02-27 Freescale Semiconductor, Inc. Programming and erasing structure for a floating gate memory cell and method of making
US8017480B2 (en) * 2006-06-13 2011-09-13 Macronix International Co., Ltd. Apparatus and associated method for making a floating gate cell in a virtual ground array
US9576657B1 (en) * 2015-09-29 2017-02-21 Sandisk Technologies Llc Memory cells including vertically oriented adjustable resistance structures
CN112490140B (zh) * 2020-11-18 2023-08-01 长江存储科技有限责任公司 一种监测沟道通孔的开封方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0582795A (ja) * 1991-08-22 1993-04-02 Rohm Co Ltd 半導体記憶装置
US5497017A (en) * 1995-01-26 1996-03-05 Micron Technology, Inc. Dynamic random access memory array having a cross-point layout, tungsten digit lines buried in the substrate, and vertical access transistors
DE19600307C1 (de) * 1996-01-05 1998-01-08 Siemens Ag Hochintegrierter Halbleiterspeicher und Verfahren zur Herstellung des Halbleiterspeichers
EP0843361A1 (fr) * 1996-11-15 1998-05-20 Hitachi Europe Limited Dispositif de mémoire
US6060723A (en) * 1997-07-18 2000-05-09 Hitachi, Ltd. Controllable conduction device
EP0843360A1 (fr) * 1996-11-15 1998-05-20 Hitachi Europe Limited Dispositif de mémoire
JP3554666B2 (ja) * 1997-10-07 2004-08-18 株式会社日立製作所 半導体メモリ装置
US5973356A (en) * 1997-07-08 1999-10-26 Micron Technology, Inc. Ultra high density flash memory
WO2001006570A1 (fr) * 1999-07-20 2001-01-25 Infineon Technologies Ag Cellule de memoire a semi-conducteurs non volatile et son procede de production

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO03028107A1 *

Also Published As

Publication number Publication date
DE10146215A1 (de) 2003-04-10
US20040252576A1 (en) 2004-12-16
WO2003028107A1 (fr) 2003-04-03

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