EP1393364A2 - Boitier en plastique associe a plusieurs puces a semi-conducteur et a une plaque de modification de cablage, et procede de fabrication dudit boitier dans un moule de moulage par injection - Google Patents

Boitier en plastique associe a plusieurs puces a semi-conducteur et a une plaque de modification de cablage, et procede de fabrication dudit boitier dans un moule de moulage par injection

Info

Publication number
EP1393364A2
EP1393364A2 EP02740387A EP02740387A EP1393364A2 EP 1393364 A2 EP1393364 A2 EP 1393364A2 EP 02740387 A EP02740387 A EP 02740387A EP 02740387 A EP02740387 A EP 02740387A EP 1393364 A2 EP1393364 A2 EP 1393364A2
Authority
EP
European Patent Office
Prior art keywords
plastic housing
ppp
underside
rewiring plate
semiconductor chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02740387A
Other languages
German (de)
English (en)
Inventor
Andreas Wörz
Thomas Zeiler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1393364A2 publication Critical patent/EP1393364A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
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    • H01L2924/01005—Boron [B]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01L2924/01032—Germanium [Ge]
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/01052—Tellurium [Te]
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    • H01L2924/12—Passive devices, e.g. 2 terminal devices
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the invention relates to a plastic housing with a plurality of semiconductor chips and a rewiring plate and a method for producing the plastic housing by means of an injection mold according to the type of the independent claims.
  • the packaging technology of individual semiconductor chips is switched to packaging techniques in plastic housings with a plurality of semiconductor chips arranged in a common housing.
  • the rewiring plates prevent rational and economically advantageous embedding of the semiconductor chips on the top side of the rewiring plate and the bonding channels on the underside of the rewiring plate, especially since the surfaces of the rewiring plate that are to accommodate external contacts on the underside of the rewiring plate must be kept free of plastic.
  • the object of the invention is to provide a plastic housing with a plurality of semiconductor chips on a rewiring plate, which can be produced economically using a special injection mold.
  • a plurality of semiconductor chips are arranged in rows and columns in the plastic housing, the semiconductor chips having active top sides and passive rear sides and edge sides.
  • the active tops of the semiconductor chips are arranged on an upper side of a rewiring plate.
  • the redistribution board has bond channels from the top to the bottom of the redistribution board.
  • the bond channels are arranged in columns and one behind the other on the underside of the rewiring plate.
  • a plastic housing compound covers the top of the redistribution board and at least the edge sides of the semiconductor chips.
  • the underside of the plastic housing consists of the underside of the rewiring plate with output contact areas and of strip-shaped bond channel covers arranged in columns.
  • the bond channel covers protrude beyond the underside of the rewiring plate, but do not protrude as far from the underside of the U wiring plate as the external contacts to be applied.
  • the bond channel covers fulfill an additional function in that they distance from a printed circuit board or another stacked electronic component when the electronic component is soldered on
  • the plastic housing consists in the columnar strip-shaped bond channel covers that protrude beyond the underside of the rewiring plate and have a spatial plastic connection at their ends to the top of the plastic housing.
  • This spatial plastic connection at the ends of the strip-shaped bond channel covers has the advantage that the material of the bond channel covers can consist of the same plastic mass as the top of the plastic housing. Without these strip-shaped elongated bond channel covers, the housing would have to be carried out in two complex process steps to cover the top side of the rewiring plate on the one hand and to cover the bond channel openings on the bottom side of the cover foils on the other hand. With this Embodiment of the plastic housing, however, the elongated strip-shaped bond channel covers on the underside can be formed in one process step during the injection of the plastic aces from the top of the plastic housing.
  • the rewiring plate has an insulating layer on the top side to the semiconductor chips and on its bottom side has contact connection areas, rewiring lines and output contact areas for external contacts.
  • the metal structure of the underside of contact connection areas, rewiring lines and output contact areas for external contacts can be laminated onto the insulating layer, so that the insulating layer forms the actually load-bearing substrate of the rewiring plate.
  • the contact connection areas on the underside of the rewiring plate are also called bond fingers because bond wires produce an electrical connection from contact areas of the active top side of the semiconductor chip in the bond channel to the contact connection areas or bond fingers on the underside of the rewiring plate.
  • rewiring lines lead from the contact connection areas or bond fingers to individual output contact areas, to which external contacts can be applied.
  • the output contact areas are surrounded by a solder stop layer, which in particular covers the rewiring lines, so that they are not damaged when the external contacts are attached or are coated with external contact material, the external contacts protruding further from the underside of the redistribution plate than the bonding channel covers ,
  • the elongated and strip-shaped bond channel covers
  • connection lines between the contact surfaces on the active top side of the semiconductor chip and contact connection surfaces Chen on the underside of the rewiring plate in a plastic housing compound This plastic housing is guided at the ends of the strip-shaped bonding channel covers from the top of the plastic housing when packaging in plastic to the bonding channels arranged on the underside of the rewiring plate.
  • the passive rear side of the semiconductor chips can also be covered with the housing plastic compound of the plastic housing. Although this increases the thickness of the plastic housing, at the same time the semiconductor chips are better protected against impacts or other impairments than if the passive rear sides of the semiconductor chips simultaneously form part of the top side of the plastic housing.
  • the external contacts in the external contact areas on the underside of the rewiring board are also arranged in rows and columns and are free of plastic housing compound. These rows and columns of the external contact areas have a standardized step size, which in the case of the BGA housings (ball grid arrays) extends up to a step size of 0.8 mm and is even lower for fine structures of the external contacts.
  • the rewiring plate has solder balls or contact bumps on its underside in the external contact areas, which are arranged on the output contact areas. While the solder balls become contact bumps made of solder material when soldering onto the output contact areas, the contact bumps can also consist of superficially metallized plastic and take any shape.
  • the rewiring plate has through openings from the top of the rewiring plate to each column-shaped strip-shaped bond channel cover on the underside of the rewiring plate.
  • these through openings are dimensioned such that they represent throttle openings for the liquid housing plastic compound.
  • These throttle openings advantageously prevent the strip of bond channel covers from being filled up in an uncontrolled manner with plastic mass, since they represent a flow resistance for the plastic, so that first the upper side of the housing can be coated with plastic mass under full injection pressure and only then is the plastic significantly delayed via the throttle openings Bond channels or the strips for bond channel covers sic. can spread.
  • the throttle openings are arranged on the upper side of the rewiring plate in an area which is ultimately wetted by the liquid plastic housing on the upper side during the production of the plastic housing.
  • the plastic housing according to the invention can also be separated into individual electronic components by sawing the plastic housing in rows and columns. Not only is the plastic mass sawn into individual pieces, but also the rewiring board is separated into areas belonging to the respective semiconductor chip.
  • Such an electronic component differs from conventional ones Components in that it has sawn outer edges in packaged form, which advantageously allow a high, precise outer dimension of the electronic components.
  • the external contact areas have external contacts arranged in rows and columns. This arrangement can correspond to international standards with internationally defined step sizes, so that the semiconductor chips are suitable for installation on standardized printed circuit boards.
  • a new injection mold is created, the plastic housing having semiconductor chips arranged in several rows and columns.
  • the upper side of the plastic housing is formed by an upper side mold of the injection mold, which rests on the upper side of the rewiring plate with a sealing sleeve and has an injection funnel, via which the housing plastic mass is pressed with an injection pressure onto the upper side of the rewiring plate and at least onto the edge sides of the semiconductor chips.
  • an underside shape of the injection mold is provided on the underside, which surrounds the bond channel areas with sealing ribs and has a vent hole at the end of each bond channel area, so that the plastic housing compound is first injected onto the top side and becomes a strip-shaped bond channel cover via the throttle opening, while that in the hollow molds accumulated air is pressed out through the ventilation hole at the end of the underside mold.
  • top of the plastic housing is packaged over a large area with the help of injection molding technology, a high one is formed Pressure that can lead to warping of the rewiring plate, which is why, in addition to the sealing ribs that surround the bond channel regions, support ribs are also provided for the underside shape of the injection mold, which are intended to support the U wiring plate in the other regions. In addition, a supporting rib is provided for the underside shape opposite the sealing sleeve of the top shape.
  • a method for producing a plastic housing of the present invention which has a plurality of semiconductor chips arranged in rows and columns and arranged on a rewiring plate, has the following method steps: Providing a rewiring plate with semiconductor chip positions arranged in rows and columns and sawing track areas provided in between and with at least a bond channel arranged on each semiconductor chip position and with a throttle opening for spatial connection of the top and bottom of the rewiring plate,
  • the housing plastic mass is injected under a pressure of 8-15 MPa via an injection funnel.
  • a high pressure is first applied to the top of the rewiring plate, so that there is a risk that the rewiring plate will bulge because the injection pressure acts on the rewiring plate only on one side. Only when the liquid plastic casing mass reaches the through openings for the bond channel covers on the underside of the rewiring plate is a back pressure generated in parts of the underside, namely where the elongated bond channel cover is created.
  • support ribs are provided on the underside shape, which are arranged on the one hand opposite the sealing sleeve on the top and on the other hand between the elongated bond channel covers are arranged.
  • the ventilation holes in the underside shape at the end of the bond channel cover cavities ensure that no air poles ⁇ CO N ho P ⁇ o C ⁇ o ⁇ . O C ⁇
  • P P- o P P- s rt, ⁇ P ⁇ t »PP ⁇ P- P cn n ⁇ P P- P- Hi ⁇ iQ ⁇ P- P- to P- a P pn ⁇ ⁇ cn P- P ⁇ £ rt rt ⁇ tr PO o C ⁇ P tr ⁇ ⁇ rt ⁇ Q
  • P P- ⁇ p P iQ ⁇ rt rt PPP iQ> ⁇ P ⁇ ⁇ C ⁇ P rt ⁇ ⁇ P ⁇ ⁇ ⁇ rt P- OP ⁇ P- Hi P op: WP P- Hi - ⁇ OP ⁇ P ⁇ P ⁇ i? d Cn P-
  • P- tr et p P tr P tP P Hi P cn PPP rt ⁇ P- tr P " ⁇ - Pi tr Hi ⁇ ⁇ P- rt ⁇ - ⁇ Hi 1 1 rt ⁇ Q ⁇ cn PP rt ⁇ sn 1 P ⁇ ⁇ rt O cn P- 1 rt ⁇
  • Standard systems for injection can be used without the need for additional materials or foils.
  • a MAP technology can be used.
  • a spraying process in a single stage or a single process step is possible, so that multi-stage injection molding processes are unnecessary.
  • Both the device and the method can be used for different substrate materials or materials of the rewiring plate, so that both metal plates and ceramic plates or printed circuit boards or system carrier tapes made of plastic can be used.
  • This rewiring plate has throttle bores as through openings for the plastic housing compound in order to generate a pressure difference between the cavity on the semiconductor chip side and the bonding channel cavities when producing plastic housings.
  • FIG. 1 shows a schematic top view of a plastic housing for several semiconductor chips
  • FIG. 2 shows a schematic view from below of a plastic housing for several semiconductor chips
  • FIG. 3 shows a schematic cross section along the section line A-A in FIG. 1 and FIG. 2 through a plastic housing with an injection mold
  • Figure 4 shows a portion of a schematic cross section of an injection mold along the section line AA in Figure 1 and Figure 2 of a first embodiment of the invention
  • Figure 5 shows a portion of a schematic cross section of an injection mold along the section line AA in Figure 1 and Figure 2 of a second embodiment of the Invention
  • FIG. 6 shows a partial area of a schematic cross section of an injection mold along the section line B-B in FIG. 1 and FIG. 2.
  • FIG. 1 shows a schematic plan view of a plastic housing 14 for a plurality of semiconductor chips 3.
  • the reference symbol 1 denotes rows of semiconductor chips and the reference symbol 2 columns of semiconductor chips in the plastic housing 14.
  • the reference symbol 5 denotes the passive rear side of the semiconductor chips and the reference symbol 6, 7, 8, 9 identify edge sides of the semiconductor chip.
  • the reference numeral 10 denotes the upper side of a rewiring plate 11.
  • the reference numeral 12 denotes a bond channel below the semiconductor chip 3.
  • the reference numeral 18 denotes bond channel covers,
  • the reference numeral 25 denotes a housing plastic compound, the reference symbol 35 an injection funnel for the housing plastic compound 25.
  • the reference symbol 37 denotes the area in which a sealing sleeve rests on the rewiring plate 11 and the reference symbol 42 • denotes sawing track areas for the separation of the plastic housing 14 into electronic components 41.
  • the semiconductor chips 3 of the plastic housing 14 are arranged in rows 1 and columns 2.
  • Pi Pi P P- " » Hi ⁇ cn tr ⁇ 3 P ⁇ ⁇ ⁇ ⁇ PP • • rt rt PPP
  • ⁇ tr P- P 1 P ⁇ uq P- rt Hl uq cn ⁇ tr ⁇ uq p. PP ⁇ - P tr P • PP cn P tr rt Pi fr p: P 1 P ⁇ PP 0 to ⁇ P rt tr ⁇ P ⁇ 3 ⁇ - P a> z P cn rt P o P.
  • P ⁇ P ⁇ ⁇ P P- is PPP cn P- ⁇ to 3 ⁇ ⁇ P- ⁇ ⁇ uq tr rt 4-. tr cn ⁇ - uq co P ⁇ P ⁇ uq ⁇ o uq rt P ⁇ - PPP 1 P rt P- 3 rt P • ⁇ P to ⁇ Pi rt PXP
  • P P P P- 3 P P fco P- ⁇ tr uq p: X) ⁇ uq n P ⁇ ⁇ ⁇ rt tr uq uq P fco uq ⁇ ⁇ ⁇
  • P. P co PP P ⁇ 0 ⁇ P Hi P p: rt to P- PP uq ⁇ cn P CD tr uq ⁇ P tr og P. et fco PNP 1 N 0 ⁇ - rt rt ' P. P" P 1 P ⁇ 1 P P- ⁇ P- to ⁇ tr 3 00 PPPH g P- P ⁇ Cd PP "PN ⁇ P ⁇ pj: 3 ⁇ PP ⁇ •

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

La présente invention concerne un boîtier en plastique (14) pour plusieurs puces à semi-conducteur (3), une plaque de modification de câblage (11) sur laquelle sont placées les puces à semi-conducteur (3), un moule de moulage par injection destiné à la fabrication dudit boîtier en plastique (14) ainsi qu'un composant électronique qui peut être fabriqué par combinaison du moule de moulage par injection, de la plaque de modification de câblage (11) et du boîtier en plastique (14). La présente invention concerne encore un procédé qui permet, grâce à l'utilisation de la plaque de modification de câblage (11) selon la présente invention et du moule de moulage par injection en deux parties, la fabrication d'un boîtier en plastique (14) de ce type avec plusieurs puces à semi-conducteur (3) pour plusieurs composants électroniques.
EP02740387A 2001-06-05 2002-06-05 Boitier en plastique associe a plusieurs puces a semi-conducteur et a une plaque de modification de cablage, et procede de fabrication dudit boitier dans un moule de moulage par injection Withdrawn EP1393364A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10127009A DE10127009A1 (de) 2001-06-05 2001-06-05 Kunststoffgehäuse mit mehreren Halbleiterchips und einer Umverdrahtungsplatte sowie ein Verfahren zur Herstellung des Kunststoffgehäuses in einer Spritzgußform
DE10127009 2001-06-05
PCT/DE2002/002044 WO2002099871A2 (fr) 2001-06-05 2002-06-05 Boitier en plastique associe a plusieurs puces a semi-conducteur et a une plaque de modification de cablage, et procede de fabrication dudit boitier dans un moule de moulage par injection

Publications (1)

Publication Number Publication Date
EP1393364A2 true EP1393364A2 (fr) 2004-03-03

Family

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EP02740387A Withdrawn EP1393364A2 (fr) 2001-06-05 2002-06-05 Boitier en plastique associe a plusieurs puces a semi-conducteur et a une plaque de modification de cablage, et procede de fabrication dudit boitier dans un moule de moulage par injection

Country Status (7)

Country Link
US (1) US20040175866A1 (fr)
EP (1) EP1393364A2 (fr)
JP (1) JP2004528729A (fr)
KR (1) KR20040012896A (fr)
DE (1) DE10127009A1 (fr)
TW (1) TW558813B (fr)
WO (1) WO2002099871A2 (fr)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW567562B (en) 2001-01-15 2003-12-21 Chuen Khiang Wang Method of packaging microchip devices, the interposer used therefor and the microchip device packaged thereby
DE10297756B4 (de) * 2002-06-19 2008-03-06 United Test And Assembly Center (S) Pte Ltd. Konfektionierung einer Mikrochip-Vorrichtung
JP2005530358A (ja) 2002-06-19 2005-10-06 ワン，チェン，キーアン マイクロチップデバイスのパッケージング
DE10320579A1 (de) * 2003-05-07 2004-08-26 Infineon Technologies Ag Halbleiterwafer, Nutzen und elektronisches Bauteil mit gestapelten Halbleiterchips, sowie Verfahren zur Herstellung derselben
JP4243177B2 (ja) * 2003-12-22 2009-03-25 株式会社ルネサステクノロジ 半導体装置の製造方法
US7235423B1 (en) * 2004-11-05 2007-06-26 Super Talent Electronics, Inc. Molded memory card production using carrier strip
US20060223227A1 (en) * 2005-04-04 2006-10-05 Tessera, Inc. Molding method for foldover package
US20070292708A1 (en) * 2005-08-12 2007-12-20 John Pereira Solder composition
US20080175748A1 (en) * 2005-08-12 2008-07-24 John Pereira Solder Composition
DE102005046737B4 (de) * 2005-09-29 2009-07-02 Infineon Technologies Ag Nutzen zur Herstellung eines elektronischen Bauteils, Bauteil mit Chip-Durchkontakten und Verfahren
DE102008032330A1 (de) 2008-07-09 2010-01-14 Akro Plastic Gmbh Verfahren zur Herstellung von montagefertigen, kunststoffumspritzten Elektronikbauteilen bzw. Elektronikbaugruppen
US20100081237A1 (en) * 2008-09-30 2010-04-01 Avago Technologies Fiber Ip (Singapore) Pte. Ltd. Integrated Circuit Assemblies and Methods for Encapsulating a Semiconductor Device
KR101012461B1 (ko) * 2010-07-13 2011-02-08 이원철 본체 코팅층의 수명감지부가 구비된 조리기기
CN102315200A (zh) * 2011-09-02 2012-01-11 华为终端有限公司 一种芯片封装结构、封装方法及电子设备
KR20140009799A (ko) 2012-07-13 2014-01-23 에스케이하이닉스 주식회사 전자 소자의 패키지 및 제조 방법
KR101688079B1 (ko) * 2015-07-13 2016-12-20 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이의 제조 방법
PL3168874T3 (pl) 2015-11-11 2021-07-12 Lipac Co., Ltd. Obudowa chipów półprzewodnikowych z interfejsem optycznym
DE102016124270A1 (de) 2016-12-13 2018-06-14 Infineon Technologies Ag Halbleiter-package und verfahren zum fertigen eines halbleiter-package

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868349A (en) * 1988-05-09 1989-09-19 National Semiconductor Corporation Plastic molded pin-grid-array power package
US5275546A (en) * 1991-12-30 1994-01-04 Fierkens Richard H J Plastic encapsulation apparatus for an integrated circuit lead frame and method therefor
WO1997001865A1 (fr) * 1995-06-28 1997-01-16 Hitachi, Ltd. Dispositif a semi-conducteurs et son procede de fabrication
KR100386061B1 (ko) * 1995-10-24 2003-08-21 오끼 덴끼 고오교 가부시끼가이샤 크랙을방지하기위한개량된구조를가지는반도체장치및리이드프레임
US6667560B2 (en) * 1996-05-29 2003-12-23 Texas Instruments Incorporated Board on chip ball grid array
DE19736210A1 (de) * 1996-11-12 1998-05-14 Siemens Ag Preßform sowie Verfahren zum Herstellen eines Kunststoffverbundkörpers
US6001672A (en) * 1997-02-25 1999-12-14 Micron Technology, Inc. Method for transfer molding encapsulation of a semiconductor die with attached heat sink
US6048755A (en) * 1998-11-12 2000-04-11 Micron Technology, Inc. Method for fabricating BGA package using substrate with patterned solder mask open in die attach area
US6143581A (en) * 1999-02-22 2000-11-07 Micron Technology, Inc. Asymmetric transfer molding method and an asymmetric encapsulation made therefrom
US6294825B1 (en) * 1999-02-22 2001-09-25 Micron Technology, Inc. Asymmetrical mold of multiple-part matrixes
US6201299B1 (en) * 1999-06-23 2001-03-13 Advanced Semiconductor Engineering, Inc. Substrate structure of BGA semiconductor package
US6210992B1 (en) * 1999-08-31 2001-04-03 Micron Technology, Inc. Controlling packaging encapsulant leakage
DE19954888C2 (de) * 1999-11-15 2002-01-10 Infineon Technologies Ag Verpackung für einen Halbleiterchip
US20030082845A1 (en) * 2000-01-14 2003-05-01 Amkor Technology, Inc. Package for multiple integrated circuits and method of making
DE10014380A1 (de) * 2000-03-23 2001-10-04 Infineon Technologies Ag Vorrichtung zum Verpacken von elektronischen Bauteilen
JP4018375B2 (ja) * 2000-11-30 2007-12-05 株式会社東芝 半導体装置
US6635209B2 (en) * 2000-12-15 2003-10-21 Siliconware Precision Industries Co., Ltd. Method of encapsulating a substrate-based package assembly without causing mold flash
JP2002208656A (ja) * 2001-01-11 2002-07-26 Mitsubishi Electric Corp 半導体装置
US20020173074A1 (en) * 2001-05-16 2002-11-21 Walsin Advanced Electronics Ltd Method for underfilling bonding gap between flip-chip and circuit substrate
US6528408B2 (en) * 2001-05-21 2003-03-04 Micron Technology, Inc. Method for bumped die and wire bonded board-on-chip package
US6668449B2 (en) * 2001-06-25 2003-12-30 Micron Technology, Inc. Method of making a semiconductor device having an opening in a solder mask
US6458626B1 (en) * 2001-08-03 2002-10-01 Siliconware Precision Industries Co., Ltd. Fabricating method for semiconductor package
JP3790705B2 (ja) * 2001-12-27 2006-06-28 新光電気工業株式会社 配線基板およびこれを用いた半導体装置の製造方法
KR100480909B1 (ko) * 2001-12-29 2005-04-07 주식회사 하이닉스반도체 적층 칩 패키지의 제조 방법
US6857865B2 (en) * 2002-06-20 2005-02-22 Ultratera Corporation Mold structure for package fabrication

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO02099871A2 *

Also Published As

Publication number Publication date
WO2002099871A3 (fr) 2003-03-06
KR20040012896A (ko) 2004-02-11
JP2004528729A (ja) 2004-09-16
DE10127009A1 (de) 2002-12-12
US20040175866A1 (en) 2004-09-09
WO2002099871A2 (fr) 2002-12-12
TW558813B (en) 2003-10-21

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