EP1532681A1 - Support de circuit a plusieurs couches et fabrication dudit support - Google Patents

Support de circuit a plusieurs couches et fabrication dudit support

Info

Publication number
EP1532681A1
EP1532681A1 EP03783945A EP03783945A EP1532681A1 EP 1532681 A1 EP1532681 A1 EP 1532681A1 EP 03783945 A EP03783945 A EP 03783945A EP 03783945 A EP03783945 A EP 03783945A EP 1532681 A1 EP1532681 A1 EP 1532681A1
Authority
EP
European Patent Office
Prior art keywords
layer
circuit carrier
structures
layers
rewiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03783945A
Other languages
German (de)
English (en)
Inventor
Frank Daeche
Jochen Dangelmaier
Stefan Paulus
Bernd Stadler
Horst Theuss
Michael Weber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Polaris Innovations Ltd
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1532681A1 publication Critical patent/EP1532681A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
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    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
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    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
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    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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    • H05K2201/2072—Anchoring, i.e. one structure gripping into another
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    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier

Definitions

  • Multi-layer circuit carrier and manufacture of the same
  • the invention relates to a multi-layer circuit carrier and manufacture thereof, and to electronic components which have such a multi-layer circuit carrier in accordance with the preamble of the independent claims.
  • the number and the packing density of microscopic contact areas and / or microscopic flip-chip contacts on the active top sides of the semiconductor chips increase.
  • the grid dimension for arranging such contact areas or flip-chip contacts of a semiconductor chip will also have microscopically small step sizes.
  • microscopic dimensions are understood to be only recognizable and measurable under a light microscope.
  • the Flachlei- ter provide microscopic contact pads inside a plastic or ceramic package, and to enter after ⁇ outside into macroscopically large external leads.
  • macroscopic size is understood to mean dimensions that can be seen and measured with the naked eye.
  • This concept which is based on flat conductors, has the disadvantage that only the outer edges of a circuit carrier for Attachment of the outer flat conductors can be used, while the relatively large underside of the circuit board of an electronic component is not used for the arrangement of external contact areas.
  • This is only achieved by using a flat conductor-free technology with the help of a rewiring body, in which a transition from the microscopic pitch of the contact areas of a semiconductor chip to the macroscopic pitch of the external contact areas of an electronic component is made possible via rewiring lines on an insulation plate.
  • Such rewiring bodies made of rewiring plates or rewiring foils not only have an expensive complex structure, but the density of the rewiring lines and the density of the macroscopic external contact areas increase with increasing contact area density on the semiconductor chip. This increases the complexity of rewiring bodies in cooperation with through contacts through the insulation plate of the rewiring body, so that on the one hand the costs increase and on the other hand the probability of failure when assembling electronic components on the basis of such rewiring bodies increases.
  • the object of the invention is to provide a circuit carrier with which the costs for the production of electronic components can be reduced and the reliability of the circuit carriers is improved.
  • a multilayer circuit carrier with at least one semiconductor chip and / or at least one discrete component is specified.
  • the multilayer circuit board has at least one rewiring layer, an insulation layer and an anchoring layer.
  • the rewiring layer has a rewiring structure, which in turn can have contact pads which are electrically connected to the microscopic contact pads of the semiconductor chips.
  • the rewiring structure can have rewiring lines which can have conductor tracks in the submicrometer range. Such rewiring structures can finally have transition contacts to through structures.
  • the insulation layer has through structures, wherein through structures not only include through contacts, but can also form continuous conductor tracks and / or continuous metal plates.
  • the anchoring layer is arranged between the rewiring layer and the insulation layer and has armature regions or metallic armature plates which fix the position of the through structures in the multilayer circuit carrier.
  • an external contact layer which has external contact surfaces which are electrically connected to the rewiring structure via the through structures and the armature plates.
  • the external contact surfaces are arranged in a predetermined grid dimension on the underside of the circuit carrier.
  • the anchor areas and the passage structures are advantageously made in one piece.
  • Continuous conductor tracks differ from through contacts in that they extend over the full height of an insulation layer and their position by anchor plates in the multilayer circuit carrier is secured.
  • Continuous metal plates differ from flat metal structures in that they extend over the full height of an insulation layer and their position in a multi-layer circuit carrier is secured by anchor plates.
  • the multilayer circuit carrier has the advantage that it realizes external contact areas in a predetermined grid dimension, and thus makes external flat conductors, which are only arranged at the edges of an electronic component, unnecessary.
  • the multilayer circuit carrier has the advantage that each element of the through structures is secured by anchor plates.
  • the multilayer circuit carrier can be formed over a large area and each have at least one semiconductor chip in a plurality of component positions and / or each comprise at least one discrete component. Such component positions can be arranged one behind the other as a single row or can be provided in rows and columns on the multilayer circuit carrier. With such measures, the costs for the production of electronic components or electronic modules can be reduced.
  • the insulation layer with through structure can form a substrate layer which, as a through structure, has only through contacts in a predetermined grid dimension, which corresponds to the grid dimension of the external contact surfaces.
  • each vias has an armature plate, the area of which is larger than the cross section of the vias.
  • the rewiring structure has an electrically conductive filled plastic.
  • the filling consists of metal particles, in particular of silver particles.
  • the circuit board can be expanded as required by additional rewiring layers with rewiring structures made of electrically conductive filled plastic.
  • Through contacts can be arranged in intermediate layers of insulation material, which can also have electrically conductive filled plastic. This results in an overall structure for a multi-layer circuit carrier which, apart from the substrate layer with its metallic through contacts, has only filled plastics.
  • a further variant of the invention provides that the circuit carrier has two insulation layers with through structures, the armature layers of which are arranged on one another with their armature plates.
  • the circuit carrier has two insulation layers with through structures, the armature layers of which are arranged on one another with their armature plates.
  • one of the anchor plates can also have a material component of a eutectic solder, while the other anchor plate has the other component of a eutectic solder, so that a low connection or joining temperature can be achieved when the anchor plates are joined to one another.
  • one of the pair of anchor plates may be gold, or one of the pair of anchor plates may have a gold alloy and the other of the pair of anchor plates may have tin or a tin alloy, so that a connection of a gold-tin eutectic occurs, which already occurs at low solder temperature.
  • one of the two joining partners has anchor plates with a gold coating and the other of the joining partners has anchor plates with an aluminum coating.
  • a further development of the invention can be achieved if one of the insulation layers of a multi-layer circuit carrier as a hollow housing has a recess for receiving at least one semiconductor chip and / or a discrete component.
  • This insulation layer which is designed as a hollow housing, can form the uppermost layer of the multilayer circuit carrier and at the same time terminate the circuit carrier in its recess, including the at least one semiconductor chip and / or the at least one discrete component.
  • the insulation layer with through structures is used in three versions, in the lowest layer of the layer sequence as a substrate layer with only through contacts and anchor plates in an anchoring layer on the insulation layer.
  • An insulation layer with through structures is arranged below, which in addition to through contacts also has continuous conductor tracks and / or continuous metal plates and which additionally bears at least one semiconductor chip and / or at least one discrete component.
  • an insulation layer is arranged, which is designed as a hollow housing and in the cutouts of which the at least one semiconductor chip and / or the at least one discrete component is arranged.
  • Such multilayer circuit carriers with buried semiconductor chips and / or buried discrete components form a compact component housing in each component position of the multilayer circuit carrier, which has an extremely small component thickness and has a predetermined arrangement of external contact surfaces on its underside, which are inside the electronic component or inside the more - layered switch plate with semiconductor chips and / or discrete components are connected.
  • the transparent plastic being able to be designed as a hollow housing and serving for image and / or radiation detection.
  • the hollow housing made of transparent plastic which is provided as a layer of a multilayer circuit carrier, has the advantage that electromagnetic waves can reach the surface of the semiconductor chip and / or the discrete component without being damped.
  • the multilayer circuit carrier with a semiconductor chip can thus form a light and / or UV and / or IR detector.
  • the transparent plastic can be designed as a detector lens over the semiconductor chip or over the discrete component, such as a photoresistor, so that the detector efficiency is increased.
  • One of the insulation layers of a multi-layer circuit carrier can have a continuous metal plate, this metal plate being designed as a shielding plate.
  • this insulation layer designed as a housing can additionally have through contacts in order to ensure an electrical connection from the underside of the circuit carrier equipped with external contact surfaces to the top of the circuit carrier.
  • a continuous metal plate as a chip island, which can accommodate a semiconductor chip on one side. On this chip island can lead to the lowest potential of an electronic circuit on the other side of the metal plate.
  • the contact areas of the active upper side of the semiconductor chip can be connected to the rewiring structure via bond connections, the rewiring structure also having continuous contact connection areas to which the bond wires of the bond connection can be electrically connected in addition to continuous conductor tracks ,
  • a further possibility of preparing a semiconductor chip with contact areas for the multilayer circuit carrier is to provide flip-chip contacts on the contact areas of the semiconductor chip. These can be flat contact structures or the flip-chip contacts can have contact balls or bumps. Also for the connection of semiconductor chips that are prepared for a flip-chip connection technology, in addition to continuous conductor tracks, continuous contact connection areas are also provided, to which the semiconductor chip can be applied using flip-chip technology.
  • the multilayer circuit carrier is provided for a plurality of component positions, it can be applied after the at least one semiconductor chip or the at least one component has been applied and after embedding these electronic elements in an insulation layer made of a plastic housing compound or by covering these electronic elements with an insulation layer which is designed as a hollow housing, are separated into individual components.
  • the costs for the individual components can thus be considerably reduced, since the multilayer circuit carrier simultaneously represents the housing for several individual electronic components.
  • a plurality of circuit carriers made of insulation layers arranged in pairs with through structures can be stacked and connected via vias to a benefit which likewise has several component positions for electronic components and can then be divided into individual electronic components.
  • the electronic components separated from a multi-layer circuit carrier or from a panel can have a rewiring structure made of conductive plastic.
  • This has the advantage that the thermal expansion behavior of the conductive plastic can completely match the surrounding plastic housing mass, so that no thermomechanical stresses occur in such a plastic housing. Only the through contacts of the lowermost insulation layer, which is also based on the substrate layer, could come loose from the plastic, but this is prevented by the anchoring layer, which is basically arranged between an insulation layer and a rewiring layer, and its anchor plate.
  • Another electronic component made from such multilayer circuit carriers or from such uses can include a stack of a semiconductor chip on an insulation layer have elongated through contacts and an insulation layer with through contacts in a predetermined grid dimension of external contact surfaces.
  • Such elongated through contacts have the advantage that the external contacts can be arranged with their pitch below the surface of the semiconductor chip, which corresponds to a so-called “fan-in”, and can also be present outside the region of the semiconductor chip, which is known as the "fan-out””corresponds.
  • This is understood to mean an area of the external contact layer which is arranged outside the projection of the semiconductor chip area onto the external contact layer, while external contact areas below the semiconductor chip comprise the external contact areas which are arranged within the projection of the semiconductor chip area onto the external contact layer.
  • the elongated through contacts thus form continuous conductor tracks in order to adapt the grid dimension of the contact surfaces of a chip to the predetermined grid dimension of the external contacts in the external contact position.
  • the multilayer circuit carrier is in fact also suitable for adapting or aligning discrete electronic components with their electrodes to predetermined grid dimensions of a flat conductor frame, for example when electrically adapting or matching input or output capacitances between individual flat conductors of a flat conductor frame or input and / or output inductances of an electronic circuit between flat conductor connections are.
  • a method for producing a multilayer circuit carrier with at least one rewiring layer, a connection core layer, an insulation layer which has through structures, and with an external contact layer has the following method steps.
  • a metal plate for producing an insulation layer with through structures is provided.
  • a photoresist layer is applied to the metal plate and this photoresist layer is structured, leaving open areas on which through structures can be deposited.
  • chemical or galvanic through structures are deposited on the exposed surfaces of the metal plate.
  • the photoresist layer is removed from the metal plate and embedded in a thermally more stable plastic housing compound
  • An anchoring layer is applied to the self-supporting insulation layer with through structures by selectively depositing anchor plates on the surfaces of the through structures, the areas of the anchor plates being made larger than the exposed surface areas of the through structures.
  • a rewiring layer can then be applied to the anchoring layer structured in this way by selectively applying a rewiring structure to the anchoring layer.
  • the anchor plates also serve as through contacts to the electrically conductive rewiring structure.
  • the multilayer circuit carrier can then be at least one semiconductor chip and / or at least one discrete component are completed.
  • This method has the advantage that the anchoring layer and the anchor plates embedded in the anchoring layer fulfill a double function, on the one hand mechanically securing the position of the through structures and on the other hand serving as through contacts for connection to the electrically conductive rewiring structure. This saves at least one additional insulation layer with correspondingly voluminous through contacts and reduces the height of the otherwise necessary insulation layer to the height of the anchoring layer. By saving a complete additional process step, the total costs of the process for producing a multilayer circuit carrier can be reduced.
  • the electrically conductive rewiring structure can advantageously be structured from conductive plastic by means of photolithography and / or by means of printing technology.
  • the photolithography technique is advantageous for the microscopic structuring of contact pads that correspond to the contact areas of a semiconductor chip, since it can implement structures in the micrometer range exactly.
  • the printing techniques are advantageous if U wiring structures are to be designed as intermediate layers, for example for a multi-layer circuit carrier with a plurality of rewiring layers arranged one above the other.
  • printing techniques, stencil printing and / or screen printing and / or jet printing can be used.
  • jet printing summarizes techniques that work with a pressure jet and a conductive plastic structure with such a pulsed can print the plastic jet.
  • a plastic can be filled with conductive particles, such as silver particles.
  • the plastic can be filled with correspondingly insulating particles.
  • insulating plastic areas and conductive plastic areas can be applied at the same time, which represents a cost advantage in terms of process technology.
  • jet printing techniques can realize finer structures for the rewiring structure than screen printing or stencil printing techniques, so that photolithographic steps for critical dimensions can be dispensed with, which in turn lowers the process costs.
  • a multi-layer circuit carrier should have a plurality of stacked and stacked rewiring layers, then any number of insulation layers with rewiring layers arranged thereon can be provided on the circuit carrier using the techniques mentioned above, with alternating insulation layers with through contacts and insulation layers with rewiring structures be applied.
  • a multilayer circuit board for producing a substrate layer which consists of an insulation layer with through contacts and which has an external contact layer with external contacts in a predetermined grid dimension.
  • individual polymer layers are applied, which serve as rewiring layers or as insulation layers.
  • a further method can be specified, in which the same technology is used both for the production of insulation layers as a substrate layer with through contacts and for the production of insulation layers with through structures. This avoids special techniques for the production of rewiring structures and reduces the costs for the production of a multilayer circuit carrier.
  • a method for producing a multilayer circuit carrier with at least two insulation layers which are arranged in pairs has the following method steps. First, at least two metal plates are provided for the production of the two insulation layers with through structures. Subsequently, photoresist layers are applied and structured, the metal plates being covered with photoresist, leaving open areas on which through structures as through contacts and / or as a rewiring structure in the form of continuous conductor tracks and / or continuous metal plates are to be deposited. Then through structures are chemically or galvanically deposited in the exposed areas and the photoresist is removed from the metal plates. Instead of the photoresist layer, a thermally more stable plastic housing compound can now be applied by embedding the passage structures and leaving surface areas of the passage structures free.
  • both metal plates are removed, so that two self-supporting insulation layers with through structures are available.
  • An anchoring layer is now selectively applied to these self-supporting insulation layers with through structures.
  • anchor plates with a larger area than the exposed surface areas of the passage structures are placed on the passage structures.
  • the insulation layers are joined in pairs with through structures by connecting the anchor plates of the anchoring layers. This pairing of the anchor plates creates a distance between the insulation layers with through structures, so that no short circuits occur, except at the desired positions of the anchor plates.
  • the space between the insulation layers can be filled with thermally stable plastic housing compound.
  • a second insulation layer is practically formed on an insulation layer, which only has vias to external contact surfaces in a predetermined pitch, by connecting or joining the respective anchor plates of the respective anchor layer, with a small distance of twice the size of the anchor plate thickness between the two Insulation layers with through contacts are created.
  • This distance is between 3 and 10 ⁇ m and can be filled with plastic housing compound.
  • the lower insulation layer only has vias, the upper insulation other through structures, such as continuous conductor tracks and continuous metal plates, as well as continuous contact connection areas and continuous connecting contacts.
  • the upper insulation layer, with its through structures, therefore completely replaces a rewiring layer to be produced separately, so that the manufacturing costs of this method are reduced compared to the method explained above.
  • Metal layers are not sufficient to represent a self-supporting insulation layer and to apply the further process steps to it, such as the application of an anchoring layer, the step of removing the metal plate can also take place after the application of the anchoring layer, which provides greater stability for the attachment and adjustment of the Anchoring position is connected.
  • a critical point of this process is the small distance between the insulation layers with through structures, which must be filled with plastic housing compound. This critical step can be avoided with a further improved process.
  • a method is specified which is used to manufacture a multilayer circuit carrier with at least two insulation layers which are arranged in pairs. These insulation layers in turn have through structures, the lower insulation layer having through contacts and the upper insulation layer with its through structures forming a rewiring layer.
  • metal plates for the production of insulation layers with through structures are provided.
  • Photoresist layers are then applied to these metal plates and these photoresist layers are structured in such a way that surfaces of the metal plates, which are used to apply through structures, are left free.
  • Such through structures can have through contacts and / or a rewiring structure in the form of continuous conductor tracks or continuous metal plates.
  • These through structures are deposited chemically or galvanically on the exposed surfaces of the metal plates.
  • Anchoring layers are then applied directly by selective application of anchor plates on the surfaces of the passage structures, the anchor plates having a larger area than the surface of the passage structures.
  • the photoresist layers on both metal plates are then removed and the insulation layers are then joined in pairs with through structures by connecting the anchor plates of the anchoring layers.
  • the intermediate step of producing self-supporting insulation layers with through structures is therefore dispensed with.
  • the through structures that are still on the metal plates in this process are joined together with their anchor plates made of metal, so that a cavity structure is created which is delimited on the outside by two opposing metal plates, the two joined rewiring structures being arranged between the metal plates are.
  • the delimiting metal plates can simultaneously serve as casting molds for injecting a plastic housing compound between the metal plates while embedding the through structures and the anchor plates of both insulation layers.
  • the metal plates are only removed after these steps, so that a self-supporting double layer made of insulation onslagen with through contacts for the further construction of a multilayer circuit carrier is available.
  • At least one semiconductor chip and / or at least one discrete component can then be applied to the paired insulation layers with through structures.
  • This method has the advantage that the metal plates are simultaneously maintained as a mold until through structures of two insulation layers are connected to one another via corresponding anchor plates, so that a larger cavity is available for embedding the rewiring structures with the anchor plates for the injection of plastic housing compound. This increases the reproducibility and reliability of this method compared to the previously explained methods.
  • an insulation layer is first produced as a substrate layer with through contacts, which are provided in the grid dimension of external contact surfaces.
  • the lower insulation layer of the multilayer circuit carrier is practically created, which at the same time can also be the basis or first substrate layer of a panel which, in addition to the insulation layer as the substrate layer, has further insulation layers with through structures that can be stacked on top of one another or arranged in pairs and then stacked ,
  • the second insulation layer of a pair can be produced as a rewiring layer with rewiring structures in the form of continuous conductor tracks and / or continuous metal plates and / or through contacts as well as continuous contact connection surfaces and continuous transition contacts. Since both the substrate layer and the rewiring layer are made using the same technology by chemical or galvanic deposition on a structured metal plate, the overall process for producing a multi-layer can
  • the through structures are deposited in the form of through contacts and / or continuous conductor tracks and / or continuous metal plates or continuous contact connection surfaces or continuous transition contacts on a metal plate made of a copper alloy.
  • the chemically or galvanically deposited metal can have a nickel alloy which differs in its etching behavior from a copper alloy, so that when the metal plate is subsequently removed, an etching stop occurs at the transition from the copper alloy to the nickel alloy.
  • a copper-clad foil for the chemical or galvanic deposition of nickel is provided on a carrier plate.
  • Such a copper-clad film is just as suitable for the chemical or galvanic application of through structures as a metal plate.
  • the copper-clad film can be pulled off the self-supporting body, so that there is no need for etching or mechanical removal of a metal plate.
  • the self-supporting body can then only be cleaned of copper residues from the copper cladding.
  • etching technology There are two technologies available for removing the metal plate using etching technology, on the one hand dry etching using a plasma and on the other hand wet etching using a metal etching.
  • etching stop through the selection of different materials for the metal plate and for the chemically or galvanically deposited through structures.
  • Such etching stops can be dispensed with in plasma etching, so that similar materials can be deposited on metal plates or with metallized foils.
  • Plasma etching can also be used to clean the surfaces, for example to remove the copper cladding of a copper-clad film after the film has been removed from an insulation layer.
  • the structuring photoresist layer can also be mirrored with the filling of the structures on the metal plate, so that only an etching mask has to be applied in order to remove the excess material except for the metal platelets.
  • a mushroom-shaped enlargement of the passage structures can be achieved by briefly continuing the galvanic deposition after the structures have been filled in, so that the galvanic deposition of the passage structures is overgrown.
  • anchor plates are formed on the passage structures, which ensure that the passage structures are anchored in the plastic housing compound to be subsequently applied.
  • the surface of the insulation layer can first be applied or mirrored with a metal layer by vapor deposition, sputtering or chemical vapor deposition, and this mirrored surface can then be structured into individual anchor plates by means of photolithography.
  • Another possibility for the production of anchor platelets is in the printing technique by printing anchor platelets on the surfaces of the passage structures, whereby on the one hand it is possible to work with a mask which selectively applies anchor platelets on the surface by means of screen printing technique or stencil printing technique or by using a pressure jet technique which describes the tops of the passage structures and thereby prints metal particles with a binder onto the passage structures.
  • semiconductor chips can be applied to the circuit carrier using flip-chip technology.
  • the semiconductor chip has flip-chip external contacts which can be applied directly to contact pads of the uppermost insulation layer with through structures.
  • flip-chip external contacts In the case of a rewiring structure made of electrically conductive plastic, it is also possible to apply such a semiconductor chip with flip-chip external contacts to the corresponding contact connection areas.
  • the advantage of such a flip-chip technology is that there is no need for the bonding step.
  • semiconductor chips are applied to the correspondingly prepared, continuous metal plates with their backs to complete the multilayer circuit carrier, while contact areas on the active top side of the semiconductor chips are connected via bonding wires and / or via bonding tapes to corresponding contact pads on the through structures or on the rewiring structure.
  • the multilayer circuit carrier can also comprise buried semiconductor chips, in that an insulation layer with or without through contacts and with depressions is applied as the uppermost layer of the multilayer circuit carrier, wherein hollow housings can be represented by means of the depressions. After such an uppermost layer has been applied, the multilayer circuit carrier becomes a panel with several component positions, the panel being separated for the production of individual electronic components.
  • the basis of the invention is a flat conductor-free multilayer circuit carrier with galvanically or chemically deposited metal structures.
  • the space between the metal structures is completely filled with non-conductive epoxy material and forms the basis for further layer structures.
  • the surface of the metal structures is left out using mask technology.
  • a conductive layer can then be applied to these exposed metal structures.
  • Such a conductive layer can also be made in multiple layers and a semiconductor chip can be applied to a top layer using flip-chip technology.
  • Multichip packaging and multichip modules can also be realized with such a multilayer circuit carrier.
  • the rewiring levels achieved in the individual insulation layers with through structures make it possible for contacting arrangements to be implemented in a housing packaging regardless of the “footprint” or the predetermined grid size of the external contact surfaces saves floor space compared to flat conductor constructions and can be advantageous in high-frequency applications, since the connection of the external contact areas to the semiconductor chip can be made very short.
  • the various through structures, rewiring structures and anchor plates can be produced very precisely using mask technology, printing techniques being particularly inexpensive.
  • pre-assembled flat conductor-free housings can be installed in a somewhat larger flat conductor-free housing, which in turn can be repeated several times, making it easy to implement any rewiring.
  • This technology is very flexible, inexpensive and allows for quick installation.
  • FIG. 1 shows a schematic cross section of an electronic component with a multilayer circuit carrier of a first embodiment of the invention
  • FIG. 2 shows a schematic cross section of an electronic component with a multilayer circuit carrier of a second embodiment of the invention
  • FIG. 3 shows a schematic cross section of an electronic component with a multilayer circuit carrier of a third embodiment of the invention
  • FIG. 4 shows a schematic cross section of an electronic component of a preliminary stage of the electronic component according to FIG. 3,
  • 5 to 10 show schematic cross sections through intermediate products in the production of a multilayer circuit carrier with a semiconductor chip in each component position of the multilayer circuit carrier in a fourth embodiment of the invention
  • FIG. 5 shows schematic cross sections through two self-supporting insulation layers with through structures
  • FIG. 6 shows schematic cross sections through two self-supporting insulation layers with through structures and attached anchor plates
  • FIG. 7 shows a schematic cross section through a pair of insulation layers joined together with anchor plates lying one on top of the other
  • FIG. 8 shows a schematic cross section through a pair of joined insulation layers with a filled gap between the insulation layers
  • FIG. 9 shows a schematic cross section through a pair of joined insulation layers with applied external contact surfaces
  • FIG. 10 shows a schematic cross section through a multi-layer wiring carrier with a semiconductor chip on a continuous metal plate as a chip island, characters
  • 11 to 17 show schematic cross sections through intermediate products in the production of a multilayer circuit carrier with a semiconductor chip in each component position of the multilayer circuit carrier of a fifth embodiment of the invention
  • FIG. 11 shows a schematic cross section through a metal plate with through structures and with anchor plates on the through structures
  • Figure 12 shows a schematic cross section through a
  • FIG. 13 shows a schematic cross section through the metal plates of FIGS. 11 and 12 after the anchor plates have been joined
  • FIG. 14 shows a schematic cross section through the metal plates according to FIG. 13, which are joined over anchor plates, with filled cavities between the metal plates,
  • FIG. 15 shows a schematic cross section through a self-supporting multi-layer circuit carrier
  • FIG. 16 shows a schematic cross section through a self-supporting multilayer circuit carrier with applied external contact surfaces
  • Figure 17 shows a schematic cross section through a
  • Figure 18 shows a schematic cross section through a
  • FIG. 19 shows a schematic cross section through a further pair of two insulation layers with through structures
  • Figure 20 shows a schematic cross section through the
  • FIG. 21 shows a schematic cross section through a multilayer circuit carrier with a semiconductor chip
  • FIG. 22 shows a schematic cross section through an electronic component with a multilayer circuit carrier with a hollow housing and a semiconductor chip of a seventh embodiment of the invention
  • FIG. 23 shows a schematic cross section through an electronic component with a multilayer circuit carrier with a hollow housing and a semiconductor chip of an eighth embodiment of the invention
  • FIG. 24 shows a schematic cross section through an electronic component with a multilayer circuit carrier with one with a hollow housing and a semiconductor chip of a ninth embodiment of the invention
  • FIG. 25 shows a multilayer circuit carrier of a tenth embodiment of the invention
  • FIG. 26 shows a multilayer circuit carrier of an eleventh embodiment of the invention
  • FIG. 27 shows a multilayer circuit carrier of a twelfth embodiment of the invention
  • FIG. 28 shows a multilayer circuit carrier of a thirteenth embodiment of the invention
  • FIG. 1 shows a schematic cross section of an electronic component 28 with a multilayer circuit carrier 1 of a first embodiment of the invention.
  • the reference symbol 2 denotes a semiconductor chip and the reference symbol 4 denotes a rewiring structure which forms an uppermost layer of the multilayer circuit carrier 1 and is identified as a rewiring layer 5.
  • the reference numeral 6 denotes passage structures which, in this first embodiment of the invention, have different technologies are made.
  • the reference numeral 7 denotes an insulation layer with through structures 6, three insulation layers being stacked on top of one another in this first embodiment of the invention.
  • the reference symbol 8 denotes external contact surfaces which are arranged on the underside 9 of the multilayer circuit carrier 1.
  • these external contact surfaces 8 are covered with a layer which forms a flat external contact 10.
  • the reference numeral 11 denotes a plastic, which forms the non-conductive part of each insulation layer 7.
  • This plastic 11 can be a plastic filled with insulation particles, such as an epoxy resin, which is filled with correspondingly non-conductive oxide or carbide particles.
  • the reference numeral 12 denotes an anchoring layer which on the one hand has the plastic 11 and forms a special insulation layer, since the plastic 11 additionally has electrically conductive metallic anchor plates 13. These anchor plates 13 perform an electrical conduction function and additionally a mechanical anchoring function.
  • the reference numeral 14 denotes through contacts, which are present in all three insulation layers 7 in the first embodiment of the invention, the through contacts 14 only performing an additional function of mechanical anchoring in the anchoring position 12.
  • the reference numeral 15 denotes an electrically conductive filled plastic which, in this embodiment of the invention, forms the uppermost layer of the circuit carrier and thus the rewiring structure 4.
  • the through contacts 14 of the uppermost insulation layer can also be constructed from such an electrically conductive filled plastic.
  • the reference numeral 22 designates contact areas of the semiconductor chip 2 on its active upper side 38.
  • the reference numeral 24 designates contact balls which are arranged on the contact areas 22 and form flip chip external contacts 34.
  • Semiconductor chip 2 is embedded with its external contacts in a plastic housing compound 30.
  • This plastic housing compound 30 can have the same material as the plastic 11 of the insulation layers. Since, in this first embodiment of the invention, the rewiring structure 4 as the uppermost layer of the multilayer circuit carrier 1 is also made of plastic, but is filled with electrically conductive particles, the semiconductor chip 2 with its flip-chip external contacts 34 is completely surrounded by plastic.
  • This first embodiment of the invention is designed as a substrate layer 33 and thus has a greater thickness than the anchoring layers lying above it and the uppermost insulation layer 7.
  • This substrate layer can be designed as a self-supporting substrate and have a plurality of component positions arranged in columns and rows.
  • This substrate layer 33 is thus the prerequisite for applying additional layers for several components at the same time, such as the anchoring layer 12 with its anchoring plate 13 or the insulation layer above it with its plastic bushings 14, as well as the top layer, which in this first embodiment of the invention an electrical rically conductive rewiring structure and is covered by the plastic housing compound 30.
  • the substrate layer 33 is first built up as an insulation layer 7 with through contacts 14 on a continuous metal plate that is no longer present in FIG - Chen the metal plate for depositing such vias 14 is performed.
  • the anchoring layer 12 can be deposited with the anchor plates 13 made of metal in a structured manner on the upper sides of the through contacts 14. For this purpose, several procedures have already been specified in the introductory part.
  • the anchor plates 13 of the anchoring layer 12 are applied selectively using the printing technique.
  • a structured insulation layer 7 is then introduced, which leaves at least parts of the anchor plates free for the application of the through contacts 14 made of electrically conductive filled plastic 15.
  • a fourth layer of electrically conductive filled plastic 15, which represents the rewiring structure 4 and has conductor tracks 40, transition contacts 37 and contact connection surfaces 25, can be applied in a structured manner to these three insulation layers 7.
  • the semiconductor chip 2 can be applied to the contact pads 25 in each of the component positions 27, one of which is shown in cross section in this exemplary embodiment.
  • the grid dimension r of the external contact surfaces 8 and thus the external contact te 10 larger than the pitch R of the flip-chip external contacts 34.
  • the difference between the two is bridged by the conductor tracks 40 of the rewiring structure 4. This makes it possible to accommodate semiconductor chips 2 in the housing made of plastic housing mass 30, irrespective of the predetermined grid dimension r of the external contacts of the electronic component 28, which have a grid dimension R for their flip-chip outer contacts 34 which deviates from the predetermined grid dimension r.
  • FIG. 2 shows a schematic cross section of an electronic component 28 with a multilayer circuit carrier 1 of a second embodiment of the invention.
  • Components with the same functions as in FIG. 1 are identified by the same reference symbols and are not discussed separately.
  • the second embodiment of the invention it is assumed that there is a substrate layer 33 which only has vias 14, an anchor plate 13 being arranged above each vias 14 in order to secure the position of the vias 14 in the plastic 11.
  • the difference from the first embodiment of the invention is that not only three insulation layers 7 are arranged one above the other, but a total of seven insulation layers are arranged one above the other by the difference between the pitch R of the flip-chip external contacts 34 and the predetermined pitch r of the external contact surfaces to compensate for the substrate layer 33.
  • the through contacts 14 are applied to an already removed metal plate by means of chemical or galvanic deposition technology and thus have a metal
  • the further through contacts 14 in the overlying insulation layers 7 are made of an electrically conductive filled plastic 15.
  • a total of three rewiring structures 4 are embedded in three rewiring layers 5 arranged one above the other, the uppermost rewiring layer 5 being electrically connected to the flip chip external contacts 34 of the semiconductor chip 2, so that any pitch R of the flip External chip contacts 34 can transition into a predetermined grid dimension r of the external contact surfaces 8.
  • the remaining conductive structures can be produced by printing technology.
  • masks such as a screen printing mask or a stencil can be used or jet printing can be carried out, in which rewiring patterns are written in succession.
  • jet printing systems work according to the principle of the so-called ink jet printer, with the only difference that here instead of the ink, a liquid plastic filled with electrically conductive particles, in particular nanoparticles, is printed in the structure of a rewiring layer or in the structure of through contacts.
  • the plastics are subsequently cured, the low-viscosity binder can simultaneously escape from the printed rewiring structure and form a compact, electrically conductive rewiring structure.
  • FIG. 3 shows a schematic cross section of an electronic component 28 with a multilayer circuit carrier 1 of a third embodiment of the invention.
  • Components with the same functions as in the previous figures marked with the same reference numerals and not discussed separately.
  • the third embodiment of the invention differs from the first two embodiments of the invention in that a larger pitch R of the flip-chip external contacts 34 is to be reduced to a predetermined smaller pitch r for the external contact surfaces 8 with the aid of the multilayer circuit carrier.
  • a larger pitch R of the flip-chip external contacts 34 is to be reduced to a predetermined smaller pitch r for the external contact surfaces 8 with the aid of the multilayer circuit carrier.
  • the multi-layer circuit carrier 1 realizes with one and the same technology an insulation layer 7 with through contacts 14 in a predetermined grid dimension r and with the same technology a second insulation layer 7 with elongated Through contacts 14, the one
  • Rewiring structure 4 correspond, is provided. Another difference is that first an electronic component 28 with elongated through contacts 14 is realized, and then an insulation layer with through contacts 14 in a predetermined pitch r with a simultaneous slight enlargement of the housing and thus the plastic housing compound 30.
  • a complete electronic component 28 is thus arranged in the larger housing 41 made of plastic housing compound 30 at a component position 27 of a multilayer circuit carrier.
  • the connection between the elongated through contacts 14 and the through contacts 14 of the substrate layer 7 is realized by a conductive adhesive 42, the conductive adhesive 42 being able to be replaced by a soldered connection.
  • the entire multilayer circuit carrier thus comprises a buried semiconductor chip with external contacts of a first uppermost anchoring layer 12 with contact plates 13 and underneath an insulation layer 7 with elongated, continuous through contacts 14 and finally an electrically conductive adhesive layer which is connected to the anchor plates 13 of a second, lower-lying anchoring layer 12, these anchor plates 13 through contacts 14 in the lowermost insulation layer 7 of the electronic component 28 in Hold position.
  • FIG. 4 shows a schematic cross section of an electronic component 28 of a preliminary stage of the electronic component 28 according to FIG. 3.
  • Components with the same functions as in the previous figures are identified by the same reference symbols and are not discussed separately.
  • This electronic component 28 shown in FIG. 4 is also based on a multi-layer circuit carrier 1 with at least one insulation layer 7 with through structures 6, which are designed here as a rewiring structure 4.
  • this rewiring structure 4 in FIG. 4 is realized with through structures 6, that is to say the through structure is rewiring line 16 and via 14 at the same time.
  • the rewiring line 16 can either be designed as an elongated through contact 14 or considerably narrower than a through contact 14 for a substrate layer 33, since this rewiring line has no external contact. must have clocks. Only the start and size of the rewiring line, which is connected to the flip-chip external contacts 34 via an armature plate 13, can be adapted to the flip-chip external contacts of the semiconductor chip 2.
  • the second end of the continuous conductor track 16 can be widened to such an extent that it corresponds to the width of the through contacts 14 of the substrate layer 33 in FIG. 3.
  • the cross section of the continuous conductor track 16 shown here in FIG. 4 thus shows three regions which can have a different order of magnitude.
  • a first area of a contact pad 25 has a size of microscopic dimension of a few 10 ⁇ m 2 that is adapted to the flip chip external contact 34.
  • a second area has a macroscopic dimension for the transition contact 37, the order of magnitude of which corresponds to the external contact areas 8, which can have several 10000 ⁇ m 2 .
  • transition contact 37 and the contact connection area 25 there is a through structure in the form of a continuous conductor track 16, which can range in width from a few micrometers into the submicrometer range.
  • Such submicron widths for conductor tracks are represented with copper or nickel alloys, which can be galvanically deposited in appropriately prepared trenches.
  • FIGS. 5 to 10 show schematic cross sections through intermediate products in the production of a multilayer circuit carrier 1 with a semiconductor chip 2 in each component position 27 of the multilayer circuit carrier 1 of a fourth
  • FIG. 5 shows schematic cross sections through two self-supporting insulation layers 7 with through structures 6.
  • the lower insulation layer 7 shown in FIG. 5 has, in addition to a through-contact 14 with anchor plates 13 in the plastic 11, an elongated structure in cross section, which can either have a continuous metal plate 17, for example of rectangular or square cross section, or an elongated continuous conductor track 16.
  • continuous conductor track 16 it can be provided in a rewiring structure and as continuous metal plate 17 it can be designed as chip island 35.
  • Such continuous structures are created using the same technology with which through contacts 14 are produced in an insulation layer 7.
  • through structures 6 represent trenches filled with metal in an insulation mask.
  • Such an insulation mask can be deposited chemically or galvanically on a metal plate already removed in FIG. 5 by means of photolithography.
  • FIG. 6 shows schematic cross sections through two self-supporting insulation layers 7 with through structures 6 and attached anchor plates 13.
  • the lower insulation layer 7 with through contacts 14 in FIG. 6 corresponds to the upper insulation layer 7 in FIG. 5.
  • the insulation layer shown in FIG. 6 corresponds to that in FIG 5 insulation layer shown below and is arranged such that the anchor plates 13 now face each other in FIG. 6 and can be joined to one another by bringing the two insulation layers 7 together in the direction of arrow A.
  • the anchor plates 13 can have different materials which, when they are joined together, form low-melting solder connections.
  • the upper anchor plates 13 have a gold alloy
  • the lower anchor plates 13 have a tin alloy and both together form a low temperature eutectic solder joint.
  • FIG 7 shows the intermediate product of the next step, in which the two insulation layers shown in Figure 6 with
  • FIG. 7 shows a schematic cross section through a pair of joined insulation layers 7 with anchor plates 13 lying on top of one another. Between the two insulation layers, there is an intermediate space of thickness d between the joined anchor plates 13. This gap of 5 to a few 10 ⁇ m is filled with plastic 11 in the subsequent step.
  • FIG. 8 shows a schematic cross section through a pair of joined insulation layers 7 with a filled gap between the insulation layers 7.
  • Semasse 30 creates an anchoring layer 12, via which the two insulation layers are held together.
  • the lower insulation layer 7 forms a substrate layer 33 which has only through contacts 14, while the upper insulation layer 7 has through structures 6 which can have both through contacts 14 and continuous conductor tracks and / or a continuous circuit board 17.
  • This pair of two insulation layers 7 with anchoring layer 12 arranged therebetween is a self-supporting part or a self-supporting plate and thus forms a multi-layer circuit carrier 1 which, in addition to this simple structure, can have a large number of such component positions 27 which are arranged in rows and columns ,
  • FIG. 9 shows a schematic cross section through a pair of joined insulation layers 7 with applied external contact surfaces 8.
  • coatings which have bondable material and / or which have a material which form a low-melting eutectic, such as, for example, are applied to the upper insulation layer 7 Aluminum.
  • a continuous metal plate 19 is introduced or chemically or galvanically deposited into the upper insulation layer 7, which is dimensioned such that it can accommodate a semiconductor chip and thus realizes a chip island 35.
  • FIG. 10 shows a schematic cross section through a multi-layer circuit carrier 1 with semiconductor chips 2 on a continuous metal plate 17 as chip island 35 and a via 14 which electrically connects the bond wire 36 to the underside 9 of the circuit board through both insulation layers.
  • Carrier connects so that an electrical connection between the external contact surface 8 and contact surface 22 is made on the semiconductor chip 2.
  • FIGS. 11 to 17 show schematic cross sections through intermediate products in the production of a multilayer circuit carrier 1 with a semiconductor chip 2 in each component position 27 of the multilayer circuit carrier 1 of a fifth embodiment of the invention.
  • Components with the same functions as in the previous figures are identified by the same reference numerals and are not discussed separately in FIGS. 11 to 17.
  • FIG. 11 shows a schematic cross section through a metal plate 29 with through structures 6 and with armature plates 13 on the through structures 6.
  • this production method for producing a multilayer circuit carrier initially no self-supporting insulation layer with through structures 6 is produced, but rather that between the metallic through structures 6 lying photoresist completely removed.
  • FIG. 11 again shows a through contact 14 and a continuous metal plate 17 as through structures 6.
  • FIG. 12 shows a schematic cross section through a metal plate 29 with through contacts 14 and with anchor plates 13 on the through contacts 14.
  • the photoresist layers that initially existed between the through contacts 14 in order to galvanically or through the through contacts 14 on the exposed surfaces to be deposited chemically, not replaced by plastic housing compound, but rather as a supporting layer, the metal plate 29 is initially retained in order to leave the through contacts 14 in position. Then you can the metal plates 29 are adjusted towards one another in the direction of arrow A, the anchor plates 13 of the two structures of FIGS. 11 and 12 coming to lie on one another.
  • FIG. 13 shows a schematic cross section through the metal plates 29 from FIG. 11 and FIG. 12 after the armature plates 13 have been joined together. Since the metal plates remain throughout and are provided for a plurality of circuit positions 27 for producing a multilayer circuit carrier 1, the method can be used in this implementation Production of a multilayer circuit carrier, the two metal plates 29 serve as a shape limitation. The spaces to be filled with plastic housing compound are now substantially larger than in FIG. 7. In addition, no plastic can penetrate the external contact surfaces 8 of the through structures 6, since these are still connected to the metal plates 29. Potting the gaps with plastic housing compound is made easier due to the larger gaps.
  • Figure 14 shows a schematic cross section through the joined metal plates 29 according to Figure 13 with filled cavities between the metal plates 29.
  • the metal plates 29 can be supported by appropriate moldings so that they do not bulge when the plastic with a high pressure to to 15 MPa in the
  • this assembled multilayer composite now provides a self-supporting structure Body or a self-supporting plate, which no longer has to be supported by the metal plates 29.
  • FIG. 15 shows a schematic cross section through a self-supporting multi-layer circuit carrier 1, the metal plates 29 still present in FIG. 14 being removed by means of wet chemical etching.
  • This removal of the metal plates 29 is supported by the fact that the through structures 6 are produced from nickel or a nickel alloy, while the metal plates 29 consist of a copper alloy.
  • the copper etching thus stops at the interface with the nickel, so that a defined metal surface of the through contacts 14 or the through structures 6 is present on the surfaces of the self-supporting plate-shaped body which is now shown in FIG. External contacts or bondable metals can be applied to these metal surfaces.
  • FIG. 16 shows a schematic cross section through a self-supporting multilayer circuit carrier 1 with applied external contact surfaces 8. These external contact surfaces 8 are only attached to the underside 9 of the multilayer circuit carrier 1, while bondable materials are applied to the through structures 6 on the upper side of the circuit carrier 1.
  • This material can also be a conductive adhesive for fastening the semiconductor chip on the continuous metal plate 17 formed there as chip island 35.
  • FIG. 17 shows a cross section through a component position 27 of a multilayer circuit carrier 1 with a semiconductor chip 2 applied.
  • the passive rear side 39 of a semiconductor chip 2 with a chip is placed on the continuous metal plate 17 Conductive adhesive 42 applied.
  • the passive rear side 39 of the semiconductor chip 2 is thus electrically connected to the external contact 8 via the conductive adhesive 42, the chip island 35, the two anchor plates 13 and the through contact 14.
  • the passive rear side 39 of the semiconductor chip 2 can thus be placed at the lowest potential of the integrated circuit with respect to the active upper side 38 of the semiconductor chip 2.
  • the electrodes of the active components of the integrated circuit on the upper side 38 of the semiconductor chip 2 are placed over the contact areas 22 and the bond connections 36 in this fifth exemplary embodiment of the invention on the stacked via 14, which is electrically connected to a further external contact 8 via the two armature plates 13 is.
  • signal pulses can be applied to the contact surface 22 of the active top side 38 of the semiconductor chip 2 via this external contact and the through contacts 14 as well as the armature plates 13 and the bond connections 36.
  • FIGS. 18 to 21 show schematic cross sections through intermediate products in the production of a panel 26 with a semiconductor chip 2 in each component position on the basis of a multilayer circuit carrier 1 of a sixth embodiment of the invention.
  • Components with the same functions as in the previous figures are identified by the same reference numerals and are not specifically discussed for FIGS. 18 to 21.
  • FIG. 18 shows a schematic cross section through a pair of insulation layers 7 with through structures 6. This pair of insulation layers 7 corresponds to the pair of insulation layers 16, but the chip island has been significantly enlarged.
  • FIG. 19 shows a schematic cross section through a further pair of two insulation layers 7 with through structures 6 which correspond to the pair of insulation layers 7 in FIG. 16.
  • FIG. 20 shows a schematic cross section through the pairs of FIGS. 18 and 19 after the two pairs have been joined in the direction of arrow A, the external contacts 8 of the one pair being joined to the uppermost contacts of the second pair of FIG. 19.
  • a further structure which is also referred to as benefit 26, is created from four multilayer circuit carriers produced using the same technology, especially if the detail shown in FIG. In principle, any number of pairs of insulation layers with through structures can be stacked on top of one another in the same way, the
  • Passage structures can serve not only as a chip island, but also as continuous conductor tracks 16.
  • the continuous conductor track 16 can expand on both sides to form transition contacts 37 and in contact with correspondingly large through contacts at both ends of the continuous conductor track 16 stand.
  • FIG. 21 shows a schematic cross section through a multilayer circuit carrier 1 with a semiconductor chip 2, which forms part of a panel 26. Since each of the pair of insulation plates with multiple through contacts 14 is self-supporting, if the dielectric strength permits and the air humidity cannot be shielded, the intermediate space with the thickness d between the insulation layers arranged in pairs remain unfilled. If, however, higher demands are placed on the dielectric strength, this gap of thickness d must also be filled with the appropriate insulating plastic material.
  • the semiconductor chip 2 can be covered with a further hollow housing layer, so that the multilayer circuit carrier 1 has a semiconductor chip 2 installed in a hollow housing.
  • FIG. 22 shows a schematic cross section through an electronic component 28 with a multilayer circuit carrier 1 with a hollow housing 18 and with a semiconductor chip 2 according to a seventh embodiment of the invention.
  • Components with the same functions as in the previous figures are identified by the same reference symbols and are not discussed separately.
  • the multilayer circuit carrier 1 of FIG. 22 is realized by joining together a substrate carrier with a through structure 6, which in addition to the through contacts 14 also has a continuous metal plate 17 which is designed as a chip island 35. Both the position of the chip island 35 and the position of the through contacts 14 are predefined with a grid dimension r.
  • a second insulation layer 7 through contacts 14 is formed such that there is a recess 19 which can serve as a hollow housing 18 for the electronic component 28.
  • both a lower insulation layer 7 with through structures 6 and an upper insulation layer 7 with through structures 6 and recesses 19 are joined together via the armature plates 13, which results in a multilayer circuit carrier 1 with buried semiconductor chips 2.
  • FIG. 23 shows a schematic cross section through an electronic component 28 with a multilayer circuit carrier 1 with a hollow housing 18 and a semiconductor chip 2 of an eighth embodiment of the invention.
  • Components with the same functions as in the previous figures are identified by the same reference symbols and are not discussed separately.
  • FIG. 23 a further insulation layer 7 is applied to the multi-layer circuit carrier 1 of FIG. 22, which has a continuous, large-area metal plate 17 which is connected at its edges via contacts 14 to external contact surfaces 8 on the underside 9 of the multi-layer circuit carrier 1.
  • This construction completely shields the semiconductor chip 2 in its hollow housing 18, so that this multilayer circuit carrier can be used for sensitive high-frequency components 28.
  • FIG. 24 shows a schematic cross section through an electronic component 28 with a multilayer circuit carrier 1 with a hollow housing 18 and a semiconductor chip 2 of a ninth embodiment of the invention.
  • Components with the same functions as in the previous figures are identified by the same reference symbols and are not discussed separately.
  • This ninth embodiment of the invention differs from the previous embodiments of the invention in that the hollow housing 18 is not made from a plastic housing compound 30, as in FIGS. 22 and 23, but from a transparent plastic 20.
  • This transparent plastic 20 a through-contact 14 can be routed to ensure that signals and supply voltages can also be to supply the top of the multilayer circuit carrier 1.
  • the transparent plastic 20, which forms the hollow housing 18, is formed above the semiconductor chip 2 as a detector lens 21 in order to achieve a higher detector efficiency or a higher sensitivity to light.
  • FIG. 25 shows a multilayer circuit carrier 1 of a tenth embodiment of the invention.
  • Components with the same functions as in the previous figures are identified by the same reference symbols and are not discussed separately.
  • a flat lead frame with a chip island 35 and flat conductors 43 are connected to a semiconductor chip 2, in which neither the size of the semiconductor chip 2 is compatible with the size of the chip island 35 of the flat lead frame, nor the pitch of the flat conductors the pitch of the Contact surfaces 22 of the semiconductor chip 2 is adapted.
  • a multilayer circuit carrier 1 can be used in order to adapt the orders of magnitude to one another at reasonable costs.
  • a lower insulation layer 7 is provided with a continuous metal plate 17, the area and distance of which from a via 14 corresponds to the area of the chip island 35 of the lead frame and the distance of this island to the lead 43.
  • a corresponding via 14 which has a bondable coating and is electrically connected to the contact areas via a bond connection, is connected via the underlying contact 14 of the underlying I- solationslage 7 and connected via the outer contact surface 8 with the flat conductor 43 of the flat lead frame.
  • FIG. 26 shows a multilayer circuit carrier 1 of an eleventh embodiment of the invention. Components with the same functions as in the previous figures are identified by the same reference symbols and are not discussed separately.
  • a large chip island 35 of a flat conductor frame which is arranged at a very short distance from a flat conductor 23, can be equipped with two substantially smaller semiconductor chips 2.
  • two insulation layers 7 are stacked one above the other and connected to one another via the anchor plates 13, so that any structure can be realized with the upper insulation layer, regardless of the size and arrangement of the chip island 35 of the flat conductor frame and the flat conductor 43 ,
  • FIG. 27 shows a multilayer circuit carrier 1 of a twelfth embodiment of the invention.
  • Components with the same functions as in the previous figures are identified by the same reference symbols and are not discussed separately.
  • a semiconductor chip 2 is arranged on a plurality of flat conductors 43, which are arranged in a predetermined pitch r, which has a contact area 22 with a connection to at least one of the flat conductors 43 and its passive rear side 39 with another of the flat conductors 43 electrically connected is.
  • This embodiment of the invention according to FIG. 27 also shows the possibility of realizing any through structures with the multilayer circuit carrier 1 according to the invention on the second insulation layer, so that different semiconductor chips 2 with a completely independent, flat distribution to predetermined flat conductors 43 of a flat conductor frame with a predetermined grid dimension r can be connected.
  • FIG. 28 shows a multilayer circuit carrier 1 of a thirteenth embodiment of the invention. Components with the same functions as in the previous figures are identified by the same reference symbols and are not discussed separately.
  • This thirteenth embodiment according to FIG. 28 differs from the previous embodiments in that the multilayer circuit carrier 1 has passive components 3 which, with their electrodes 44 and any distance between the electrodes 44, on a lead frame
  • a multilayer circuit carrier 1 is again provided with at least two insulation layers 7 with through structures 6, which make it possible for the discrete components 3 with their electrodes 44 of any dimension to be electrically connected to the outer flat conductors 43 of a flat conductor frame with a predetermined grid dimension r.
  • the multilayer circuit carrier 1 according to the invention is the construction of an entire module from discrete components and / or semiconductor chips and the adaptation of these structures with their corresponding electrodes 44 or their contact surfaces 22 to predetermined grid dimensions, be it the grid dimensions r of external contact surfaces 8 or, as shown in the examples in FIGS. 25 to 28, the raster dimensions r of flat conductors 43,

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

La présente invention concerne un support (1) de circuit à plusieurs couches, ainsi que des composants électroniques (28) et une plaquette (26) qui comportent des supports (1) de circuit à plusieurs couches de ce type. La présente invention concerne en outre un procédé de fabrication d'un support (1) à plusieurs couches de ce type. Ledit support (1) de circuit à plusieurs couches comporte au moins une puce (2) à semi-conducteur ainsi qu'au moins une couche intermédiaire (5) possédant une structure (4) de couche intermédiaire. Ledit support (1) de circuit à plusieurs couches comporte en outre au moins une couche d'isolation (7) pourvue de structures traversantes (6).
EP03783945A 2002-08-01 2003-07-31 Support de circuit a plusieurs couches et fabrication dudit support Withdrawn EP1532681A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10235332A DE10235332A1 (de) 2002-08-01 2002-08-01 Mehrlagiger Schaltungsträger und Herstellung desselben
DE10235332 2002-08-01
PCT/DE2003/002575 WO2004015770A1 (fr) 2002-08-01 2003-07-31 Support de circuit a plusieurs couches et fabrication dudit support

Publications (1)

Publication Number Publication Date
EP1532681A1 true EP1532681A1 (fr) 2005-05-25

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EP03783945A Withdrawn EP1532681A1 (fr) 2002-08-01 2003-07-31 Support de circuit a plusieurs couches et fabrication dudit support

Country Status (4)

Country Link
US (1) US7221048B2 (fr)
EP (1) EP1532681A1 (fr)
DE (1) DE10235332A1 (fr)
WO (1) WO2004015770A1 (fr)

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US20050151246A1 (en) 2005-07-14
US7221048B2 (en) 2007-05-22
WO2004015770A1 (fr) 2004-02-19
DE10235332A1 (de) 2004-02-19

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