JP2005530358A - マイクロチップデバイスのパッケージング - Google Patents
マイクロチップデバイスのパッケージング Download PDFInfo
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- JP2005530358A JP2005530358A JP2004515340A JP2004515340A JP2005530358A JP 2005530358 A JP2005530358 A JP 2005530358A JP 2004515340 A JP2004515340 A JP 2004515340A JP 2004515340 A JP2004515340 A JP 2004515340A JP 2005530358 A JP2005530358 A JP 2005530358A
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- interposer
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- microchip device
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- insulating material
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 22
- 238000000926 separation method Methods 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 21
- 239000004020 conductor Substances 0.000 claims description 24
- 238000001721 transfer moulding Methods 0.000 claims description 24
- 239000011810 insulating material Substances 0.000 claims description 19
- 239000012777 electrically insulating material Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 abstract description 40
- 238000013461 design Methods 0.000 description 16
- 239000011347 resin Substances 0.000 description 7
- 229920005989 resin Polymers 0.000 description 7
- 230000002093 peripheral effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
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- 238000000429 assembly Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
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- 238000010586 diagram Methods 0.000 description 1
- 238000010017 direct printing Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000011232 storage material Substances 0.000 description 1
- 230000007847 structural defect Effects 0.000 description 1
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- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
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- B29C45/14655—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components connected to or mounted on a carrier, e.g. lead frame
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Abstract
マイクロチップデバイスと、パッケージング用インターポーザーと、実装マイクロチップデバイスとのパッケージング方法。インターポーザー(7)は、マイクロチップデバイス(1)上に配置される。インターポーザー(7)は、外部電気接点(9)が配置されるインターポーザーの表面から、マイクロチップデバイス(1)の表面にまで延びるアパーチャ(11)を備えている。マイクロチップデバイス(1)の表面上の電気接点(3)と、インターポーザー(7)の外部電気接点(9)とを電気的に接続するために、電気接点(3)がアパーチャ(11)を通じてアクセス可能である。インターポーザー(7)は、特に外部電気接点(9)の位置するインターポーザー表面からインターポーザー(7)の内部にまで延びるブリッジ(19)によって分割された、分離開口またはアパーチャ領域を有している。これによって、完成パッケージの取扱いが容易になり、アパーチャ(11)を充填材料で満足に充填可能になる。
Description
特にアパーチャの端部がマイクロチップデバイスの表面にある接点に近接して配置される場合には、マイクロチップの表面上の電気接点と、外部接点とを接続する導体の長さを非常に短く保つことができる。
このようにして、部品配置を非常にコンパクトに構成できる。
パッケージの外部接点を基板の接点と直結可能である。さらに、周囲環境への熱放散が最大限に行われるように、マイクロチップデバイスがパッケージの反対側の表面上に配置されるか、または反対側表面に近接して配置される。
本発明の別の目的は、トランスファー成形の加工中及び加工後におけるインターポーザー及びマイクロチップデバイスの取扱いを容易にすることにある。
第1電気接点を有するマイクロチップデバイスを提供し、
第2電気接点と、外側から貫通して延びるアパーチャと、外側から内側へ開けられた分離開口とを備えたインターポーザーを提供し、
外側からアパーチャを通じて第1電気接点にアクセス可能なように、インターポーザーをマイクロチップデバイスの近隣に配置し、
第1電気接点を第2電気接点に電気的に接続し、
電気絶縁材料をトランスファー成形によってアパーチャに充填し、
絶縁材料を、アパーチャに到達する前に分離開口の領域を通過する方向から供給することで構成される方法。
通路の終端位置に隣接する分離開口もまた、アパーチャまたはキャビティが完全に充填されるのに役立っている。分離開口は貯蔵場所として働き、そこに流入した材料が、後から注入された材料を偏向させるというのが、その1つの説明である。このように、後から注入された材料の流速は、通路の終端位置で減少し、その領域での材料の蓄積が促進される。
複数の第1電気接点を有するマイクロチップデバイスを提供し、
外側に複数の第2電気接点と、外側から貫通して延びるアパーチャとを備え、前記アパーチャは、アパーチャの対向する両端部を接続するブリッジによって、少なくとも2つの開口に分割されるインターポーザーを提供し、
外側から少なくとも最初の開口を通じて第1電気接点にアクセス可能なように、インターポーザーをマイクロチップデバイスの近隣に配置し、
複数の第1電気接点及び第2電気接点の中から、対応する各々1個の接点を互いに電気的に接続する工程。
本発明によると、マイクロチップデバイスのパッケージング用に以下のインターポーザーを提供することがさらに提案されている。
外側からインターポーザーの内部にまで延び、少なくとも2つの開口に分割されるアパーチャとから成り、
少なくとも最初の開口は、マイクロチップデバイスヘの接続を可能にするように、外側から前記インターポーザーを貫通して延びる、インターポーザー。
トランスファー成形加工中に電気絶縁材料を通過させる通路を形成するように、直列に整列された複数のアパーチャを備えるのがさらに望ましい。2つのアパーチャの間に、通路に沿って、外側からインターポーザーの内側にまで延びる開口を配置してもよい。
複数の第1電気接点を備えたマイクロチップデバイスと、
複数の第2電気接点と、外部からインターポーザーを貫通して延びるアパーチャと、外側からインターポーザーの内部にまで延びる分離開口とを備えたインターポーザーと、
第1電気接点と、対応する第2電気接点とを電気的に接続する導電体とを備え、
インターポーザーは、マイクロチップデバイスに付着され、
少なくとも1つの導電体はアパーチャ内にまで延び、
アパーチャ及び分離開口は、少なくとも部分的に電気絶縁材料で充填され、それによって、少なくとも1つの導電体はインターポーザーに固定される、実装マイクロチップデバイス。
図4に、複数のマイクロチップデバイス1を同時または並列に1回の加工でパッケージング可能であるように、複数のマイクロチップデバイス1に隣接して配置されたインターポーザー7の透視図を示している。図4の配置は、点線のパッケージ輪郭8によって示されるように、パッケージングされる少なくとも9個のマイクロチップデバイス1を備えている。この配置のプロファイルを示すために、配置の右側の一部が切り取られている。
Claims (11)
- 第1電気接点(3)を有するマイクロチップデバイス(1)を用意し、
第2電気接点(9)と、外側から貫通して延びるアパーチャ(11)と、外側から内側へ延びる分離開口(16,17)とを備えたインターポーザー(7)を用意し、
外側からアパーチャ(11)を通じて第1電気接点(3)にアクセス可能なように、 インターポーザー(7)をマイクロチップデバイス(1)の近隣に配置し、
第1電気接点(3)を第2電気接点(9)に電気的に接続し、
アパーチャ(11)をトランスファー成形によって電気絶縁材料(25)で充填し、
絶縁材料(25)を、アパーチャ(11)に到達する前に分離開口(16,17)の領域を通過する方向から供給する過程を有する、
マイクロチップデバイス(1)のパッケージング方法。 - 第1及び第2接点(3,9)を電気的に接続する電気接続(5)を備え、電気接続(5)は、マイクロチップデバイス(1)からアパーチャ(11)を通って、インターポーザー(7)の外側のアパーチャ(11)の外側にまでさらに延びており、電気接続(5)は、トランスファー成形によって少なくともアパーチャ(11)の外側で絶縁材料(25)にカプセル封じされる、請求項1に記載の方法。
- 電気絶縁材料は、インターポーザー(7)またはマイクロチップデバイス(1)、あるいはその両方の少なくとも一部をカプセル封じするために、インターポーザー(7)またはマイクロチップデバイス(1)、あるいはその両方の外面にまで供給され、分離開口(16,17)は、トランスファー成形中に絶縁材料(25)がアパーチャ(11)に到達する前に前記外面に沿って流れるよう、寸法決め及び配置決めされている、請求項1または請求項2に記載の方法。
- 電気絶縁材料(25)で充填される複数の分離アパーチャ(11)が存在し、アパーチャ(11)は、トランスファー成形中に電気絶縁材料の通過する通路を形成するよう直列に整列され、さらなる分離開口(16)は、前記通路に沿って2個のアパーチャ(11)の間に配置される、請求項1から請求項3のいずれかに記載の方法。
- アパーチャ(11)は、絶縁材料(25)をアパーチャ(11)の内部にまで、または内部を通過して供給するよう、インターポーザー(7)の外側に沿って延びる少なくとも1本の通路を形成し、分離開口(17)は、前記通路の開始位置に隣接して配置される、請求項1から請求項4のいずれかに記載の方法。
- 前記通路、または前記複数の通路の1本の開始位置または終端位置に各々隣接して配置された、複数の分離開口(17)が存在する、請求項5に記載の方法。
- 実装マイクロチップデバイスと電気的に接触し、マイクロチップデバイス(1)に電気的に接続されるインターポーザー(7)の外側に配置された複数の電気接点(9)と、
外側からインターポーザー(7)の内部にまで延び、少なくとも2つの開口(15,16,17)に分割されるアパーチャ(11)とから成り、
少なくとも最初の開口は、マイクロチップデバイス(1)ヘの接続を可能にするように、外側から前記インターポーザー(7)を貫通して延びる、
マイクロチップデバイス(1)のパッケージング用インターポーザー。 - アパーチャ(11)は、アパーチャの対向する端部(13)を互いに接続するブリッジ(18)によって分割されている、請求項7に記載のインターポーザー。
- 複数のアパーチャ(11)を備え、アパーチャ(11)は、トランスファー成形加工中に電気絶縁材料を通過させる通路を形成するように直列に整列されている、請求項7または請求項8に記載のインターポーザー。
- 通路に沿って、2つのアパーチャ(11)の間に配置され、インターポーザー(7)の外側から内側にまで延びる開口(16)をさらに備えている、請求項9に記載のインターポーザー。
- 複数の第1電気接点(3)を備えたマイクロチップデバイス(1)と、
複数の第2電気接点(9)と、外部からインターポーザー(7)を貫通して延びるアパーチャ(11)と、外側からインターポーザー(7)の内部にまで延びる分離開口(16,17)とを備えたインターポーザー(7)と、
第1電気接点(3)と、対応する第2電気接点(9)とを電気的に接続する導電体(5)とを備え、
インターポーザー(7)は、マイクロチップデバイス(1)に付着され、
少なくとも1つの導電体(5)はアパーチャ(11)内にまで延び、
アパーチャ(11)及び分離開口(16,17)は、少なくとも部分的に電気絶縁材料(25)で充填され、それによって、少なくとも1つの導電体(5)はインターポーザー(7)に固定される、
実装マイクロチップデバイス。
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PCT/SG2002/000124 WO2004001838A1 (en) | 2002-06-19 | 2002-06-19 | Packaging of a microchip device-i |
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US7504715B2 (en) | 2009-03-17 |
US7129115B2 (en) | 2006-10-31 |
US20070013040A1 (en) | 2007-01-18 |
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US20040121511A1 (en) | 2004-06-24 |
DE10297755T5 (de) | 2005-09-01 |
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