EP1374257A1 - Verfahren zum herstellen von dünnschicht-chipwiderständen - Google Patents
Verfahren zum herstellen von dünnschicht-chipwiderständenInfo
- Publication number
- EP1374257A1 EP1374257A1 EP02700251A EP02700251A EP1374257A1 EP 1374257 A1 EP1374257 A1 EP 1374257A1 EP 02700251 A EP02700251 A EP 02700251A EP 02700251 A EP02700251 A EP 02700251A EP 1374257 A1 EP1374257 A1 EP 1374257A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- resistance
- laser
- thin
- substrate
- structuring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/003—Apparatus or processes specially adapted for manufacturing resistors using lithography, e.g. photolithography
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/006—Apparatus or processes specially adapted for manufacturing resistors adapted for manufacturing resistor chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/22—Apparatus or processes specially adapted for manufacturing resistors adapted for trimming
- H01C17/24—Apparatus or processes specially adapted for manufacturing resistors adapted for trimming by removing or adding resistive material
- H01C17/242—Apparatus or processes specially adapted for manufacturing resistors adapted for trimming by removing or adding resistive material by laser
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S430/00—Radiation imagery chemistry: process, composition, or product thereof
- Y10S430/146—Laser beam
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/94—Laser ablative material removal
Definitions
- the present invention relates to the field of manufacturing passive electronic components. It relates to a method for producing thin-film chip resistors in accordance with the preamble of claim 1.
- a method for producing a laser structuring of conductor tracks is known from DE-C1-38 43 230.
- the direct structuring of metal films on plastic for printed circuit boards is proposed.
- the object is achieved by the entirety of the features of claim 1.
- the essence of the invention is to use a direct laser exposure process for structuring the resistance tracks for the individual resistors, in which a complete wi the resistor or several complete resistors can be structured with a single exposure that extends over the entire area of the resistors (a “laser shot”) through an appropriately structured mask.
- chip components can be produced even more quickly and therefore more cost-effectively with the invention, because the structuring is not carried out in writing by a focused laser beam, but rather as direct exposure of an entire or even of several whole components with one or several laser shots.
- a preferred embodiment of the method according to the invention is characterized in that a UV laser (e.g. excimer laser) with wavelengths of 150 nm to 400 nm is used for the laser lithographic direct exposure, in the beam path of which one of the structure of the resistance tracks to be formed appropriate mask is inserted, and that in the present case an excimer laser emits laser radiation with wavelengths in the range between 248 nm to 351 nm. With sufficient energy at the exposed areas, the laser radiation removes the metallic thin layer of the resistance layer directly or converts it into a non-conductive oxide.
- a UV laser e.g. excimer laser
- a substrate is used which is divided into individual areas by structuring means, preferably notches, but also laser scratches, that a thin-film chip resistor is generated in each area, that the structuring means comprises a plurality of mutually perpendicular Lattice denden- notches in the surface of the substrate, and that after the completion of the individual thin-film chip resistors, the substrate along the notches is divided into individual thin-film chip resistors.
- the structuring for example laser cuts, can also take place in the production process, ie after the thin layers have been applied.
- Another preferred embodiment of the method according to the invention is characterized in that prior to the structuring of the resistance layer in the individual resistance tracks for each of the thin-film chip resistors to be produced, local contact layers are applied as islands or as continuous strips to the resistance layer in the end regions of the resistance tracks to be produced.
- Thin-film technology e.g. masked vapor deposition
- Thick film processes are also conceivable, as well as combinations of the two. The order of the manufacturing processes (resistance layer, contact layer) can also be reversed.
- Figure 1 is a perspective, partially sectioned view of a pre-notched, laser-scored or sawn substrate, as is preferably used in the manufacturing method according to the invention.
- Fig. 2- ⁇ different steps for the production of thin-film
- Chip resistors according to a preferred embodiment of the invention, in particular
- FIG. 2 shows the substrate from FIG. 1 in longitudinal section
- FIG. 3 shows the substrate from FIG. 2 with a resistance layer applied over the entire surface
- Fig. 4 shows the coated substrate of Fig. 3 with on the top
- Fig. 5 shows the laser lithographic direct exposure process for
- FIG. 7 shows the substrate with an exemplary finished structured chip resistor in a representation comparable to FIG. 1;
- the substrate 10 consists for example of a glass, silicon, SiO or an insulating ceramic such as Al 2 O 3 or AIN. It is divided into individual areas 13 on the top by notches 11, 12 running perpendicular to one another in the manner of a grid, in which because a thin film chip resistor is to be generated. However, the substrate 10 can also be sawn or laser scratched or can be present without subdivision. Depending on the subdivision, resistance arrays or resistance networks can also be created.
- a resistance layer 14 is first applied to the substrate 10, which is shown again in longitudinal section in FIG. 2, according to FIG. 3, preferably over the entire surface.
- the resistance layer 14 is usually a metal layer made of a suitable resistance alloy such as e.g. CrNi, CrSi, TaN, CuNi.
- the resistance layer is preferably applied by sputtering or vapor deposition. Germination e.g. Pd for subsequent metallizations are conceivable. It is also conceivable to carry out a masked coating instead of the entire surface coating, for example in order to produce resistance layers which are electrically separated from one another in adjacent regions 13. Several layers of resistance on top of each other are also conceivable.
- local contact layers 15, 16 or 17 are subsequently formed on the resistance layer 14 or on the top side of the substrate 10 and optionally on the bottom side, as shown in FIG. 18 applied.
- a pair of spaced-apart contact layers 15, 16 is used, between which the resistance path (24 in FIG. 7) to be subsequently structured extends.
- the contact areas 17, 18 on the underside are later electrically connected to the corresponding contact areas 15, 16 on the top side and serve as contacts of the chip resistors used as SMD components.
- the contact areas 17, 18 can also be continuous, as indicated at 17 in FIG. 4.
- the contact layers 15, 16 are preferably applied using the thin-film method and the contact layers 17, 18 using the thick-film technique.
- the order of manufacture is preferably carried out in such a way that the contact layer is applied to the resistance layer, that is to say in a subsequent process step.
- the contact layer under the resistance layer ie in a previous process step.
- the lower contact layer 17, 18 can be applied as a first process step.
- a masked laser radiation 21 is generated from a flat laser radiation 20 with a beam cross-section of up to 20 ⁇ 30 mm 2 through a suitably structured mask 19, which is optically imaged on a surface that is at least as large as the surface of the resistance path to be structured ( 25), meets the resistance layer 14.
- the mask 19 has mask openings 21 in the areas in which the material of the resistance layer 14 is removed or brought into a non-conductive state by oxidation.
- the resistance tracks of a resistor or a plurality of adjacent resistors in the example in FIG.
- these are two) are structured in a non-writing process by means of a single or several “laser shots” in an image field having a size of up to several mm 2 .
- the mask 19 is designed in such a way that the resistance layer 14 is also exposed in the area of the notches 11, 12, so that when there is a full-area resistance layer 14, the individual areas 13 are electrically isolated at the same time.
- the result of the structuring is a thin-film chip resistor 100, as is shown by way of example for one of the regions 13 in FIG. 7.
- the accuracy of the resistance value necessary fine adjustment which is carried out according to FIG. 6 preferably by processing the resistance track by means of a (writing) laser beam 23 in conventional technology.
- the various thin-film chip resistors 100 ′, 100 ′′ can be separated by breaking the substrate 10 along separation lines 28 predetermined by the notches 11, 12. Depending on the shape of the separation lines, it is also possible to produce connected resistance arrays or resistance networks.
- the invention can be used to produce thin-film chip resistors with the advantages of a lithographic technique in an extremely cost-effective manner, the structuring, including the electrical insulation of the individual elements, not being carried out in writing by a focused laser beam, but rather as direct exposure of a whole or even several whole components with one Laser shot, and in contrast to photolithography in one process step.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Plasma & Fusion (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Non-Adjustable Resistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10110179A DE10110179B4 (de) | 2001-03-02 | 2001-03-02 | Verfahren zum Herstellen von Dünnschicht-Chipwiderständen |
DE10110179 | 2001-03-02 | ||
PCT/EP2002/001730 WO2002071419A1 (de) | 2001-03-02 | 2002-02-19 | Verfahren zum herstellen von dünnschicht-chipwiderständen |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1374257A1 true EP1374257A1 (de) | 2004-01-02 |
EP1374257B1 EP1374257B1 (de) | 2004-09-15 |
Family
ID=7676132
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP02700251A Expired - Lifetime EP1374257B1 (de) | 2001-03-02 | 2002-02-19 | Verfahren zum herstellen von dünnschicht-chipwiderständen |
Country Status (9)
Country | Link |
---|---|
US (1) | US6998220B2 (de) |
EP (1) | EP1374257B1 (de) |
JP (1) | JP4092209B2 (de) |
KR (1) | KR100668185B1 (de) |
CN (1) | CN100413000C (de) |
AT (1) | ATE276575T1 (de) |
DE (2) | DE10110179B4 (de) |
TW (1) | TW594802B (de) |
WO (1) | WO2002071419A1 (de) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10110179B4 (de) | 2001-03-02 | 2004-10-14 | BCcomponents Holding B.V. | Verfahren zum Herstellen von Dünnschicht-Chipwiderständen |
US7378337B2 (en) * | 2003-11-04 | 2008-05-27 | Electro Scientific Industries, Inc. | Laser-based termination of miniature passive electronic components |
TW200534296A (en) * | 2004-02-09 | 2005-10-16 | Rohm Co Ltd | Method of making thin-film chip resistor |
JP2011187985A (ja) * | 2004-03-31 | 2011-09-22 | Mitsubishi Materials Corp | チップ抵抗器の製造方法 |
US7882621B2 (en) * | 2008-02-29 | 2011-02-08 | Yageo Corporation | Method for making chip resistor components |
CN102176356A (zh) * | 2011-03-01 | 2011-09-07 | 西安天衡计量仪表有限公司 | 一种铂电阻芯片及铂电阻芯片的制备方法 |
DE102018115205A1 (de) * | 2018-06-25 | 2020-01-02 | Vishay Electronic Gmbh | Verfahren zur Herstellung einer Vielzahl von Widerstandsbaueinheiten |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1765145C3 (de) * | 1968-04-09 | 1973-11-29 | Siemens Ag, 1000 Berlin U. 8000 Muenchen | Verfahren zum Bearbeiten dunner Schichten von elektrischen Schalt kreisen mit Laserstrahlen |
US3699649A (en) * | 1969-11-05 | 1972-10-24 | Donald A Mcwilliams | Method of and apparatus for regulating the resistance of film resistors |
US4468414A (en) * | 1983-07-29 | 1984-08-28 | Harris Corporation | Dielectric isolation fabrication for laser trimming |
US4594265A (en) * | 1984-05-15 | 1986-06-10 | Harris Corporation | Laser trimming of resistors over dielectrically isolated islands |
DE3843230C1 (en) * | 1988-12-22 | 1989-09-21 | W.C. Heraeus Gmbh, 6450 Hanau, De | Process for making a metallic pattern on a base, in particular for the laser structuring of conductor tracks |
JPH04178503A (ja) * | 1990-11-14 | 1992-06-25 | Nec Corp | 歪センサーの製造方法 |
US5384230A (en) * | 1992-03-02 | 1995-01-24 | Berg; N. Edward | Process for fabricating printed circuit boards |
DE4429794C1 (de) * | 1994-08-23 | 1996-02-29 | Fraunhofer Ges Forschung | Verfahren zum Herstellen von Chip-Widerständen |
US5683928A (en) * | 1994-12-05 | 1997-11-04 | General Electric Company | Method for fabricating a thin film resistor |
US5852226A (en) * | 1997-01-14 | 1998-12-22 | Pioneer Hi-Bred International, Inc. | Soybean variety 93B82 |
US5976392A (en) * | 1997-03-07 | 1999-11-02 | Yageo Corporation | Method for fabrication of thin film resistor |
DE19901540A1 (de) * | 1999-01-16 | 2000-07-20 | Philips Corp Intellectual Pty | Verfahren zur Feinabstimmung eines passiven, elektronischen Bauelementes |
US6365483B1 (en) * | 2000-04-11 | 2002-04-02 | Viking Technology Corporation | Method for forming a thin film resistor |
US6605760B1 (en) * | 2000-12-22 | 2003-08-12 | Pioneer Hi-Bred International, Inc. | Soybean variety 94B73 |
US6613965B1 (en) * | 2000-12-22 | 2003-09-02 | Pioneer Hi-Bred International, Inc. | Soybean variety 94B54 |
DE10110179B4 (de) | 2001-03-02 | 2004-10-14 | BCcomponents Holding B.V. | Verfahren zum Herstellen von Dünnschicht-Chipwiderständen |
-
2001
- 2001-03-02 DE DE10110179A patent/DE10110179B4/de not_active Expired - Fee Related
-
2002
- 2002-02-19 JP JP2002570248A patent/JP4092209B2/ja not_active Expired - Lifetime
- 2002-02-19 US US10/469,214 patent/US6998220B2/en not_active Expired - Lifetime
- 2002-02-19 WO PCT/EP2002/001730 patent/WO2002071419A1/de active IP Right Grant
- 2002-02-19 EP EP02700251A patent/EP1374257B1/de not_active Expired - Lifetime
- 2002-02-19 AT AT02700251T patent/ATE276575T1/de not_active IP Right Cessation
- 2002-02-19 CN CNB028059069A patent/CN100413000C/zh not_active Expired - Lifetime
- 2002-02-19 KR KR1020037011426A patent/KR100668185B1/ko not_active IP Right Cessation
- 2002-02-19 DE DE50201035T patent/DE50201035D1/de not_active Expired - Lifetime
- 2002-02-26 TW TW091103422A patent/TW594802B/zh not_active IP Right Cessation
Non-Patent Citations (1)
Title |
---|
See references of WO02071419A1 * |
Also Published As
Publication number | Publication date |
---|---|
JP4092209B2 (ja) | 2008-05-28 |
DE10110179B4 (de) | 2004-10-14 |
US20040126704A1 (en) | 2004-07-01 |
KR20030086282A (ko) | 2003-11-07 |
US6998220B2 (en) | 2006-02-14 |
DE10110179A1 (de) | 2002-12-05 |
EP1374257B1 (de) | 2004-09-15 |
WO2002071419A1 (de) | 2002-09-12 |
ATE276575T1 (de) | 2004-10-15 |
DE50201035D1 (de) | 2004-10-21 |
JP2004530290A (ja) | 2004-09-30 |
CN100413000C (zh) | 2008-08-20 |
KR100668185B1 (ko) | 2007-01-11 |
TW594802B (en) | 2004-06-21 |
CN1552080A (zh) | 2004-12-01 |
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