EP1362372A2 - Structure d'essai d'electromigration pour la determination de la fiabilite de cablages - Google Patents

Structure d'essai d'electromigration pour la determination de la fiabilite de cablages

Info

Publication number
EP1362372A2
EP1362372A2 EP01995590A EP01995590A EP1362372A2 EP 1362372 A2 EP1362372 A2 EP 1362372A2 EP 01995590 A EP01995590 A EP 01995590A EP 01995590 A EP01995590 A EP 01995590A EP 1362372 A2 EP1362372 A2 EP 1362372A2
Authority
EP
European Patent Office
Prior art keywords
electromigration
test structure
area
region
structure according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01995590A
Other languages
German (de)
English (en)
Inventor
Josef Fazekas
Andreas Martin
Jochen Von Hagen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1362372A2 publication Critical patent/EP1362372A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
    • G01R31/2858—Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Electromigration test structure to detect reliability of wiring
  • the present invention relates to an electromigration test structure for determining the reliability of wiring and in particular to an electromigration test structure for highly accelerated tests in semiconductor circuits.
  • a first and a second sensor connection are located on the test structure connection areas, which leads to an associated sensor pad.
  • JEDEC standard test methods such as the isothermal test (JESD63) and the so-called SWEAT test (JEP119)
  • JEDEC standard test methods such as the isothermal test (JESD63) and the so-called SWEAT test (JEP119)
  • JEDEC standard test methods such as the isothermal test (JESD63) and the so-called SWEAT test (JEP119)
  • JEDEC standard test methods such as the isothermal test (JESD63) and the so-called SWEAT test (JEP119)
  • the invention is therefore based on the object of providing an electromigration test structure for detecting a reliability of wiring, with which a test can be further accelerated with improved test accuracy.
  • a simplified electrical fault analysis can also be carried out for the exact determination of a failure location.
  • the first and second test structure connection areas preferably have a taper to the area to be tested, as a result of which the occurrence of mechanical stresses and a metal flow divergence due to temperature differences and a changed electromigration can be prevented.
  • the taper is in this case essentially stepped, so that a maximum and precisely predeterminable temperature gradient can be set with a corresponding structuring or selection of the respective conductor track widths.
  • the sensor connections to the electromigration area or to the test structure connection area are designed in such a way that a certain temperature adjustment can take place and the influence of the sensor connections is minimized.
  • a second sensor connection is preferably located on the second test structure connection area in the area of the taper, as a result of which a temperature prevailing in the electromigration area remains almost unaffected.
  • blind structures can be formed essentially parallel to the area to be tested, as a result of which much more realistic structures are generated and, for example, a temperature derivative on adjacent conductor tracks can be evaluated.
  • the blind structure preferably consists of a blind electromigration area and a blind Electromigration barrier area, whereby not only the conductor tracks but also, for example, the contacts (vias) can be tested with regard to their product-relevant temperature behavior.
  • FIG. 1 a shows a simplified top view of an electromigration test structure according to a first exemplary embodiment
  • FIG. 1b shows a temperature profile associated with the test structure according to FIG.
  • Figure lc is a simplified sectional view taken along section A-A 'in Figure la;
  • FIG. 1d shows a partial view of the electromigration test structure in the region of an electromigration barrier region
  • FIG. 2 shows a simplified top view of an electromigration test structure according to a second exemplary embodiment
  • Figure 3 is a partial sectional view of an electromigration barrier area according to a third embodiment.
  • FIG. 1 a shows a simplified top view of an electromigration test structure according to a first embodiment. game, wherein an area to be tested has an electromigration area L and an electromigration barrier area V. More precisely, the electromigration region L consists, for example, of a metallic conductor track with a width B1, which is formed, for example, in a metallization level of an associated semiconductor circuit. With a sufficient length 1 of the electromigration region L, there is a constant material flow in this region at a constant temperature, which is caused by electromigration.
  • the test structure uses a contact (via) or contact hole V, which is located between the metallization level for the electromigration area L and a further metallization level for one first test structure connection area II is located.
  • contacts (vias) establish respective connections between the individual metallization levels, although usually other materials are used and therefore a reduced material flow due to the electromigration effect prevails. These areas therefore act as electrical migration barriers.
  • Figure lc shows a simplified sectional view along a section A-A 'in Figure la, the same reference numerals representing the same or corresponding elements and a repeated description is omitted below.
  • the first connection region II can have a first metallic conductor track, which consists, for example, of aluminum, copper, etc.
  • a first metallic conductor track which consists, for example, of aluminum, copper, etc.
  • Electromigration area L also have an aluminum, copper or other metallic conductor track.
  • the as a takt (Via) realized electromigration area consists, for example, of tungsten, titanium or another electrically conductive material with good filling properties. Due to the different material, however, such contacts (vias) V act as electromigration barriers, since no material of the same type is subsequently supplied and therefore material is preferably removed at the conductive level, which can ultimately lead to failure of the test structure.
  • a first sensor connection S 1 and a third sensor connection S 3 with a small conductor track width B are located in the immediate vicinity of the contact (vias) V. Due to the small conductor track width, influencing a temperature of the area to be tested can be minimized. Furthermore, a width B2 of the first test structure connection region II at the contact (via) V is dimensioned to the width B1 of the electromigration region L in such a way that the temperature gradient does not become too high between the two levels due to the heating caused by the impressed heating current.
  • a temperature gradient between the first test structure connection region II at the contact (via) V and the electromigration region L is preferably set to ⁇ 50 ° C., as a result of which mechanical stresses and an influence on electromigration can be reliably minimized.
  • Current is impressed directly from the first test structure connection area II to the second test structure connection area 12, which connects at the other end of the electromigration area L.
  • the widths of the first and second test structure connection areas II and 12 are each gradually reduced (tapering), which results in a taper to the area to be tested.
  • the cross-sectional areas of the respective conductor track sections are again so adjusted so that a maximum temperature gradient Tmax of, for example, 50 ° C. results and mechanical stresses between the stages are thus avoided in particular.
  • the second test structure connection region 12 has a second sensor connection S2, which, according to FIG. 1 a, is only formed at the taper or second stage, as a result of which the temperature profile is influenced by the second sensor connection S2 can be further reduced.
  • the width of the sensor connection is kept as small as possible in order to prevent an undesirable temperature drop.
  • Figure lb shows a simplified representation of a temperature profile along the test structure shown in Figure la. It is essential here that the temperature generated in the electromigration area L is extremely homogeneous and can also be quantitatively recorded very precisely via the sensor connections S2 and S3, which is particularly important in the case of highly accelerated tests. With a test structure of this type, the greatly increased current densities and high temperatures resulting from the Joule heating, which leads to a substantial reduction in the test times, can thus be achieved, particularly in the electromigration region L, due to the greatly increased current densities.
  • the extraordinarily high temperatures in the electromigration range L are essentially constant and can be determined with high precision via the second and third sensor connections S2 and S3 in order to control the respective test programs accordingly.
  • a temperature dependency of the electromigration region L or an associated metal resistor is used to determine the temperature, the sensor connections each being used as voltage taps for detection a respective voltage drop or a potential difference across the electromigration range L.
  • the simple structure of the electromigration region L with its sufficient length 1 and predetermined width B1 thus enables a simple and extremely exact determination of a respective conductor temperature during the measurement, as a result of which sufficient conclusions can be drawn about the associated semiconductor circuit or thin-film circuit.
  • the electromigration area L and the contact (via) correspond to typical conductor tracks and contacts (vias) in the associated semiconductor circuit.
  • the widths B1, B2, B3 and B4 of the respective connection regions II and 12 of the electromigration region L and the electromigration barrier region V are dimensioned such that when a respective test temperature in the electromigration region L is reached, a respective temperature gradient below a maximum predetermined value T ma ⁇ (e.g. 50 ° C).
  • T ma ⁇ e.g. 50 ° C.
  • this additional sensor connection S3 now makes it possible to also determine the exact location of the failure electrically, as a result of which a particular cause of the failure can be determined. Expensive preparations and SEM examinations, as they had to be carried out on conventional test structures, for example to determine the exact location of the failure, are therefore no longer necessary.
  • FIG. 2 shows a simplified top view of an electro-migration test structure in accordance with a second exemplary embodiment, the same reference symbols denoting identical or corresponding elements and a repeated description being omitted below.
  • blind structures are formed in a second exemplary embodiment parallel to the area to be tested, which essentially has the electromigration area L and the electromigration barrier area V, and are preferably spaced apart by a distance F.
  • F is a minimal structural width of a respective manufacturing process that can be realized lithographically.
  • Such a blind structure which is designed at least for the electromigration region L, in turn serves to increase a respective product relevance. Since, in particular, the imaging properties used in lithographic processes can only image isolated or individual conductor tracks in a fuzzy manner and with very indefinite cross-sectional properties, the blind structure shown in FIG. 2 enables adaptation to actually prevailing conditions, since the area to be tested is essentially the same Structuring shows how a conductor track in the associated semi-conductor ter or thin film circuit. The occurrence of supercritical test structures, which fail earlier than the associated semiconductor circuit, for example, can thereby be prevented.
  • a blind electromigration region or a respective Du my line DL is therefore formed parallel to the electromigration region L at the minimum permitted distance on both sides of the test structure.
  • the temperature conditions in an associated semiconductor circuit can also be simulated much better. More precisely, the blind electromigration areas DL cool because of their proximity to the test structure or to the electromigration area L, which is why a higher current density is necessary to achieve the same test temperature. Since this current also flows through the electromigration barrier areas V and causes it to heat up, the blind structures can also have respective blind electromigration barrier areas DV or so-called dummy contacts (vias) in order to avoid a corresponding overheating.
  • a further improvement in product relevance or heat radiation on parallel conductor tracks can be realized by the blind connection areas DI shown in FIG. 2 parallel to the first and second connection areas II and 12.
  • a uniform cooling of the contact (vias) V and the conductive plane can consequently be achieved and a possibly uniform and photo-technically flawless image of the respective structure can be realized, as a result of which a very precise statement can be made about the respective structure Receives product properties of an associated semiconductor circuit.
  • FIG. 3 shows a simplified partial sectional view of an electromigration test structure in accordance with a third exemplary embodiment in the area of the electro-migration barrier V.
  • the same reference symbols again designate the same or corresponding elements as in FIGS. 1 and 2, which is why a repeated description is omitted below.
  • an electromigration barrier with a reduced material flow can also be created, for example, by depositing a continuous metallic conductor track over a topography or edge, which, for example, results in different material structures due to different deposition speeds on the edge and a reduced material flow due to the Electromigration effect occurs.
  • the electromigration test structure described above can therefore be applied not only to the contacts (vias) described above but also to the electromigration barrier regions V shown in FIG. 3, which in turn enables a highly accurate and highly accelerated test of such structures can realize.
  • side wall contacts or connecting structures in trenches, for example, which are realized by means of spacer technology also fall under the term electromigration barrier region.
  • the invention has been described above using integrated semiconductor circuits. However, it is not limited to this and in the same way comprises electrical circuits which are formed using thin-film technology.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Environmental & Geological Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

L'invention concerne une structure d'essai d'électromigration pour la détermination de la fiabilité de câblages. Entre une première zone de raccordement de structure d'essai (I1) et une seconde zone de raccordement de structure d'essai (I2) est formée une zone à tester comportant une zone d'électromigration (L) et une zone faisant barrière à l'électromigration (V). Pour qu'il soit possible d'évaluer une durée de vie avec une grande précision et avec des tests ultrarapides, à proximité immédiate de la zone faisant barrière à l'électromigration (V) se trouvent un premier raccordement de capteur (S1) et un troisième raccordement de capteur (S3), et, sur la seconde zone de raccordement de structure d'essai (I2) se trouve un second raccordement de capteur (S2).
EP01995590A 2001-02-23 2001-12-07 Structure d'essai d'electromigration pour la determination de la fiabilite de cablages Withdrawn EP1362372A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10108915 2001-02-23
DE10108915A DE10108915A1 (de) 2001-02-23 2001-02-23 Elektromigrations-Teststruktur zur Erfassung einer Zuverlässigkeit von Verdrahtungen
PCT/DE2001/004599 WO2002067318A2 (fr) 2001-02-23 2001-12-07 Structure d'essai d'electromigration pour la determination de la fiabilite de cablages

Publications (1)

Publication Number Publication Date
EP1362372A2 true EP1362372A2 (fr) 2003-11-19

Family

ID=7675345

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01995590A Withdrawn EP1362372A2 (fr) 2001-02-23 2001-12-07 Structure d'essai d'electromigration pour la determination de la fiabilite de cablages

Country Status (5)

Country Link
US (1) US20040036495A1 (fr)
EP (1) EP1362372A2 (fr)
CN (1) CN1502132A (fr)
DE (1) DE10108915A1 (fr)
WO (1) WO2002067318A2 (fr)

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DE10253626A1 (de) * 2002-11-15 2004-06-03 Infineon Technologies Ag Teststruktur zur Bestimmung der elektrischen Belastbarkeit von Kontakten
US7888672B2 (en) * 2002-11-23 2011-02-15 Infineon Technologies Ag Device for detecting stress migration properties
US6993446B2 (en) * 2003-03-17 2006-01-31 Schlumberger Technology Corporation Method and apparatus for predicting the time to failure of electronic devices at high temperatures
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US7146588B1 (en) * 2004-08-02 2006-12-05 Advanced Micro Devices, Inc. Predicting EM reliability by decoupling extrinsic and intrinsic sigma
DE102006025351B4 (de) * 2006-05-31 2013-04-04 Globalfoundries Inc. Teststruktur zur Überwachung von Leckströmen in einer Metallisierungsschicht und Verfahren
DE102006049791A1 (de) * 2006-10-21 2008-04-30 X-Fab Semiconductor Foundries Ag Teststruktur für hochbeschleunigte Elektromigrationstests für dicke Metallisierungssysteme von Festkörperschaltkreisen
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US7858406B2 (en) 2007-02-06 2010-12-28 Infineon Technologies Ag Semiconductor device test structures and methods
US7851237B2 (en) * 2007-02-23 2010-12-14 Infineon Technologies Ag Semiconductor device test structures and methods
CN103681621B (zh) * 2012-09-10 2016-03-16 中芯国际集成电路制造(上海)有限公司 半导体检测结构及形成方法
CN104458035B (zh) * 2013-09-24 2017-09-26 中芯国际集成电路制造(上海)有限公司 检测结构及检测方法
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Also Published As

Publication number Publication date
US20040036495A1 (en) 2004-02-26
DE10108915A1 (de) 2002-09-12
CN1502132A (zh) 2004-06-02
WO2002067318A3 (fr) 2003-05-08
WO2002067318A2 (fr) 2002-08-29

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