EP1333483A4 - Procede d'attaque de structure en double damasquinage - Google Patents

Procede d'attaque de structure en double damasquinage

Info

Publication number
EP1333483A4
EP1333483A4 EP01970312A EP01970312A EP1333483A4 EP 1333483 A4 EP1333483 A4 EP 1333483A4 EP 01970312 A EP01970312 A EP 01970312A EP 01970312 A EP01970312 A EP 01970312A EP 1333483 A4 EP1333483 A4 EP 1333483A4
Authority
EP
European Patent Office
Prior art keywords
dual damascene
damascene structure
etching
layer
hard mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01970312A
Other languages
German (de)
English (en)
Other versions
EP1333483A1 (fr
Inventor
Yoshihide Kihara
Shin Okamoto
Koichiro Inazawa
Tomoki Suemasa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of EP1333483A1 publication Critical patent/EP1333483A1/fr
Publication of EP1333483A4 publication Critical patent/EP1333483A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

L'invention concerne un procédé d'attaque de structure en double damasquinage reposant sur l'utilisation d'au moins une couche de film à faible K et d'au moins une couche de masque dur. On forme sur le masque dur au moins une couche de film fictif ne restant pas dans la structure finale, afin d'éviter le phénomène de séparation, moyennant quoi ce procédé permet de limiter le phénomène de séparation du masque dur.
EP01970312A 2000-10-18 2001-10-01 Procede d'attaque de structure en double damasquinage Withdrawn EP1333483A4 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2000317661 2000-10-18
JP2000317661A JP4850332B2 (ja) 2000-10-18 2000-10-18 デュアルダマシン構造のエッチング方法
PCT/JP2001/008623 WO2002033747A1 (fr) 2000-10-18 2001-10-01 Procede d'attaque de structure en double damasquinage

Publications (2)

Publication Number Publication Date
EP1333483A1 EP1333483A1 (fr) 2003-08-06
EP1333483A4 true EP1333483A4 (fr) 2006-02-08

Family

ID=18796413

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01970312A Withdrawn EP1333483A4 (fr) 2000-10-18 2001-10-01 Procede d'attaque de structure en double damasquinage

Country Status (6)

Country Link
US (1) US7326650B2 (fr)
EP (1) EP1333483A4 (fr)
JP (1) JP4850332B2 (fr)
KR (1) KR100810788B1 (fr)
TW (1) TW522490B (fr)
WO (1) WO2002033747A1 (fr)

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JP3944838B2 (ja) 2002-05-08 2007-07-18 富士通株式会社 半導体装置及びその製造方法
JP2004055781A (ja) * 2002-07-19 2004-02-19 Sony Corp 半導体装置の製造方法
TWI286814B (en) 2003-04-28 2007-09-11 Fujitsu Ltd Fabrication process of a semiconductor device
US7125792B2 (en) * 2003-10-14 2006-10-24 Infineon Technologies Ag Dual damascene structure and method
US7091612B2 (en) 2003-10-14 2006-08-15 Infineon Technologies Ag Dual damascene structure and method
KR100519250B1 (ko) 2003-12-04 2005-10-06 삼성전자주식회사 반도체 소자의 금속배선용 패턴 형성방법
JP2005203672A (ja) 2004-01-19 2005-07-28 Sony Corp 半導体装置の製造方法
JP2006179515A (ja) * 2004-12-20 2006-07-06 Oki Electric Ind Co Ltd 半導体素子の製造方法、及びエッチング方法
KR100695431B1 (ko) * 2005-06-22 2007-03-15 주식회사 하이닉스반도체 반도체 소자의 컨택홀 형성방법
KR100674982B1 (ko) * 2005-07-06 2007-01-29 삼성전자주식회사 반도체 소자의 제조방법
US7381343B2 (en) * 2005-07-08 2008-06-03 International Business Machines Corporation Hard mask structure for patterning of materials
KR100739530B1 (ko) * 2006-06-07 2007-07-13 삼성전자주식회사 큰 종횡비의 콘택홀을 갖는 반도체장치의 제조 방법
US7884026B2 (en) * 2006-07-20 2011-02-08 United Microelectronics Corp. Method of fabricating dual damascene structure
JP2008089817A (ja) 2006-09-29 2008-04-17 Oki Electric Ind Co Ltd フォトマスク及びそれを用いた半導体素子の配線パターン形成方法
CN101784533B (zh) * 2007-08-22 2013-08-21 艾博特股份有限两合公司 4-苄基氨基喹啉、含有它们的药物组合物和它们在治疗中的用途
JP2009059903A (ja) * 2007-08-31 2009-03-19 Sharp Corp 半導体装置の製造方法
US7879683B2 (en) * 2007-10-09 2011-02-01 Applied Materials, Inc. Methods and apparatus of creating airgap in dielectric layers for the reduction of RC delay
US8653100B2 (en) * 2008-04-01 2014-02-18 Abbvie Inc. Tetrahydroisoquinolines, pharmaceutical compositions containing them, and their use in therapy
TW201038569A (en) 2009-02-16 2010-11-01 Abbott Gmbh & Co Kg Heterocyclic compounds, pharmaceutical compositions containing them, and their use in therapy
AR075442A1 (es) 2009-02-16 2011-03-30 Abbott Gmbh & Co Kg Derivados de aminotetralina, composiciones farmaceuticas que las contienen y sus usos en terapia
JP2010283213A (ja) * 2009-06-05 2010-12-16 Tokyo Electron Ltd 基板処理方法
JP5600447B2 (ja) * 2010-03-05 2014-10-01 株式会社日立ハイテクノロジーズ プラズマエッチング方法
US9051280B2 (en) 2010-08-13 2015-06-09 AbbVie Deutschland GmbH & Co. KG Tetraline and indane derivatives, pharmaceutical compositions containing them, and their use in therapy
US8883839B2 (en) 2010-08-13 2014-11-11 Abbott Laboratories Tetraline and indane derivatives, pharmaceutical compositions containing them, and their use in therapy
US9045459B2 (en) 2010-08-13 2015-06-02 AbbVie Deutschland GmbH & Co. KG Phenalkylamine derivatives, pharmaceutical compositions containing them, and their use in therapy
US8846743B2 (en) 2010-08-13 2014-09-30 Abbott Laboratories Aminoindane derivatives, pharmaceutical compositions containing them, and their use in therapy
US8877794B2 (en) 2010-08-13 2014-11-04 Abbott Laboratories Phenalkylamine derivatives, pharmaceutical compositions containing them, and their use in therapy
US8586478B2 (en) * 2011-03-28 2013-11-19 Renesas Electronics Corporation Method of making a semiconductor device
US9309200B2 (en) 2011-05-12 2016-04-12 AbbVie Deutschland GmbH & Co. KG Benzazepine derivatives, pharmaceutical compositions containing them, and their use in therapy
WO2013020930A1 (fr) 2011-08-05 2013-02-14 Abbott Gmbh & Co. Kg Dérivés d'aminochromane, d'aminothiochromane et d'amino-1,2,3,4-tétrahydroquinoléine, compositions pharmaceutiques contenant ceux-ci et leur utilisation thérapeutique
JP2014533675A (ja) 2011-11-18 2014-12-15 アッヴィ・ドイチュラント・ゲー・エム・ベー・ハー・ウント・コー・カー・ゲー Ｎ置換アミノベンゾシクロヘプテン、アミノテトラリン、アミノインダンおよびフェナルキルアミン誘導体、これらを含有する医薬組成物、および治療におけるこれらの使用
US9365512B2 (en) 2012-02-13 2016-06-14 AbbVie Deutschland GmbH & Co. KG Isoindoline derivatives, pharmaceutical compositions containing them, and their use in therapy
US8668835B1 (en) 2013-01-23 2014-03-11 Lam Research Corporation Method of etching self-aligned vias and trenches in a multi-layer film stack
US9650334B2 (en) 2013-03-15 2017-05-16 Abbvie Inc. Pyrrolidine derivatives, pharmaceutical compositions containing them, and their use in therapy
US9656955B2 (en) 2013-03-15 2017-05-23 Abbvie Inc. Pyrrolidine derivatives, pharmaceutical compositions containing them, and their use in therapy
US8906810B2 (en) 2013-05-07 2014-12-09 Lam Research Corporation Pulsed dielectric etch process for in-situ metal hard mask shape control to enable void-free metallization
AU2014336153A1 (en) 2013-10-17 2016-04-28 AbbVie Deutschland GmbH & Co. KG Aminochromane, aminothiochromane and amino-1,2,3,4-tetrahydroquinoline derivatives, pharmaceutical compositions containing them, and their use in therapy
JP2016533375A (ja) 2013-10-17 2016-10-27 アッヴィ・ドイチュラント・ゲー・エム・ベー・ハー・ウント・コー・カー・ゲー アミノテトラリン誘導体およびアミノインダン誘導体、これらを含有する医薬組成物、および治療におけるこれらの使用

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Publication number Priority date Publication date Assignee Title
US5821169A (en) * 1996-08-05 1998-10-13 Sharp Microelectronics Technology,Inc. Hard mask method for transferring a multi-level photoresist pattern
EP0905768A1 (fr) * 1997-09-30 1999-03-31 Siemens Aktiengesellschaft Procédé de double damasquinage pour couches métalliques et couches organiques entre deux niveaux de métallisation
US6060380A (en) * 1998-11-06 2000-05-09 Advanced Micro Devices, Inc. Antireflective siliconoxynitride hardmask layer used during etching processes in integrated circuit fabrication
JP2000150519A (ja) * 1998-08-31 2000-05-30 Fujitsu Ltd 半導体装置の製造方法

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JP3078812B1 (ja) * 1998-03-26 2000-08-21 松下電器産業株式会社 配線構造体の形成方法
US6312874B1 (en) * 1998-11-06 2001-11-06 Advanced Micro Devices, Inc. Method for forming a dual damascene trench and underlying borderless via in low dielectric constant materials
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US5821169A (en) * 1996-08-05 1998-10-13 Sharp Microelectronics Technology,Inc. Hard mask method for transferring a multi-level photoresist pattern
EP0905768A1 (fr) * 1997-09-30 1999-03-31 Siemens Aktiengesellschaft Procédé de double damasquinage pour couches métalliques et couches organiques entre deux niveaux de métallisation
JP2000150519A (ja) * 1998-08-31 2000-05-30 Fujitsu Ltd 半導体装置の製造方法
US6060380A (en) * 1998-11-06 2000-05-09 Advanced Micro Devices, Inc. Antireflective siliconoxynitride hardmask layer used during etching processes in integrated circuit fabrication

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Title
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 08 6 October 2000 (2000-10-06) *
See also references of WO0233747A1 *

Also Published As

Publication number Publication date
US20040026364A1 (en) 2004-02-12
US7326650B2 (en) 2008-02-05
TW522490B (en) 2003-03-01
EP1333483A1 (fr) 2003-08-06
KR100810788B1 (ko) 2008-03-06
WO2002033747A1 (fr) 2002-04-25
KR20030051720A (ko) 2003-06-25
JP4850332B2 (ja) 2012-01-11
JP2002124568A (ja) 2002-04-26

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