EP1276024B1 - Elektronischer Schaltkreis und Uhrwerk enthaltend einen solchen Schaltkreis - Google Patents

Elektronischer Schaltkreis und Uhrwerk enthaltend einen solchen Schaltkreis Download PDF

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Publication number
EP1276024B1
EP1276024B1 EP02022189A EP02022189A EP1276024B1 EP 1276024 B1 EP1276024 B1 EP 1276024B1 EP 02022189 A EP02022189 A EP 02022189A EP 02022189 A EP02022189 A EP 02022189A EP 1276024 B1 EP1276024 B1 EP 1276024B1
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EP
European Patent Office
Prior art keywords
signal
electronic circuit
voltage
energy
circuit according
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EP02022189A
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German (de)
English (en)
French (fr)
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EP1276024A3 (de
EP1276024A2 (de
Inventor
Konrad Schafroth
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Richemont International SA
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Richemont International SA
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Priority claimed from PCT/EP1996/002791 external-priority patent/WO1997009657A1/de
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Priority to EP02022189A priority Critical patent/EP1276024B1/de
Publication of EP1276024A2 publication Critical patent/EP1276024A2/de
Publication of EP1276024A3 publication Critical patent/EP1276024A3/de
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04C—ELECTROMECHANICAL CLOCKS OR WATCHES
    • G04C19/00—Producing optical time signals at prefixed times by electric means
    • G—PHYSICS
    • G04—HOROLOGY
    • G04C—ELECTROMECHANICAL CLOCKS OR WATCHES
    • G04C11/00—Synchronisation of independently-driven clocks
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G19/00—Electric power supply circuits specially adapted for use in electronic time-pieces
    • G—PHYSICS
    • G04—HOROLOGY
    • G04C—ELECTROMECHANICAL CLOCKS OR WATCHES
    • G04C10/00—Arrangements of electric power supplies in time pieces

Definitions

  • the present invention relates to an electronic circuit according to the preamble of claim 1 and a movement containing such a circuit.
  • CH-A-597636 Ebauches SA
  • the described movement contains a spring which drives a time display and a generator supplying an alternating voltage via a gear train.
  • the generator feeds a rectifier, the rectifier feeds a capacitive device, and the capacitive device feeds an electronic reference circuit with a stable quartz oscillator and an electronic control circuit.
  • the electronic control circuit has a comparator logic circuit and an energy dissipation circuit connected to the output of the comparator logic circuit and controllable by the comparator logic circuit in their power consumption.
  • the comparator logic circuit is designed to be one of the electronic Reference circuit compares incoming clock signal with a derived from the generator clock signal, depending on the result of this comparison, the size of the power consumption of the Energydissipationsscrien controls and regulates in this way on the control of crizscarias elaboratesinger the gear of the generator and thus the passage of the time display.
  • a watch combines the advantages of a mechanical watch, ie the absence of batteries, with the precision of a quartz watch.
  • EP-A-0239820 and EP-A-679 968 describe various electronic circuits for controlling the speed of a microgenerator in which a monitoring circuit constantly monitors the angular position of the rotor and brakes it as soon as its angular position is ahead. These circuits are difficult to handle because of their sensitivity to errors and phase variations of the components.
  • FIG. 1 a block diagram of an inventive electronic circuit 11 for speed control of a microgenerator is shown.
  • the electronic circuit is from the Microgenerator 1, the speed of which controls it, fed via a capacitance C3, which temporarily stores the energy emitted by the generator.
  • the microgenerator 1, which generates an alternating voltage, is driven by a non-illustrated gear train by a spring, not shown.
  • the wheel train further drives the time display (not shown).
  • the electronic circuit 11 regulates the power consumption of an energy dissipation circuit 9 connected to the microgenerator (FIG. Fig. 11 ), so that the rotational frequency of the rotor of the microgenerator is synchronized with the reference frequency at the output of a frequency divider 5 whose input is fed by a quartz oscillator 3, 4.
  • the nominal frequency of the AC voltage of the microgenerator 1 is preferably 2 n Hz, where n is a natural number different zero.
  • the mechanical part of the movement is part of the prior art and described for example in CH-A-597 636 ,
  • the microgenerator 1 is connected to the two inputs G and G + of the electronic circuit 11.
  • the circuit 11 is preferably constructed as a single IC.
  • the inputs G- and G + are connected to a rectifier and voltage converter circuit 2, the function of which is described below with respect to FIGS FIGS. 2 to 5 is described.
  • the rectifier and voltage converter 2 charges a storage capacitor 10 (C3) which temporarily stores the electrical energy generated by the microgenerator and releases the energy in the form of a substantially continuous voltage to the IC.
  • the rectifier and voltage converter 2 further uses two other capacitors 16 (C1) and 15 (C2).
  • the capacitors C1, C2 and C3 are preferably external, although they could also be integrated in the IC 11.
  • the energy dissipation circuit is connected in parallel with the microgenerator 1.
  • the Energy dissipation circuit 9 but could also be on the other side of the rectifier and voltage converter 2, connected in parallel with the capacitor C3, arranged.
  • the energy dissipation circuit 9 consists of an ohmic resistor whose value is determined by energy dissipation control means 30 (FIG. Fig. 10 ) is controlled.
  • the Energydissipationsscnies 9 could also consist of a regulatable power source.
  • the rotational speed of the rotor of the microgenerator 1 is controlled by varying the resistance value.
  • a stabilized, in detail with reference to FIG. 6 described current source 32 generates various stabilized currents pp, pn, which are intended to power the rectifier and voltage converter 2 and the elements 3, 7, 31.
  • the stabilized current source 32 draws its energy from the capacitance C3, which feeds the entire IC.
  • An oscillator 3,4, provides a reference signal at a predetermined frequency.
  • the oscillator 3, 4 has a quartz 4, which is preferably mounted outside the IC 11 and whose oscillations define a reference frequency at the output of the oscillator 3. This reference frequency is divided by a frequency divider 5 by a predetermined factor, which will be described in detail with reference to FIGS FIGS. 7 and 8 is described.
  • the IC also includes a counter 6, which is described in detail with reference to FIG FIG. 9 is described.
  • a decrement input (DOWN) of the counter 6 is connected to the output of the frequency divider 5, while the increment input (UP) of the counter 6 via a hysteresis comparator 7, which detects the zero transitions of the signal at the output of the microgenerator 1, and via an anti-coincidence circuit 8 with the Microgenerator 1 is connected.
  • the anti-coincidence circuit 8 prevents the simultaneous occurrence of UP and DOWN pulses on both inputs of the counter 6, which could otherwise assume unpredictable behavior.
  • the anti-coincidence circuit synchronizes the signals UP and DOWN to signals with different phase, which originate from the frequency divider 5.
  • the IC further includes an internal voltage doubler 31, which allows the energy dissipation control means brake control 30 and the Energydissipationsscrien 9 with a higher voltage HV> Vdd and a lower voltage LV ⁇ Vss to feed and drive.
  • the energy dissipation control means 30 controls the energy dissipation of the Energydissipationsscaria 9 in response to the reference signal, which is generated by the quartz crystal 3,4 and the signal coming from the microgenerator 1.
  • the reference signal which is generated by the quartz crystal 3,4 and the signal coming from the microgenerator 1.
  • the frequency of the signal between the inputs G + and G- is greater than the frequency of the reference signal at the output of the frequency divider 5.
  • the counter 6 thus receives more pulses on its increment input UP than during a time interval its decrement input DOWN; its count thus increases.
  • the energy dissipation control means 30 controls the resistance value of the energy dissipation circuit 9 and consequently the energy dissipation in such a way that the microgenerator 1 is braked. In this way, the rotational frequency of the microgenerator 1, and thus the course of the time display with the reference frequency, which originates from the quartz oscillator, synchronized.
  • the regulation value B1: B31 which is given to the energy dissipation circuit 9 by the energy dissipation control means 30 in this example depends on the counter value 6, that is, the difference of the number of pulses of the signal UP coming from the microgenerator and the number of pulses DOWN which come from the quartz oscillator 3,4, since the start of the clock.
  • the control mode is thus integral.
  • Other types of control such as a control that is proportional to the current frequency difference or the gradient of the frequency difference, or proportional-integral-derivative (PID) control, may also be used.
  • the rotor rotation speed is controlled by controlling the braking resistance value in the energy dissipation circuit 9; An on-off control could also be used.
  • the energy dissipation control means includes a hysteresis comparator 7 which compares the signals G +, G- on the two inputs connected to the microgenerator 1.
  • the signal Gen at the output of the comparator 7 is thus a rectangular signal which changes state at each polarity change of the signal between the inputs G +, G-.
  • the use of a hysteresis comparator allows filtering of signal interference between inputs G +, G-.
  • the hysteresis comparator 7 is fed by the current source 32.
  • the rectification and voltage converter circuit 2 is on the FIGS. 2 to 5 shown.
  • the first switch 19 preferably consists of a field-effect transistor, which acts as a simple diode immediately after a start of the movement.
  • the voltage drop across the switch 19 is at this moment equal to the diode threshold voltage, about 400 mV.
  • the transistors acting as switches are driven by the comparators.
  • the voltage supplied by the voltage tripler circuit is higher than that Voltage of the capacitor 10
  • the first field effect transistor is opened.
  • the voltage drop across the channel of the field effect transistor is only about 10 mV. The voltage loss is thus significantly reduced in the use of transistors and the transistors driving comparators instead of the diodes, the energy reserve of the movement used more economically and increases the power reserve.
  • the field effect transistor 19 is only blocked again when the voltage C2 supplied by the voltage tripler circuit drops below the voltage Vdd of the first capacitor 10 again.
  • the first switch 19 is controlled by a signal / ser, which from a first on FIG. 4 shown comparator 21 is discharged.
  • the comparator circuit 21 has a comparator 210 which compares the voltage on both sides of the switch 19. When the voltage C2 on the left side of the switch is higher than the voltage Vdd on the right side, the output of the comparator 210 goes from 0 to 1.
  • the voltage differential across switch 19 must be 2mV or more for the output of comparator 210 to go to one.
  • the switch 19 would close as soon as the voltage difference is 2mV or more. But since the Internal resistance of this switch is small, the voltage drop across the closed switch can be smaller than the offset voltage. In this case, the switch 19 would be opened immediately. The voltage difference across the switch 19 would then be present again, so that the output of the comparator would go back to 1 and the switch 19 would close again: the system could oscillate.
  • a time difference is made between the measuring and the switching.
  • the switch 19 is blocked by the signal mess and thereby the comparator is allowed to detect the voltage difference across the switch.
  • the value at the output of the comparator 210 when the transistor 19 is locked is stored in a memory element 211 by means of a latch signal. Only after a period of time, the signals mess and latch go to 0, and the switch 19 is controlled with the value stored in the memory element 211 ser. This ensures that the system does not oscillate and that the current flows from C2 to Vdd.
  • a NAND gate 3081 which combines the 16 kHz, 8 kHz, 4 kHz, 2 kHz and 1 kHz signals emitted by the frequency divider 5 outputs a signal p.
  • the pulsation signal p therefore always has the value 1, except once per 1 kHz cycle during a 16 kHz half-cycle.
  • This signal at the output of the NAND gate 3081 is inverted by an inverter 3082 which is connected to an AND gate 3083.
  • the signal rud is zero, then always one.
  • the signal mess output by the gate 3083 is always zero, except after the startup when p has the logic state 1.
  • the signal p at the output of the NAND gate 3081 is delivered, inter alia, to the OR gate 3084, which also receives a 32 kHz signal, which originates from the frequency divider 5.
  • the signal r output from gate 3084 therefore always has the value zero, except when p and the 32 kHz signal are simultaneously zero, that is, once per 1 kHz cycle during a half 32 kHz cycle.
  • This signal is validated by the signal rud and inverted by means of a NAND gate 3085.
  • the latch signal output by port 3085 will only pass zero if r is 1 and rud is not zero at the same time.
  • the signal latch is thus used to store the state at the output of the comparators 20 and 21 in the registers 201, 211 in the comparison circuits 20, 21, respectively.
  • the signals mess and latch can be formed only when the quartz oscillator and the divider chain are functioning. However, this is not the case when starting up the circuit, and so the circuit must be designed so that the switches are controlled directly by the comparators when the system is started: When the system is started up, the signals mess, bwz. Latch, held by the signal rud to zero, or one. As a result, the switch 19 is driven directly by the comparators 20,21. As soon as the signal rud goes to one, which means that the quartz oscillator and the divider chain are functioning, the switch 19 is driven with the value stored in the memory means 211.
  • the voltage tripler 15, 16, 17, 18 includes a second capacitor 15 (C2) and a third capacitor 16 (C1) connected in series with the microgenerator 1 at the inputs G + and G-.
  • a second switch 17 is connected between the input G and the grounded end of the third capacitor 16 opposite the microgenerator.
  • a third switch 18 is connected between the input G + and the end of the second capacitor 15 opposite the microgenerator, which is connected to the first switch 19.
  • the switches 17 and 18 are controlled by a second comparator circuit 20 (FIG. FIG. 3 ) controlling the electrical potential of the input G-, which is connected to the second capacitor 15, compares with the potential of the mass.
  • the switches 17 and 18 are also made of field effect transistors, which act as diodes in the locked state. After starting the movement, the capacitances 15 and 16 are charged by the diode structures of the transistors 17 and 18. As soon as the comparators operate and the voltage of the generator at node G- is lower than Vss, the second comparator circuit 20 tilts on the next edge of the signal mess, and the state of the comparator is stored in the memory element 201 at the edge of the latch signal, and the Switch with the stored values activated. The two transistors 15 and 16 are then conductive. The capacitors 15 and 16 are therefore charged alone through the channel of the transistors 17 and 18, which turns out to be energetically favorable. It should be noted that the input G- connected to the microgenerator 1 is connected to the ground via the channel of the transistor 17 as soon as the transistor 17 is conducting.
  • Comparators 200 and 210 are fed with the voltage stored in the capacitor C3 Vdd. In addition, they require a power supply pp, or pn, which by the current source 32, in the FIG. 6 explained is accomplished.
  • the comparators do not work as long as the currents pp and pn are not n high enough; In this case, its output remains in the zero state, such that the controlled switches 17, 18, 19 remain disabled.
  • the current source 32 consists of a classic current mirror. It includes a resistor 321 of high value, for example 300K ⁇ , connected between the ground and source of an n-channel field effect transistor 322.
  • the drain of transistor 322 is connected to the drain of field effect transistor 323a and to the gate of 3 P-channel transistors 323a, 323b, 323c connected in series, wherein the source of the latter is fed with the voltage generated by the voltage converter 2 voltage.
  • the drain of the transistor 322 is further connected to the gate of the three P-channel field effect transistors 323a, 323b, 323c as a mirror circuit.
  • the current pp which passes through the channel of the transistor 322 and the resistor 321, feeds the comparator 200, which in FIG. 3 is explained.
  • the drain of transistor 323a is connected to the drain of N-channel transistor 322 and connected in series with the gate of N-channel transistors 322a ', 322b', 322c ', 322d' and as a mirror with respect to transistor 322.
  • the source of transistor 322a ' is connected to ground.
  • the current pn which passes through the transistors 323a ', 323b' and 323c ', feeds the comparator 210, which in FIG. 4 is explained
  • a decrease in pp results in a reduction of the voltage drop across resistor 323 and, consequently, a voltage reduction applied to the gate of P-channel transistors 323a ', 323b', 323c '. These become consequently more permeable, which leads to an increase of the voltage at the drain of the transistor 323a ', which is applied to the gate of the transistor 322. This is therefore permeable and allows an increase of the flowing current pp.
  • the current pp is stabilized and therefore depends only slightly on the applied load. It is easy to show that the current pn penetrating the transistors 323a ', 323b' and 323c 'is stabilized in the same way.
  • the magnitude of the current can thus be determined by adjusting the characteristics of the elements in the current source, in particular the number of transistors and the size of their channels. It is thus possible to freely determine the currents pp and pn through the two branches of the mirror.
  • Such a current mirror has two equilibrium states. The first has been described and is reached when the currents pp and pn have reached the desired magnitude. The second state corresponds to the currents pp and pn equal to zero. This second state is reached by name, when all transistors are blocked. This condition exists in particular when the system is energized, thus the currents pp and pn are zero.
  • An N-channel initialization transistor 320 is provided to force current through the current mirror 32 at the start-up phase to reach its first equilibrium state. The gate of the transistor 320 is grounded while its source is connected to the input G- of the microgenerator 1. The drain of the initialization transistor is connected to the gate of the P-channel transistors.
  • the microgenerator 1 is floating with respect to the mass.
  • the signal G- at the input of the microgenerator thus oscillates in an approximately sinusoidal manner with respect to the ground.
  • the input signal is G-negative, that is, below the ground voltage
  • the transistor 320 becomes transparent and the negative voltage of G- is applied to the gate of the P-channel transistor 323a ', 323b', 323c '. Consequently, these transistors suddenly become conductive, such that only one current pn circulates, that the voltage at the gate of the transistor 322 rises and that this also transmits a current pp. This current is, as explained above, applied to the comparator 20 (FIG. FIG.
  • the output of the comparator circuit 20 changes state, such as in the FIG. 2 indicated when the voltage at the node G- is lower than Vss, and opens the transistors 17 and 18, which connects the input G- of the microgenerator 1 with the ground and the input G + of the microgenerator with C2.
  • the transistor 320 is turned off and stops from now on to consume power.
  • the current source 2 is initialized from now on and the currents pp and pn quickly reach the desired value.
  • the current source can be easily completed, for example by means of other N-channel transistors whose gate is connected to the drain of transistor 323a 'and the source to the ground.
  • the current through these transistors can thus be easily controlled for the supply of other components, for example components of the quartz oscillator 3,4.
  • FIG. 7 illustrates a preferred embodiment of a frequency divider 50 of the present invention.
  • the frequency divider consists of ten series-connected D flip-flops. The frequency of the signal is divided by 2 for each flip-flop.
  • the frequency of the signal at the output of the divider 50 is 2 -10 * 32kHz, that is 32 Hz.
  • This signal is combined by the 500 kHz circuit with the 4 kHz signal to produce a DOWN signal, which occurs once per cycle of 32 Hz and during a 4 kHz half cycle. assumes the logical state 1.
  • the FIG. 8 illustrates a circuit 51 that provides a power-on-reset signal rud. This signal is determined inter alia to reset the counter 6 at the initialization to a predetermined value and turn off the Energydissipationsscrien 9.
  • the circuit 51 includes 3 P-channel field effect transistors 510, 511, 512 arranged in series with a P-channel transistor between the ground and the power supply. The gate of the three P-channel transistors receives the signal pp, which originates from the current source 32. In the Initialization, the 3 transistors 510, 511 and 512 remain blocked as long as the current source 32 does not supply a sufficient current. The voltage at point 516 is therefore zero.
  • the inverter 550 converts this voltage into a signal POR1, which is combined by means of an OR gate 528 with a signal POR2.
  • the signal at the output of the gate 528 is forwarded to a 2-input flip-flop consisting of the two NOR gates 517 and 518.
  • the other input of the flip-flop 517, 518 is connected to the output of a frequency divider 520, which is composed of five flip-flops 521-526.
  • the 32 Hz output signal output by the frequency divider 50 is connected to the input of the first flip-flop 521.
  • the inputs / reset for resetting the flip-flops 521-526 are connected via an inverter 527 to the output of the inverter 515.
  • the signal POR1 is one as long as the power source is not supplying enough power.
  • the signal POR2 is one as long as the frequency from the frequency divider 5 does not reach a predetermined value. Consequently, the signal at the output of the gate 528 is only zero when the crystal oscillator and the power source are both functioning.
  • this signal is still 1, so flip-flops 521-526 are all set to zero.
  • the input of the flip-flop 517, 518, which is connected to the flip-flop 526, thus receives the logic state zero, while the input, which is connected to the inverter 515, the logic state 1 receives.
  • the output of the flip-flop 517, 518 is therefore 1.
  • the signal is inverted by the inverter 519 into a signal labeled rud (reset up-down counter) having a logical value of zero.
  • the 3 transistors 510 to 512 become permeable.
  • the signal at point 516 is thus Vdd, such that the inverter 515 outputs a signal POR1 having a logical value of zero.
  • a logic zero will be applied to the 2-input flip-flop 517, 518 through the gate 528, while the inputs / reset of the flip-flop 521-526 receive the logic 1 value.
  • the frequency divider 520 begins dividing the supplied 32 Hz frequency. After one second, the signal at the output of the flip-flop 560 goes to 1. Since the two inputs of the flip-flop 517, 518 are logic 1, its output goes to zero so that the signal rud reaches logic 1. This value is then maintained as long as the current value pp is sufficient and the quartz oscillator also works.
  • the signal POR1 does not go to one.
  • the second power-on-reset signal POR2 goes to one as soon as the frequency from the frequency divider drops below a certain value.
  • the signal rud appears again, so that the switches 17, 18, 19 of the voltage converter are also directly controlled by the comparators 200, 210 in this case.
  • the starting of the IC is ensured only with the signal POR2 au the frequency divider.
  • the signal POR2 remains at zero.
  • FIG. 9 illustrates a preferred embodiment of the counter circuit 6.
  • the counter circuit 6 comprises a 6-bit counter 60t.
  • the counter 60 is formed, for example, by six resettable and series D flip-flops.
  • the binary number formed by the outputs Q1 to Q6 increases by one unit at every leading edge output to the input 601.
  • the counter is reset to zero when a signal rud is issued to the reset input 603.
  • false counts are prevented outside the count limits of the counter 60.
  • the signals Q1 - Q6, which are output by the counter 6, allow the coding of 64 different braking values.
  • the braking of the microgenerator between these minimum and maximum values does not increase linearly.
  • the energy dissipation via the braking resistor Rf of the energy dissipation circuit 9 preferably develops in such a way as shown schematically on the diagram of FIG Figure 10A is shown. Between 0 and 31, the frequency difference between the microgenerator 1 and the oscillator 3, 4 integrated by the counter 6 is low: no braking is initiated.
  • the FIG. 10 explains the energy dissipation control means 30. They convert the signals Q1: Q6 from the counter into signals B1: B63 corresponding to those on the FIG. 11 explained Energydissipationsscnies 9 directly control. Like at FIG. 1 set forth, the Energydissipationsscnies 9 is connected directly between the inputs G +, G- of the microgenerator. It consists of a plurality of resistors 910 to 916 integrated on the IC.
  • the values of the resistors 910 to 916 are according to Figure 10A Inversely proportional to the strength of the control signals B1 - B63: the signals B62 and B63 control a more effective braking than, for example, the signal B1.
  • the switches 900 to 906 are N-channel field effect transistors. When the voltage at the gate of the transistor is at 0, the transistor turns off, so no current flows through the transistor. But as soon as the voltage at the source of the corresponding transistor is below Vss, the transistor becomes conductive. This means that the generator is braked, because now a current flows, since the resistors are connected between the terminals (G + and G-) of the generator.
  • N-channel and P-channel transistors can only be used near Vss and Vdd as good switches. If the voltage at the drain and source is somewhere between Vdd and Vss, it is no longer sufficient to use the gate with Vdd resp. Vss for the transistors to become conductive.
  • the transistor 920 is not driven by Vss, but by a signal LV that has a much lower voltage than Vss in the active state.
  • the formation of the LV in the circuit 30 will be described later.
  • the N-channel transistors 900: 906 can not be directly driven with the signals Q1: Q6 from the counter because these signals can not be higher than Vdd. Therefore, these transistors are driven by the signals B1: B63, whose logic states correspond to those of Q1: Q6, but whose voltages are doubled.
  • the signals Q1-Q5 are converted with level shifters 301-305 in the energy dissipation control means 30 into the output signals B1-B5.
  • the switch 18 of the voltage converter 2 is driven with a signal which has the same logic state as the signal par, but whose voltage is increased. It would also be possible to double the voltage of the signals par and ser, which drive the switches 17 and 19.
  • the level shifters 301-305 in FIG. 10 are fed by a voltage HV, which is obtained by a doubling of the voltage Vdd at the capacitor C3 by means of a voltage doubler 31, not shown.
  • the voltage doubler must be built to deliver a voltage that is at least equal to Vdd even at initialization.
  • the voltage doubler 31 may be driven by the already described signal rud so that it provides a voltage Vdd at initialization and a doubled voltage HV only after the signal rud has changed state when the crystal oscillator and current source both function.
  • the logic state "62" is detected by an AND gate 306 when the signals B2, B3, B4 and B5 are all 1 (62 expressed in decimal equals 111110 binary).
  • Gate 306 multiplies signals B2 through B5 and provides logic state 1 signal B62 only when the counter reaches stage 30 or 31.
  • a second AND gate multiplies B62 by B1 in such a way that the logic state "63" is detected by means of a signal B63.
  • the signals B62, or B63 directly control the transistors 905, and 906, respectively.
  • the circuit 30 supplies the signal LV, which is intended to drive the P-channel transistor 920 in the energy dissipation circuit 9.
  • the LV signal is generated by a level shifter 300.
  • the voltage from the LV signal in the active state must be at least one threshold lower than Vss.
  • the output of the level shifter 300 is connected to a capacitor 3005.
  • a transistor 3006, which functions like a diode, is connected between the other side of the capacitor 3005 and the dot / rud.
  • the transistor 3006 has a threshold Ue, eg 400mV.
  • the level shifter 300 supplies a voltage HV
  • the voltage charged in the capacitor 3005 is ⁇ U HV -Ue.
  • the voltage of the LV signal drops to Vss- (HV-Ue), allowing the transistor 920 to conduct.
  • the signal / rud is one, so that LV also remains at one, and transistor 920 is disabled. Transistor 920 can not conduct until the signal is rud / zero.
  • the level shifter 300 is controlled by a signal / b such that the energy dissipation circuit 9 brakes when the signal / b is zero.
  • the signal / b is output through a NAND gate 3080, which logically combines the signals Q6 and p.
  • the signal / b is 1 if at least one of these two signals is zero. For example, if Q6 is zero, that is, if the counter 6 has not reached at least the level 16, the signal / b 1 is such that the Energydissipationsscrien 9 can brake only from level 16 of the counter, according to the diagram of Fig. 10a ,
  • the formation of the pulsation signal p by the circuit 308 has already been described in relation to FIGS FIG. 5a explained.
  • the pulsation signal p therefore always has the value 1, except once per 1 kHz cycle during a 16 kHz half-cycle. This serves to recharge the capacity that the LV generates.
  • the braking is interrupted by the pulsation signal p once every millisecond (pulsed braking).
  • solutions are also conceivable in which work is done with LV1 and LV2 and accordingly with 2 P-channel transistors so that the brake does not have to be interrupted.
  • the charging of the capacitances C1, C2, C3 and braking must be disconnected, ie the moment where braking is applied must not depend on the charging.
  • the voltage drop is relatively small, in addition, this voltage drop is only present when braking is strong. But this is synonymous with a high drive torque and thus a great security that the generator quickly with a stroke again accelerated and the system can be re-energized. But it would also be possible to separate the braking and charging strictly. For example, during a positive and negative half-cycle, one could first only brake and during the next positive and negative half-wave, first only brake and during the next positive and negative half-cycle only charge the capacities. Thus, the voltage drop caused by the braking is eliminated and the capacities are maximally charged.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Electromechanical Clocks (AREA)
  • Electric Clocks (AREA)
  • Control Of Electric Motors In General (AREA)
  • Control Of Eletrric Generators (AREA)
EP02022189A 1996-06-26 1997-06-25 Elektronischer Schaltkreis und Uhrwerk enthaltend einen solchen Schaltkreis Expired - Lifetime EP1276024B1 (de)

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EP02022189A EP1276024B1 (de) 1996-06-26 1997-06-25 Elektronischer Schaltkreis und Uhrwerk enthaltend einen solchen Schaltkreis

Applications Claiming Priority (4)

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PCT/EP1996/002791 WO1997009657A1 (de) 1995-09-07 1996-06-26 Uhrwerk
WOPCT/EP96/02791 1996-06-26
EP97810403A EP0816955B1 (de) 1996-06-26 1997-06-25 Elektronischer Schaltkreis und Uhrwerk enthaltend einen solchen Schaltkreis
EP02022189A EP1276024B1 (de) 1996-06-26 1997-06-25 Elektronischer Schaltkreis und Uhrwerk enthaltend einen solchen Schaltkreis

Related Parent Applications (2)

Application Number Title Priority Date Filing Date
EP97810403.2 Division 1997-06-25
EP97810403A Division EP0816955B1 (de) 1996-06-26 1997-06-25 Elektronischer Schaltkreis und Uhrwerk enthaltend einen solchen Schaltkreis

Publications (3)

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EP1276024A2 EP1276024A2 (de) 2003-01-15
EP1276024A3 EP1276024A3 (de) 2007-05-02
EP1276024B1 true EP1276024B1 (de) 2011-12-21

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EP97810403A Expired - Lifetime EP0816955B1 (de) 1996-06-26 1997-06-25 Elektronischer Schaltkreis und Uhrwerk enthaltend einen solchen Schaltkreis
EP02022189A Expired - Lifetime EP1276024B1 (de) 1996-06-26 1997-06-25 Elektronischer Schaltkreis und Uhrwerk enthaltend einen solchen Schaltkreis

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EP97810403A Expired - Lifetime EP0816955B1 (de) 1996-06-26 1997-06-25 Elektronischer Schaltkreis und Uhrwerk enthaltend einen solchen Schaltkreis

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US (2) US6194878B1 (es)
EP (2) EP0816955B1 (es)
JP (1) JP2933910B2 (es)
KR (1) KR100547249B1 (es)
DE (1) DE59709745D1 (es)
DK (1) DK0848842T3 (es)
ES (1) ES2196288T3 (es)
SG (1) SG72793A1 (es)
TW (1) TW366444B (es)

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DE69735094T2 (de) 1996-11-13 2006-07-20 Seiko Epson Corp. Stromversorgungseinrichtung und tragbare elektronische einrichtung
JP3006593B2 (ja) * 1997-09-30 2000-02-07 セイコーエプソン株式会社 電子制御式機械時計およびその制御方法
US6795378B2 (en) 1997-09-30 2004-09-21 Seiko Epson Corporation Electronic device, electronically controlled mechanical timepiece, and control method therefor
CN1237419C (zh) 1998-11-17 2006-01-18 精工爱普生株式会社 电子控制式机械钟表
US6414909B1 (en) * 1998-11-19 2002-07-02 Seiko Epson Corporation Electrically controlled mechanical timepiece and control method therefor
EP1215545A1 (fr) 2000-12-18 2002-06-19 Asulab S.A. Montre électronique analogique ayant un dispositif de remise à l'heure suite à une insuffisance d'alimentation
JP3627660B2 (ja) * 2001-02-28 2005-03-09 セイコーエプソン株式会社 電子機器、電子制御式機械時計、電子機器の制御プログラム、記録媒体、電子機器の制御方法および電子機器の設計方法
CH694621A5 (fr) * 2001-07-02 2005-04-29 Richemont Int Sa Procédé de régulation et module électronique de régulation pour mouvement d'horlogerie à remontage mécanique.
US6826124B2 (en) * 2002-12-04 2004-11-30 Asulab S.A. Timepiece with power reserve indication
DE60312536T2 (de) * 2003-12-16 2007-11-22 Asulab S.A. Elektromechanische Uhr, die mit einer Gangreserveanzeige ausgerüstet ist
JP5707761B2 (ja) * 2010-07-20 2015-04-30 日産自動車株式会社 欠相診断装置及び欠相診断方法
CH705679B1 (fr) 2011-10-28 2017-01-31 Swatch Group Res & Dev Ltd Circuit d'autorégulation de la fréquence d'oscillation d'un système mécanique oscillant, et dispositif le comprenant.
EP2590035B1 (fr) * 2011-11-01 2020-12-30 The Swatch Group Research and Development Ltd. Circuit d'autorégulation de la fréquence d'oscillation d'un système mécanique oscillant, et dispositif le comprenant
CH707005B1 (fr) 2012-09-25 2023-02-15 Richemont Int Sa Mouvement de montre-chronographe avec barillet et régulateur à quartz.
CH707340A2 (fr) * 2012-12-11 2014-06-13 Richemont Internat Ltd Organe régulateur pour montre-bracelet.
CH707787B1 (fr) 2013-03-25 2021-09-15 Richemont Int Sa Organe régulateur pour montre bracelet et procédé d'assemblage d'un organe régulateur pour montre bracelet.

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Also Published As

Publication number Publication date
KR19990006361A (ko) 1999-01-25
EP0816955A1 (de) 1998-01-07
DE59709745D1 (de) 2003-05-15
EP0816955B1 (de) 2003-04-09
EP1276024A3 (de) 2007-05-02
EP1276024A2 (de) 2003-01-15
KR100547249B1 (ko) 2006-03-23
US6194878B1 (en) 2001-02-27
TW366444B (en) 1999-08-11
DK0848842T3 (da) 1999-11-08
JPH1123743A (ja) 1999-01-29
ES2196288T3 (es) 2003-12-16
JP2933910B2 (ja) 1999-08-16
US6208119B1 (en) 2001-03-27
SG72793A1 (en) 2000-05-23

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