EP1264190A1 - Ensemble circuit et procede pour evaluer des condensateurs dans des matrices - Google Patents

Ensemble circuit et procede pour evaluer des condensateurs dans des matrices

Info

Publication number
EP1264190A1
EP1264190A1 EP01913677A EP01913677A EP1264190A1 EP 1264190 A1 EP1264190 A1 EP 1264190A1 EP 01913677 A EP01913677 A EP 01913677A EP 01913677 A EP01913677 A EP 01913677A EP 1264190 A1 EP1264190 A1 EP 1264190A1
Authority
EP
European Patent Office
Prior art keywords
measuring
test
path
circuit arrangement
branch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01913677A
Other languages
German (de)
English (en)
Inventor
Ute Kollmer
Stephan Sauter
Carsten Linnenbank
Roland Thewes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1264190A1 publication Critical patent/EP1264190A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/06—Sense amplifier related aspects
    • G11C2207/063—Current sense amplifiers

Definitions

  • the present invention relates generally to a circuit arrangement and a method for evaluating capacitances in m arrays.
  • matrix-shaped capacitance arrangements z. B. be carried out in capacitive sensors, the task of which is to measure capacitively detectable parameters within certain limits as a function of the location (examples: spatially resolved pressure sensors, fingertip sensor).
  • Circuits for on-chip capacitance-voltage, on-chip capacitance-current, or on-chip capacitance-frequency conversion are also required in products with which sensor signals, which come from capacitive sensors, are evaluated and have to be further processed (e.g. capacitive pressure sensors, defogging sensors, ...)
  • the invention is therefore based on the object of providing a circuit and a method which can be used with this circuit and which enables the measurement-related elimination of parasitic effects and other deviations in the correct determination of capacitances in matrices.
  • the invention is initially directed to a circuit arrangement for evaluating the capacities of a matrix, which in at least one dimension has a plurality of rows with at least one capacitance, with a test branch which is connected to a first electrode of each of the capacitances to be evaluated and with which two different potentials can be applied to the first electrodes, a measuring branch which is connected to the second electrodes of each of the capacitances to be evaluated and which has:
  • the circuit arrangement is characterized by control means which can switch each of the capacitances to be evaluated individually to the two different potentials.
  • the capacitances to be evaluated are to be understood here as all the capacitances occurring in a matrix that have to be measured, for example on-chip capacitances that can be produced with semiconductor processes or capacitances with discrete circuit arrangements, capacitors etc.
  • a matrix has an arrangement of capacities. In the simplest case, this is a single set of capacities. Such a matrix could be described as one-dimensional, since there is an arrangement of capacities in only one of the dimensions.
  • a two-dimensional matrix has a plurality of rows of capacities (in contrast, the one-dimensional matrix has only one capacitance for each of these rows), each of the capacities in one row belonging to a different row of capacities in the other dimension. Accordingly, each of the capacities is defined by its clear assignment to the rows of the two dimensions. The same applies to three- or multi-dimensional matrices, but with more groups of rows of capacities.
  • Each capacitor has two electrodes that are connected to the rest of one Circuit are connected.
  • the part of circuit, to which the verbun one electrode of each of the capacitances ⁇ is referred to as the test arm as it is involved in examining the capacity and connected with said other electrode of each of the capacitances branch is called the measuring path, which is so called because it contains the actual Mes ⁇ solution, ie assessment of capacity to be.
  • a path is to be understood here as an electrical control system which uniquely connects points and into which, in addition to the actual conductors, further elements such as switches, transistors and measuring instruments can be incorporated.
  • This circuit arrangement according to the invention enables the method according to the invention for evaluating capacitances to be carried out due to the fact that the various potentials can be applied.
  • the basic principle of the invention consists in activating at least one of the capacities to be assessed, i.e. to apply the potentials to them in order to be able to carry out an evaluation of the capacitance and then to carry out a measurement-free evaluation of the capacitance by means of the measuring branch.
  • Capacities can also be grouped with suitable control, so that several capacities can be evaluated at the same time. It is also possible to assign a plurality of evaluation circuits to a corresponding matrix of capacities, which are either responsible for sub-areas of the matrix or which can all be connected to any capacities of the matrix.
  • the drive means for each dimension of the matrix of an arrangement of switching paths, wherein E ach of the rows with capacities is a circuit path is at least sen zugewie- having a control and Kursin ⁇ est a switchable by the drive, m the Prufzweig integrated control switching element at least one of the two different which potentials to the first electrodes in a row
  • an n-dimensional grid of switching paths is formed, with which, by selecting one of the rows per dimension, a specific capacitance located at the intersection of the rows can be controlled.
  • the activation is done simply in that the first and second Po be ⁇ tential connected to the electrode of the capacitor, what happens to the switching elements, which the respective capacitance your health for each of the dimensions of a spot of fr portion of Prufpfads m the Prufpfad incorporated become .
  • each of the capacitances of a row has at least one control switching element integrated into the part of the test branch leading to the capacitance.
  • each part of the test branch that supplies a capacitance has its own control switching element for its activation.
  • the control switching elements of a number of capacitances, which are controlled by a switching path, are switched simultaneously.
  • the switching paths of at least one dimension for each of the rows of capacitors can have at least one control switching element integrated into the part of the test branch leading to the row.
  • the switching paths of at least one dimension for each of the rows of capacitors can have at least one control switching element integrated into the part of the test branch leading to the row.
  • Capacity receives its own switching element and for a second dimension all capacities are activated via a common control switch.
  • control means can have an address decoder with an individually controllable output for each of the rows of capacitances, and the controls can have a signal line between each output and the control switching element.
  • a separate address coder is required for each of the dimensions, whereby the address decoders of the individual dimensions can be combined to form a common unit.
  • an alternating voltage can simply be applied to the test branch, the amplitude maxima of which then each represent the two different potentials.
  • the AC voltage can preferably be a square-wave voltage in order to make a clear and quick back and forth
  • the test branch may have a first test path with a first switching element and a second test path with a second switching element for each of the capacitors, a first potential being present on the first test path and a second potential on the second test path, and both test paths via one Nodes are connected to the first electrode.
  • This preferred arrangement ensures, by means of the two switching elements, that the different potentials can be applied to the electrode of a capacitor.
  • connectivity is via switching elements, which are integrated into the test paths. V orteilhaftate both Prufpfade should be switched on at a time. Therefore, it is preferred that the switching paths to ⁇ least one dimension for Ede the capacities of a number m a first Prufpfad integrated control switching element and a second m Prufpfad integrated control switching element having.
  • This circuit arrangement can also be simplified, as above, in that the switching paths of at least one dimension for each series of capacitors have a control switching element integrated in the first test path and a control switching element integrated in the second test path.
  • all capacities in a row that are controlled by a common switching path are in turn switched by a single control switching element (provided the corresponding control switching elements are also switched on in the other dimensions).
  • the first measuring path is connected via a third switching element and the second measuring path is connected via a fourth switching element.
  • At least one of the switching elements is preferably a transistor. In fact, in conventional circuits, especially in semiconductor circuits, all of the switching elements will be transistors.
  • the instrument for evaluating the capacities is preferably an ammeter. However, it is also conceivable to use other instruments if they are suitable for carrying out an assessment of the capacities to be assessed. In particular, so-called integrating measuring devices are used which are able to establish a current flow integral on the measuring path b . As will be explained in detail below, an evaluation of the capacitance by means of the MESSIN ⁇ struments during charging or during discharging of the capacity with the potentials. On the other hand, no evaluation is carried out on this measuring instrument during the complementary process, i.e. unloading or loading.
  • clock signals are preferably provided to control the switching elements, which are fed directly or indirectly to the switching elements and which can make it possible to periodically and synchronously apply the various relevant potentials to the electrodes of the capacitance to be evaluated.
  • These different clock signals can be generated independently of one another or have a common origin.
  • a common alternating clock voltage is present as a clock signal on the first switching element and on the second switching element and the first or second switching element are designed such that they can be switched or switched alternately by the alternating voltage.
  • the first and second S chaltelement having a pMOS and an nMOS transistor which are alternately teterrial ⁇ from the clock or AC voltage can be switched.
  • the circuit arrangement further comprises: a means for generating the clock signals applied to the switching elements and, if appropriate, a used alternating clock voltage from a master clock signal.
  • the common potential is equal to the first or the second potential.
  • the first or second potential represents an operating voltage that is inherent in the circuit arrangement anyway, and the other of the second or first potential is the ground.
  • the invention is further directed to a method for evaluating capacities, in particular using the circuit arrangement according to the invention described above, with the following steps:
  • the principle of the method according to the invention is based on the fact that after activation of a specific capacitance in a matrix of capacitances, one of the two electrodes of the capacitance to be evaluated (when using a switching arrangement according to the invention, the electrode connected to the test branch) is periodically recharged between two potentials. while the other electrode remains at a common potential and the capacity is only assessed on the basis of the charging or discharging process.
  • the activation is preferably carried out by switching on the part of the test branch leading to a specific capacity.
  • the switching on of the specific part of the test branch can take place by means of control switching elements integrated in this part of the test branch, a control switching element being provided for each of the dimensions.
  • the switching on of the specific part of the test branch can be carried out by control switches integrated in the test branch. sliding elements take place, wherein for at least one of the dimensions of a control switching element in that particular part of the fürzweigs is integrated, and for at least one of Dimension ⁇ versions a control switching element in a portion of the strigzweigs is integrated, which leads to a number of capacities and which also includes certain Part heard.
  • the at least one evaluation of the capacitance is preferably carried out by an instrument which is integrated in a first measuring path of the measuring branch.
  • This measuring instrument can be, for example, a current measuring device, so that the evaluation can be carried out by measuring a current flow integral through the first measuring path of the measuring branch during the charging or discharging of the capacitance.
  • the common potential applied according to the invention which must be carried over the measuring instrument during the evaluation, is preferably applied directly to the second electrode via a second measuring path of the measuring branch, while the at least one evaluation is not carried out.
  • the second electrode remains at the common potential throughout the entire time for a recharging to ensure.
  • the time profiles of the measurement during loading and unloading described above do not mean that at all times a measurement must be performed or must be applied to a ⁇ be-determined potential to the electrodes. Rather, it is also possible to apply potentials or to carry out measurements only over certain time intervals, while in other time intervals the arrangement used for the method according to the invention is completely decoupled from all external potentials and is therefore also not measured.
  • the capacity rating be done so that the entire charging or discharging process is detected.
  • the invention therefore preferably has the further step: second evaluation of the capacity during the process of unloading or charging, in which the at least one evaluation is not carried out.
  • the second evaluation of the capacitance is preferably carried out by a second instrument, which is integrated in a second measuring path, in order to ensure that the current flow derived from the first instrument during the complementary one
  • Operation of unloading or loading can flow through the second instrument.
  • the alternating application of the first and second potential to the first electrode can, for example, be carried out in a simple manner
  • the alternating application of the first and the second potential can take place by alternately connecting a first test path with a first potential and a second test path with a second potential to the first electrode.
  • This connection can take place, for example, by means of switching elements integrated in the test paths, for example switches or transistors.
  • the first measuring path and the second measuring path can be connected alternately to the second electrode. This connection can also be carried out by means of switching elements integrated in the measuring paths.
  • a particularly preferred embodiment of the method according to the invention leads to a further reduction in the measurement error, since the mismatch within the measurement branch is eliminated.
  • This procedure has the following steps:
  • the temporal correlation can be interchanged, for example, by shifting the phase of the AC voltage by 180 ° with respect to the period of the at least one evaluation, or by either interchanging the timing of the two measurement paths or applying the two potentials to the test branch ,
  • FIG. 2 shows an exemplary embodiment of a circuit arrangement according to the present invention
  • FIG. 3 shows a further exemplary embodiment of a simplified circuit arrangement according to the present invention.
  • FIG. 4 shows yet another exemplary embodiment of a circuit arrangement according to the present invention using AC voltage.
  • FIG. 1 shows a schematic illustration of a basic circuit which can be used in the invention.
  • the capacitances C p , ⁇ 2 and Cp, 34 shown in the figure represent the parasitic capacitances at the nodes N ⁇ 2 and N 34 which are unavoidable in real technical applications. Their effect on the function of the circuit, or the fact that these parasitic capacitances do not falsify the measurement result, is discussed in detail below.
  • FIG. 1 The principle shown in FIG. 1 is based on the fact that a first electrode of capacitance C ch ar. which is connected to the node N 12 of the test branch 2, is periodically reloaded between the voltage values V x and V 2 which are present on the two test paths, while the other, second electrode which is connected to the node N 3 -, the measuring branch 3 is connected to the common potential V remains 0 and the average value of the currency only ⁇ end of the charging (or depending on the definition and choice of Vi, V 2 and V 34 optionally also of Discharge) process occurring displacement current is measured, which occurs between the electrode of the capacitance, which is at constant potential V 0 , and the voltage source, which supplies this potential. This happens because
  • That one of the two electrodes of the capacitance (the one that is connected in the figure to the node N i2 of the test branch) by means of the switching elements (here the transistors T1 and T2) in a periodic change according to the timing diagram shown in the figure is connected to the potentials Vi and V 2 , so that the node N i2 is reloaded with the same period between these two potentials,
  • all the signals ⁇ i, ⁇ 2 , ⁇ 3 , and ⁇ 4 used for the control have the same frequency, but different phase positions and possibly also different duty cycle relationships.
  • the node N 34 is connected to the potential V 0 via exactly one of the two possible measurement paths before the start and after completion of a recharging process of the capacitance to be evaluated, so that the current measuring instrument 1 - depending on whether it is m on the same measurement path as the transistor T 3 or m lies in the same measuring path as the transistor T A - either measures the displacement current, which corresponds to the entire charging process, or measures the displacement current, which corresponds to the total discharge process of the capacitance C Char .
  • Frequency and duration of the "OPEN" phases of the signals ⁇ lr ⁇ 2 , ⁇ 3 , and ⁇ 4 are chosen so that the potential at node N ⁇ 2 during the reloading process safely reaches the full values V x and V 2 .
  • Tent intervals are also shown in the timing diagram of Figure la (dotted areas) in which one or the other or both of the two electrodes of the capaci ty ⁇ C C ar "float".
  • an exactly complementary control of the transistors T 2 and T 2 is also possible, ie that the closing of Ti (T 2 ) takes place simultaneously with the opening of T 2 (Ti) or that the control signal ⁇ _ is exactly complementary to Control signal ⁇ i is.
  • the choice of the potential V 0 has no influence on the measurement result, provided that C C har is independent of the voltage, ie it is an ideal capacitance.
  • the measurement result is also not of the value and of the other properties such.
  • the parasitic capacitance C p , ⁇ 2 is also recharged between the potentials V x and V 2 , but the current required for this flows exclusively through the transistors Ti and T 2 and through the sources Vi and V, but not via the transistors T. 3 and Ti, and therefore not via the current measuring instrument 1 and the source V 0 .
  • the displacement current flowing between node ⁇ 34 and voltage source V 0 is used here, and this is exactly the same as the current required for recharging the electrode of C ch ar connected to node N ⁇ ( ⁇ total current for reloading the node Ni, this measurand is not affected by the parasitic capacity C p , ⁇ 2 .
  • the parasitic capacitance C p , 34 is also not included in the measurement result, since, as a result of the constant potential at node N 4, it is not recharged during the entire measurement process and thus does not lead to the occurrence of a charge / discharge current which can be assigned to this capacity.
  • the value of C ch ar is obtained. by looking at the mean of the charging current I meas , ⁇ at a frequency f that is not too low
  • the measuring instrument has an integrating effect.
  • a mismatch in the levels of the signals ⁇ 3 and ⁇ can have a similar effect to a threshold voltage mismatch of the transistors T 3 and T 4 .
  • This effect is also compensated for by the above-mentioned measure or can be prevented from the outset in that the signals provided for controlling the gates of T 3 and T 4 are buffered on-chip by inverters, which in turn are operated with identical supply voltages.
  • the signals .phi..sub.i and ⁇ 2 of Figure la are here combined to form a signal ⁇ i2, the ert the common gate terminal of the transistors Ti and T 2 ansteu ⁇ .
  • the transistors Ti and T 2 this case form a simple CMOS inverter only for the control an input signal is required, which represents an advantageous simplification compared to the circuit from FIG.
  • the frequency and duration of the corresponding time intervals of the clock signals ⁇ i, ⁇ 2 . ⁇ 3 and ⁇ 4 , or ⁇ i2 , ⁇ 3 , and ⁇ 4 must be chosen in this concrete implementation, which is carried out with real components, so that a charge of the capacitance C C nar to the full value of Vi or a discharge the full value of V 2 is possible and that the respective displacement currents completely subside during the time intervals that T 3 or T 4 conducts.
  • FIG. 2 shows an embodiment of the invention
  • Circuit arrangement with an N x M matrix circuit based on a CMOS process in which the principle according to FIG. 1 was applied to a matrix arrangement.
  • Exactly one capacity or cell is selected within the matrix.
  • the corresponding logical complementary signals are present at the complementary outputs XOUT x and YOUT y for the switching paths 7, 9.
  • the transistors Tq,, y , and T ⁇ c rX , y in this cell are also both in the blocked state, so that they do not influence the recharging process.
  • all other (not selected * cells ") at least one of the transistors T 5 , x , y and T 6 , x , y , and at least one of the transistors T ⁇ , ⁇ , y and T 8 , x , y blocks, so that it is not possible to charge the capacitors within these cells via the transistors T ⁇ rX , y and T z , x , y , and there is at least one of the transistors T 9 , x , y and T ⁇ o, > , y within these cells in the conductive state, so that a defined potential (here V - V 0 ) lies over all capacities which are not selected.
  • Table 1 shows the result of a simulation of a 2 x 2 matrix which contains capacitances whose values scatter around
  • the technology parameters for the transistors Ti - T 4 originate from a 3.3 V CMOS process with an oxide thickness of 9 nm and a minimum channel length of 0.5 ⁇ m.
  • Table 1 Simulation of 2 x 2 matrix according to Figure 2.
  • T 1000 ns.
  • the order of the transistors T l X , y , T 5 , x , y and T 6 ,, y and ⁇ , y T 7 , x , y and T 8 , x , y can be interchanged. Furthermore, it is possible to execute the selection transistors with respect to one coordinate, ie either T 5 , x , y and T 8 , x , y or T 6 , x , y and T, x , y not individually within each cell, but for the whole Columns (first dimension) or for entire rows (second dimension).
  • FIG. 4 shows a further simplified embodiment of the present invention, in which the test branch 2 is fed by an AC voltage 4.
  • a control switching element depending SW ⁇ provided y (for the Y-decoder 11) and SW X, y (for the X-decoder 10), which m the har to the capacitance C , y , y leading test branch is integrated.
  • transistors instead of the individual control sliding elements, transistors here, it is also possible to transfer gates ⁇ (n parallel p) to use in each of which an n-MOS and p-MOS transistor ensure that the full voltage can be constructed.
  • the converted outputs to X out and Y out are also required for control.
  • mismatch of transistors T 3 and T 4 can lead to a certain falsification of the measurement result. Parameter variations of all other transistors used in Figures 2 and 3 are not critical. Furthermore, a mismatch with the levels of the signals ⁇ 3 and ⁇ 4 can also be understood here as a threshold voltage mismatch of the transistors T 3 and T 4 , which then also manifests itself as a small measurement error.
  • Ratio C char , ⁇ / C char , 2 should be set.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un ensemble circuit pour évaluer des condensateurs d'une matrice qui présente, dans au moins une dimension, une pluralité de rangées (12, 13) comportant au moins un condensateur (Cchar). Cet ensemble circuit présente une branche de contrôle (2) qui est raccordée à des premières électrodes de chacun des condensateurs (Cchar) à évaluer et qui permet d'appliquer deux potentiels différents (V1, V2) aux premières électrodes ; une branche de mesure (3) qui est raccordée à des deuxièmes électrodes de chacun des condensateurs (Cchar) à évaluer et qui présente un premier et un deuxième trajet de mesure auxquels est appliqué un potentiel commun (V0), le premier trajet de mesure présentant un instrument (1) qui sert à évaluer les condensateurs (Cchar), et le premier et le deuxième trajet de mesure pouvant être raccordés aux deuxièmes électrodes. Cet ensemble circuit est caractérisé par des moyens de commande qui peuvent commuter, de manière individuelle, chacun des condensateurs (Cchar) à évaluer sur les deux potentiels différents.
EP01913677A 2000-03-06 2001-02-16 Ensemble circuit et procede pour evaluer des condensateurs dans des matrices Withdrawn EP1264190A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10010888 2000-03-06
DE10010888A DE10010888B4 (de) 2000-03-06 2000-03-06 Schaltungsanordnung und Verfahren zum Bewerten von Kapazitäten in Matrizen
PCT/DE2001/000626 WO2001067119A1 (fr) 2000-03-06 2001-02-16 Ensemble circuit et procede pour evaluer des condensateurs dans des matrices

Publications (1)

Publication Number Publication Date
EP1264190A1 true EP1264190A1 (fr) 2002-12-11

Family

ID=7633706

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01913677A Withdrawn EP1264190A1 (fr) 2000-03-06 2001-02-16 Ensemble circuit et procede pour evaluer des condensateurs dans des matrices

Country Status (5)

Country Link
US (1) US6870373B2 (fr)
EP (1) EP1264190A1 (fr)
KR (1) KR20030009381A (fr)
DE (1) DE10010888B4 (fr)
WO (1) WO2001067119A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5342443A (en) * 1993-04-06 1994-08-30 Engelhard Corporation Method for bleaching kaolin clay

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10325863A1 (de) * 2003-06-06 2005-01-05 Infineon Technologies Ag Verfahren zum Herstellen eines integrierten Fingerabdrucksensors sowie Sensorschaltungsanordnung und Einspritzanordnung
CN100396055C (zh) * 2005-02-04 2008-06-18 华为技术有限公司 组播源过滤的处理方法
DE102005028507B3 (de) * 2005-06-17 2006-11-30 Texas Instruments Deutschland Gmbh Verfahren zur Kapazitäts-Spannungs-Wandlung und Kapazitäts-Spannungs-Wandler
US8736000B1 (en) * 2006-10-19 2014-05-27 Sandia Corporation Capacitive chemical sensor
DE102007025947B4 (de) * 2007-06-04 2009-02-26 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Integrierter kapazitiver Sensor
EP2201368B1 (fr) 2007-10-12 2015-07-22 Nxp B.V. Capteur, réseau de capteurs, et procédé de fonctionnement d'un capteur
EP2490221A1 (fr) * 2011-02-17 2012-08-22 Nanya Technology Corporation Cellule de mémoire et réseau de mémoire utilisant la cellule de mémoire
US9793220B2 (en) 2012-03-16 2017-10-17 Intel Deutschland Gmbh Detection of environmental conditions in a semiconductor chip
DE102013102557B4 (de) * 2012-03-16 2014-07-10 Intel Mobile Communications GmbH Erfassung von Umgebungsbedingungen in einem Halbleiterchip
CN104914325B (zh) * 2012-04-27 2017-07-11 上海三菱电梯有限公司 电容组内部连接方式辨识与参数设置方法
CN105224153A (zh) * 2015-08-31 2016-01-06 京东方科技集团股份有限公司 触控电极的电学性能检测装置和检测方法
CN110383089B (zh) * 2018-02-12 2021-11-05 深圳市汇顶科技股份有限公司 矩阵电容板及芯片测试方法
US11062763B2 (en) * 2019-04-09 2021-07-13 Micron Technology, Inc. Memory array with multiplexed digit lines
JP7294036B2 (ja) * 2019-09-30 2023-06-20 三菱電機株式会社 半導体試験装置、半導体装置の試験方法および半導体装置の製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2529475C3 (de) * 1975-07-02 1981-10-08 Ewald Max Christian Dipl.-Phys. 6000 Frankfurt Hennig Elektrische Schaltungsanordnung zum zeitabhängigen Messen von physikalischen Größen
US4783796A (en) * 1982-09-28 1988-11-08 Opcom PBX telephone call control system
US4728932A (en) * 1986-07-25 1988-03-01 Honeywell Inc. Detector for capacitive sensing devices
DE4237196C1 (de) * 1992-11-04 1994-02-10 Vega Grieshaber Gmbh & Co Verfahren und Anordnung zur Messung zumindest einer Kapazität
US6011859A (en) * 1997-07-02 2000-01-04 Stmicroelectronics, Inc. Solid state fingerprint sensor packaging apparatus and method
DE19833210C2 (de) * 1998-07-23 2000-06-21 Siemens Ag Verstärkerschaltung zur Kapazitätsmessung

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0167119A1 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5342443A (en) * 1993-04-06 1994-08-30 Engelhard Corporation Method for bleaching kaolin clay

Also Published As

Publication number Publication date
DE10010888A1 (de) 2001-09-27
US20030062905A1 (en) 2003-04-03
DE10010888B4 (de) 2004-02-12
WO2001067119A1 (fr) 2001-09-13
KR20030009381A (ko) 2003-01-29
US6870373B2 (en) 2005-03-22

Similar Documents

Publication Publication Date Title
DE112010002926B4 (de) Elektrometer mit breitem Dynamikbereich und schneller Reaktion
DE10010888B4 (de) Schaltungsanordnung und Verfahren zum Bewerten von Kapazitäten in Matrizen
DE69733789T2 (de) Hochauflösendes Stromversorgungsprüfsystem
DE102006055844B4 (de) Kapazitiver Sensor für eine physikalische Grösse, sowie Verfahren zu dessen Diagnose
DE10119080B4 (de) Verfahren und Schaltanordnung zur Widerstandsmessung
EP1636599B1 (fr) Ensemble circuit de commutation pour la stabilisation de potentiel sur un biocapteur et la numerisation du courant de mesure
DE102014103445A1 (de) Vorrichtung und Verfahren zur Bestimmung der Empfindlichkeit einer kapazitiven Sensorvorrichtung
EP0908736B1 (fr) Circuit pour déterminer la capacité ou la variation de capacité d'un circuit ou module capacitif
DE102011078334A1 (de) Verfahren und System zum Kalibrieren eines Shunt-Widerstands
DE19857689B4 (de) Strommeßschaltung für ein IC-Testgerät
EP1116957B1 (fr) Mesure de la capacité des structures dans un circuit intégré
DE102005024648A1 (de) Elektrische Schaltung zum Messen von Zeiten und Verfahren zum Messen von Zeiten
DE10204652B4 (de) Schaltkreis-Anordnung, elektrochemischer Sensor, Sensor-Anordnung und Verfahren zum Verarbeiten eines über eine Sensor-Elektrode bereitgestellten Stromsignals
DE19744152A9 (de) Schaltungsanordnung zur Erfassung der Kapazität bzw. einer Kapazitätsänderung eines kapazitiven Schaltungs- oder Bauelementes
EP0431686B1 (fr) Arrangement pour lire des détecteurs sensibles à la lumière ou aux rayons X
DE10156026B4 (de) Komparatorschaltung sowie Verfahren zum Bestimmen eines Zeitintervalls
DE69813948T2 (de) Methode zur Kompensation von Störungen in einer kapazitiven Schaltung und Anwendung in Matrixanzeigevorrichtungen
DE10010946C2 (de) Schaltungsanordnung und Verfahren zum Bewerten von Kapazitäten
DE10143034B4 (de) Vorrichtung zum Messen von Störkapazitäten auf einer integrierten Schaltung
DE10126298A1 (de) Verfahren und Vorrichtung zur Messung der Phasenverschiebung zwischen einem periodischen Signal und einem Ausgangssignal an einem Ausgang eines elektronischen Bauelements
WO2001014895A1 (fr) Circuit et procede d'evaluation de capacites
WO2015051824A1 (fr) Procédé pour l'étalonnage dans le temps d'une matrice de condensateurs connectée
DE102007009549B4 (de) Vorrichtung und Verfahren zur Messung der Stromaufnahme und der Kapazität eines Halbleiterbauelements
DE10321490B3 (de) Schaltkreis-Anordnung, elektrochemischer Sensor, Sensor-Anordnung und Verfahren zum Verarbeiten eines über eine Sensor-Elektrode bereitgestellten Stromsignals
DE112022001880T5 (de) Messen des spannungspegels eines spannungsknotens unter nutzung einer integrierten messschaltung

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20020805

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

REG Reference to a national code

Ref country code: DE

Ref legal event code: 8566

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20040430