WO2001014895A1 - Circuit et procede d'evaluation de capacites - Google Patents

Circuit et procede d'evaluation de capacites Download PDF

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Publication number
WO2001014895A1
WO2001014895A1 PCT/DE2000/001962 DE0001962W WO0114895A1 WO 2001014895 A1 WO2001014895 A1 WO 2001014895A1 DE 0001962 W DE0001962 W DE 0001962W WO 0114895 A1 WO0114895 A1 WO 0114895A1
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WO
WIPO (PCT)
Prior art keywords
circuit arrangement
branch
measuring
capacitance
evaluated
Prior art date
Application number
PCT/DE2000/001962
Other languages
German (de)
English (en)
Inventor
Roland Thewes
Carsten Linnenbank
Stephan Sauter
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2001014895A1 publication Critical patent/WO2001014895A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/27—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements

Definitions

  • the present invention relates generally to a circuit arrangement and a method for evaluating capacitances.
  • CMOS processes and other technologies it is necessary to determine the value of certain capacities, for example intended on-chip capacities for analog applications, and unintended but technically unavoidable parasitic apacitates, for example line coverings, line crossings at different metal levels and the like. Very high accuracy is desirable and necessary for certain applications.
  • the known circuit arrangements and concepts are therefore not able to permit a simple and precise determination of capacitances, for example on-chip capacitances, free of parasitic effects and the influence of non-ideal properties of the components used in the respective evaluator circuit. Furthermore, the previously known circuit arrangements are very complex in terms of circuitry.
  • the present invention is based on the object of providing a circuit arrangement and a method for evaluating capacitances with which the disadvantages described with regard to the prior art are avoided.
  • a circuit arrangement and a method are to be created the one that is easy to implement in terms of circuitry and delivers a highly precise result.
  • a circuit arrangement for evaluating capacities with a measuring branch which is connected via a node to an electrode of the capacitance to be evaluated, one or more parasitic capacitances being present in the measuring branch, and with a second branch for setting different operating modes of the circuit arrangement, which is connected via a node to the other electrode of the capacitance to be evaluated and which is designed such that within the measuring branch either the sum of the capacitance to be evaluated and the parasitic capacity (s) or but only the parasitic capacity (s) is / are or can be assessed.
  • a circuit arrangement for evaluating capacitances is provided, with a measuring branch which is connected via a node to an electrode of the capacitance to be evaluated, one or more parasitic capacitances being present in the measuring branch, and with a second branch for setting Different operating modes m of the circuit arrangement, which is connected via a node to the other electrode of the capacitance to be evaluated and which is designed such that the sum of the parasitic capacitance (s) and a defined, specifically variable portion of the capacitance to be evaluated are evaluated within the measuring branch will / will be or can be evaluated.
  • the circuit arrangements according to the invention make it possible in a simple manner in terms of circuit technology to be able to determine capacitances with high precision.
  • the circuit arrangements according to the invention are completely parasitic-compensated circuits which are particularly suitable for the highly precise evaluation of small on-chip capacitances and capacitance coatings.
  • the influence of parasitic large and non-ideal properties of the m of the invention measured circuitry components completely eliminated. This achieves a resolution that is clearly superior to all previously known methods and circuits.
  • the circuit arrangement according to the invention can advantageously be used in CMOS processes.
  • a basic idea of the present invention is to convert the capacitance value m to be determined into a linear current. Such a current can be measured particularly simply and precisely.
  • Both of the aforementioned embodiments of the circuit arrangement according to the invention are based on a principle which is described in detail below in connection with FIG. 1.
  • two different operating modes can be selected in the circuit arrangement according to the invention with the aid of corresponding additional circuits which are implemented in the second switching branch.
  • the actual characterization of the capacitance to be evaluated always takes place in the measuring branch.
  • the difference between the measured values from the measurements in the two operating modes which are referred to below as mode A and mode B, gives an error-free measured value for the capacity to be evaluated.
  • the sum of the parasitic capacitances and a clearly definable, specifically changeable portion ⁇ of the capacitance to be assessed to be measured within one and the same branch (measuring branch).
  • the difference between the measurement from the measurements in the two operating modes knowing the weighting factors ⁇ (mode A) and ⁇ (mode B), a measurement value for the capacity to be determined which is unaffected by the properties.
  • the circuit arrangements according to the invention can, for example, also generally be used as circuits for the — advantageously on-chip capacitance voltage or — advantageously — on-chip capacitance current conversion.
  • they can be used, for example, in m products, in which sensor signals that come from capacitive sensors have to be evaluated and processed.
  • sensors are, for example, capacitive pressure sensors, acceleration sensors or the like.
  • other possible uses for the circuit arrangements according to the invention are also conceivable.
  • the evaluation of the capacitance using the circuit arrangements according to the invention always leads to a mismatch-error-free measurement result. This enables a particularly precise assessment of even small capacities.
  • the circuit arrangements according to the invention preferably have, as will be explained in more detail with reference to FIGS. 3 to 8, a number of different switching elements.
  • the invention is not restricted to certain switching elements. However, at least some of the switching elements can advantageously be designed as transistors.
  • Figure 1 e general measuring principle for evaluating small capacitors with idealized components, which as
  • FIG. 2 shows a circuit arrangement known from the prior art, in which the influence of parasitic capacitances could be reduced;
  • FIG. 3a and 3b show a first embodiment of a circuit arrangement according to the invention, FIG. 3a representing operating mode A and FIG. 3b representing operating mode B;
  • FIG. 4 shows another embodiment of a circuit arrangement according to the invention
  • Figure 5 shows another embodiment of an inventive
  • FIG. 6a representing operating mode A
  • FIG. 6b representing operating mode B
  • Figure 7 shows another embodiment of an inventive
  • FIG. 8 shows an extended modification of the circuit arrangement according to FIG. 7.
  • FIG. 1 shows a circuit arrangement 60 for evaluating a capacitance 64.
  • This circuit arrangement 60 which is constructed from idealized components, illustrates the general principle according to which the circuit arrangements according to the invention function, as are shown, for example, in FIGS. 3 to 8.
  • the basic circuit with idealized components is shown in the upper area of FIG.
  • the circuit arrangement 60 has two changeover switches 62, 63, which are connected to a node N12.
  • the changeover switches 62, 63 are controlled via pulses S1 and S2.
  • a time slide is shown. shown that shows the temporal course of the pulses Sl and S2.
  • a capacity value converted into a current can be measured via a current measuring device 61.
  • one of the two electrodes of the capacitance to be evaluated is placed at a fixed potential.
  • the GND potential was chosen for this in FIG. However, any other fixed potential is also conceivable.
  • the other electrode of the capacitance 64 is connected to the potentials VDD and GND by means of the changeover switches 61, 62 m, so that the capacitance 64 to be evaluated is reloaded with the same period between these two potentials.
  • the mean value of the charging or discharging current is measured via the current measuring device 61, the current measuring device 61 either, as shown in FIG. 1, between the changeover switch 62 and VDD potential, or alternatively between the changeover switch 63 and GND -Potential can be arranged.
  • the change-over switches 62, 63 should be closed during the "CLOSED” phases and during the "OPEN” phases in the non-conductive state.
  • the pulses S1 and S2 used to control the changeover switches 62, 63 form so-called non-overlapping clocks, which is a necessary condition for the use of this idealized circuit arrangement 60.
  • the node N12 floats" and no current flows anywhere in the circuit arrangement 60.
  • the condition must be met that the duration of the "CLOSED" phases is at least in each case long enough that the capacitance 64 can be practically completely reloaded, which means that the node N12 has reached GND or VDD potential at the beginning of the "OPEN" phases.
  • Capacity 64 112 / (VDD x f) (lb)
  • the left-hand switching branch 72 of the circuit arrangement 70 according to FIG. 2 can be considered, that the changeover switch 62 by a transistor T1 (for example a p-MOS transistor) and the changeover switch 63 by a transistor T2 (for example an n-MOS) Transistor) was replaced.
  • T1 for example a p-MOS transistor
  • T2 for example an n-MOS Transistor
  • 71 parasitic capacitors Cpl and Cp2 are shown at node N12. These parasitic capacitances essentially consist of the capacities of the respective drain regions of the transistors against the substrate or the well.
  • equation (1) the circuit arrangement 70 results for the branch 72
  • Capacity 71 [112 / (VDD x f)] - (Cpl + Cp2) (2)
  • the measured value was between 25 and 30 fF, i.e. a macceptable if there is a large deviation of more than 100% from the actual value of the capacity to be assessed 71.
  • This circuit arrangement 70 has two identical switching branches 72, 74, which each have transistors T1, T2 and T3 and T4.
  • the transistors have the same dimensions and the same layout and each receive the same drive signals S1 and S2.
  • the capacitance 71 to be evaluated is only realized in one branch 72.
  • the branch 72 is used to determine the sum of the capacitance 71 to be evaluated and the parasitic capacitances Cpl and Cp2, while the other branch 74 is used to exclusively characterize the sum of the parasitic capacitances Cp3 and Cp4.
  • FIGS. 3 to 8 now describe exemplary embodiments of circuit arrangements according to the present invention with which these mismatch effects can be prevented, so that an error-free, highly accurate evaluation of capacities is possible.
  • FIG. 3 shows a first embodiment of the circuit arrangement 10 according to the invention for evaluating a capacitance 11.
  • This circuit arrangement 10 is based on the Principle of the circuit arrangement 60 shown in FIG. 1.
  • the circuit arrangement 10 has a measuring branch 20 which is connected via a node N12 to an electrode 12 of the capacitance 11 to be evaluated.
  • an measuring instrument is advantageously provided, in the present case an current measuring instrument 21.
  • the circuit arrangement 10 has a second branch 30.
  • the second branch 30 can be used to set two operating modes of the circuit arrangement 10, namely an operating mode A, as shown in FIG. 3a, and an operating mode B, as shown in FIG. 3b.
  • the second branch 30 is connected via a node N34 to the second electrode 13 of the capacitance 11 to be evaluated.
  • mode A and mode B the difference between the measured values from the measurements m in the two operating modes A and B (hereinafter referred to as mode A and mode B) results in an error-free measured value for the capacitance 11 to be evaluated.
  • the measurement is in each case carried out in the measuring branch 20 (the left branch of the circuit arrangements), consisting of one or more, preferably two, transistors T1 and T2 and the measuring instrument 21.
  • the measuring branch 20 the left branch of the circuit arrangements
  • an electrode 12 of capacitance 11 is connected to the common dram node N12 of transistors T1 and T2.
  • the second electrode 13 of the capacitance 11 to be evaluated is not opened fixed potential, but connected to the node N34 of the second branch 30, the second branch 30, preferably consisting of the transistors T3 and T4, except for the measuring instrument being constructed like the measuring branch 20. Alldmgs is an exact match Characteristics of the transistors of both branches are not required.
  • the gates of the transistors T3 and T4 can be switched so that T3 receives the same signal as T1, in the present case thus a clock signal S1, and T4 receives the same signal as T2, in the present case em Clock signal S2.
  • the circuit arrangement 10 is in mode A.
  • the gates of T3 and T4 it is also possible for the gates of T3 and T4 to be at VDD potential via the position of the changeover switches 31, 32, so that T3 m is closed and T4 m is open located. In this case, the circuit arrangement 10 is in mode B.
  • both electrodes 12, 13 of the capacitance 11 to be evaluated are switched in the same direction between VDD and GND potential, so that the state of charge of the capacitance 11 does not change.
  • Differences in the node potentials N12 and N34 during the recharging processes of the nodes N12 and N34 due to the mismatch of the transistors T1 and T3 or T2 and T4 have no disadvantageous effects. It is only important that the voltage drop across the capacitance 11 is identical at the point in time when the signal S1 goes to L potential (see lower area of FIG.
  • Capacity 11 (112 (mode A) - 112 (mode B)) / (VDD x f) (9)
  • FIG. 4 shows another embodiment of the circuit arrangement 10 according to the invention.
  • the circuit arrangement 10 has the basic structure and the basic function like that from FIG. 3.
  • the switch 31 is another embodiment of the circuit arrangement 10 according to the invention.
  • transistors T9 and T10 are sufficient, which can be designed as p-MOS transistors.
  • control signal SEL which together with one via an inverter
  • the transfer gates and pass transistors em- is coupled and controls the state of the transfer gates T5, T6 or T7, T8 and the pass transistors T9 and T10.
  • the selection of the respective operating modes A or B according to the basic circuit according to FIG. 3 can also be made by removing the changeover switches 31 and 32 and by replacing two clock signals S1 and S2 with four clock signals or Control signals Sl to S4 are used. Each of these clock and control signals S1 to S4 is fed directly to the gate of a respective transistor T1 to T4.
  • the mode of operation m mode A is analogous to the corresponding mode of operation m mode A in FIGS. 3 to 5, so that reference is made to the above statements in this regard.
  • the measured current 112 thus results in
  • both electrodes 12, 13 of the capacitor 11 are recharged in opposite phases.
  • the capacitance 11 to be evaluated now acts on this node N12, based on the known so-called Miller effect, weighted by the difference in the voltage swing on both electrodes 12, 13 of the capacitance 11.
  • the capacitance 11 can be assessed precisely.
  • the switching of the clocks or operating modes can be carried out by similar measures as described when the circuit arrangement 10 m FIG. 3 was changed to the circuit arrangements m FIGS. 4 and 5.
  • FIG. 20 m Another embodiment of a circuit arrangement 20 according to the invention is shown in FIG.
  • the two operating modes A and B each measure the sum of the parasitic capacitances and a clearly definable, specifically changeable portion of the capacity to be evaluated.
  • the difference between the measured values from the measurements in both operating modes when the weighting factors ⁇ (mode A) and ⁇ (mode B) are known, gives a measurement value for the capacitance to be evaluated which is unaffected by the properties of the parasitic capacitors.
  • the transistors T1 to T4 in both modes receive unchanged clock signals.
  • the circuit arrangement 10 has two voltage sources 34 35, which are connected to the node N34 via the transistors T3 and T4. Variable voltage values can be set via the voltage sources 34, 35.
  • Capacity 11 [112 (mode A) - 112 (mode B) / [( ⁇ (mode A) - ⁇ (mode B)) x VDD x f] (17)
  • transistors T3 and T4 match the selected voltages. can also switch through at full height at node N34.
  • FIG. 8 shows a further modification of the circuit arrangement 10 according to FIG. 7 in order to allow a completely free choice of the potentials V3 and V4 within the framework given by GND potential and VDD.
  • second switching branch 30 of the circuit arrangement 10 the connection from node N34 to the voltage sources

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Resistance Or Impedance (AREA)

Abstract

L'invention concerne un procédé et un circuit (10) permettant d'évaluer des capacités (11). L'invention a pour objet de permettre une évaluation de haute précision sans erreur de désadaptation même de petites capacités. A cet effet, une première valeur de capacité convertie en courant est mesurée dans une branche de mesure (20) du circuit (10), laquelle branche présente une série de capacités parasites (Cp1, Cp2). Par une deuxième branche (30) du circuit (10), on règle un premier mode de fonctionnement (mode A), dans lequel seules les capacités parasites (Cp1, Cp2) de la branche de mesure (20) sont évaluées. Ensuite, une deuxième valeur de capacité convertie en courant est mesurée dans la même branche de mesure (20) du circuit (10). Par la deuxième branche (30) du circuit (10), on règle un deuxième mode de fonctionnement (mode B), dans lequel est évaluée la somme de la capacité à évaluer (11) et des capacités parasites (Cp1, Cp2) de la branche de mesure (20). Ensuite, on détermine la capacité à évaluer (11) par soustraction des valeurs mesurées dans une seule et même branche de mesure (20) en mode A et en mode B.
PCT/DE2000/001962 1999-08-25 2000-06-15 Circuit et procede d'evaluation de capacites WO2001014895A1 (fr)

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DE19940357.0 1999-08-25
DE19940357 1999-08-25

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001067120A1 (fr) * 2000-03-06 2001-09-13 Infineon Technologies Ag Circuit et procede d'evaluation de capacites
EP1521090A2 (fr) * 2003-09-30 2005-04-06 Aisin Seiki Kabushiki Kaisha Dispositif de détection de capacitance
US9435802B2 (en) 2007-10-12 2016-09-06 Nxp B.V. Sensor, a sensor array, and a method of operating a sensor
WO2023169742A1 (fr) * 2022-03-08 2023-09-14 Robert Bosch Gmbh Capteur d'environnement et procédé de fonctionnement d'un capteur d'environnement

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
CHEN J C ET AL: "An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution", IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING,US,IEEE INC, NEW YORK, vol. 11, no. 2, 1 May 1998 (1998-05-01), pages 204 - 210, XP002096116, ISSN: 0894-6507 *
KORTEKAAS C: "ON-CHIP QUASI-STATIC FLOATING-GATE CAPACITANCE MEASUREMENT METHOD", PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES. (ICMTS),US,NEW YORK, IEEE, 5 March 1990 (1990-03-05), pages 109 - 113, XP000143982 *
MCGAUGHTY B W ET AL: "A SIMPLE METHOD FOR ON-CHIP, SUB-FEMTO FARAD INTERCONNECT CAPACITANCE MEASUREMENT", IEEE ELECTRON DEVICE LETTERS,US,IEEE INC. NEW YORK, vol. 18, no. 1, 1997, pages 21 - 23, XP000636030, ISSN: 0741-3106 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001067120A1 (fr) * 2000-03-06 2001-09-13 Infineon Technologies Ag Circuit et procede d'evaluation de capacites
EP1521090A2 (fr) * 2003-09-30 2005-04-06 Aisin Seiki Kabushiki Kaisha Dispositif de détection de capacitance
EP1521090A3 (fr) * 2003-09-30 2005-05-25 Aisin Seiki Kabushiki Kaisha Dispositif de détection de capacitance
US7015705B2 (en) 2003-09-30 2006-03-21 Aisin Seiki Kabushiki Kaisha Capacitance detection apparatus
US9435802B2 (en) 2007-10-12 2016-09-06 Nxp B.V. Sensor, a sensor array, and a method of operating a sensor
WO2023169742A1 (fr) * 2022-03-08 2023-09-14 Robert Bosch Gmbh Capteur d'environnement et procédé de fonctionnement d'un capteur d'environnement

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