WO2001014895A1

WO2001014895A1 - Circuit and method for evaluating capacitances

Info

Publication number: WO2001014895A1
Application number: PCT/DE2000/001962
Authority: WO
Inventors: Roland Thewes; Carsten Linnenbank; Stephan Sauter
Original assignee: Infineon Technologies Ag
Priority date: 1999-08-25
Filing date: 2000-06-15
Publication date: 2001-03-01

Abstract

The invention relates to a method and a circuit (10) for evaluating capacitances (11). The aim is to provide a means of evaluating even small capacitances without making mismatch errors. To this end, a first capacitance value that has been converted into a current is measured in a measuring branch (20) of the circuit (10), said branch having a series of parasitic capacitances (Cp1, Cp2). A first operating mode (mode A) in which only the parasitic capacitances (Cp1, Cp2) in the measuring branch (20) are measured is initiated by means of a second branch (30) of the circuit. A second capacitance value that has been converted into a current is then measured in the same measuring branch (20) of the circuit (10), a second operating mode (mode B) in which the sum of the capacitance (11) to be evaluated and the parasitic capacitances (Cp1, Cp2) in the measuring branch (20) is evaluated being initiated by means of the second branch (30) of the circuit (10). The capacitance (11) to be evaluated is then determined by finding the difference between the values measured in mode A and mode B in the same measuring branch (20).

Description

description

Circuitry and method for evaluating capacities

The present invention relates generally to a circuit arrangement and a method for evaluating capacitances.

For the parametric description of CMOS processes and other technologies, it is necessary to determine the value of certain capacities, for example intended on-chip capacities for analog applications, and unintended but technically unavoidable parasitic apacitates, for example line coverings, line crossings at different metal levels and the like. Very high accuracy is desirable and necessary for certain applications.

Various circuit arrangements are known from the prior art which convert the value of capacitances to be determined, for example on-chip capacitances, or the ratio of two or more capacitances to one another into a size which is easier to handle, such as current and / or voltage or current and / or implement voltage relationships. These sizes are generally relatively easy to measure and can be measured with high accuracy. A direct measurement of the capacitance values is not possible due to parasitic capacitances in external feed lines, pads and feed lines located on the chip or the like.

However, the circuit arrangements and methods known in the prior art for evaluating capacitances have a number of disadvantages. Parasitic capacitances and other non-ideal properties of the real components used in a respective evaluator circuit falsify the measurement result or have to be carried out with great circuitry wall as far as possible. A complete error suppression has not yet been possible.

Many of the known concepts normalize the measured values to a reference quantity that is also integrated, but not quantitatively known exactly. These concepts therefore only allow statements to be made about capacity relationships. Absolute value determinations, in particular of small capacitances, for example of line crossings or the like, which are indispensable for precise process parameterization, have so far not been possible with such circuit arrangements.

The known circuit arrangements and concepts are therefore not able to permit a simple and precise determination of capacitances, for example on-chip capacitances, free of parasitic effects and the influence of non-ideal properties of the components used in the respective evaluator circuit. Furthermore, the previously known circuit arrangements are very complex in terms of circuitry.

From a number of publications, for example "An On-Chip, Attofarad Interconnect Charge Based Capacitance Measurement (CBCM) Technique by Chen et al, IEDM 96, pages 69 to 72", "A Simple Method For On-Chip, Sub- Femto Farad Interconnect Capacitance Measurement by Chen et al, IEEE Electron Device Letters, Vol.18, No.l, January 1997, pages 21 to 23 "," An On-Chip, Interconnect Capacitance Characterization Method With Sub-Femto-Farad Resolution by Chen et al, Proc.IEEE 1997 Int. Conference on Microelectronic Test Structures, Vol.10, March 1997, pages 77 to 80 "and" An On-Chip, Interconnect Capacitance Characterization Method With Sub-Femto-Farad Resolution by Chen et al, IEEE Transactions on semiconductor Manufacturing, Vol.11, No.2, May 1998, pages 204 to 209 "describes a circuit arrangement for evaluating capacities with which the disadvantages described above with regard to the evaluability of capacities are already reduced can. This known circuit arrangement, which is explained in detail in connection with FIG. 2, has two identical switching branches, each of which has transistors with the same dimensions and the same layout and which each receive the same control signals in pairs. The capacitance to be assessed is only realized in one of the two switching branches. One switching branch is used to determine the sum of the capacitance to be evaluated and parasitic capacitances, while the other switching branch is used to determine only the

Characterize the sum of the parasitic capacities. The values determined in this way are then subtracted from one another, resulting in the value of the capacity to be assessed.

Even if this circuit arrangement has advantages compared to the concepts mentioned above, there are still a number of disadvantages with regard to the precise assessment of capacities even with this proposed solution.

It is known, for example, that components with the same dimensions, the same layout, the same orientation and the same topology in the environment have parameter variations due to stochastic causes. This means that, despite the same configuration, two adjacent components have differences in their electrical parameters. This effect is called mismatch. This mismatch effect cannot be avoided with the known circuit arrangement, so that errors also occur here when evaluating capacities, which is a considerable disadvantage particularly when evaluating small capacities.

Starting from the prior art mentioned, the present invention is based on the object of providing a circuit arrangement and a method for evaluating capacitances with which the disadvantages described with regard to the prior art are avoided. In particular, a circuit arrangement and a method are to be created the one that is easy to implement in terms of circuitry and delivers a highly precise result.

This object is achieved according to the first aspect of the invention by a circuit arrangement for evaluating capacities, with a measuring branch which is connected via a node to an electrode of the capacitance to be evaluated, one or more parasitic capacitances being present in the measuring branch, and with a second branch for setting different operating modes of the circuit arrangement, which is connected via a node to the other electrode of the capacitance to be evaluated and which is designed such that within the measuring branch either the sum of the capacitance to be evaluated and the parasitic capacity (s) or but only the parasitic capacity (s) is / are or can be assessed.

According to a second aspect of the invention, a circuit arrangement for evaluating capacitances is provided, with a measuring branch which is connected via a node to an electrode of the capacitance to be evaluated, one or more parasitic capacitances being present in the measuring branch, and with a second branch for setting Different operating modes m of the circuit arrangement, which is connected via a node to the other electrode of the capacitance to be evaluated and which is designed such that the sum of the parasitic capacitance (s) and a defined, specifically variable portion of the capacitance to be evaluated are evaluated within the measuring branch will / will be or can be evaluated.

The circuit arrangements according to the invention make it possible in a simple manner in terms of circuit technology to be able to determine capacitances with high precision. The circuit arrangements according to the invention are completely parasitic-compensated circuits which are particularly suitable for the highly precise evaluation of small on-chip capacitances and capacitance coatings. The influence of parasitic large and non-ideal properties of the m of the invention measured circuitry components completely eliminated. This achieves a resolution that is clearly superior to all previously known methods and circuits. The circuit arrangement according to the invention can advantageously be used in CMOS processes.

A basic idea of the present invention is to convert the capacitance value m to be determined into a linear current. Such a current can be measured particularly simply and precisely.

Both of the aforementioned embodiments of the circuit arrangement according to the invention are based on a principle which is described in detail below in connection with FIG. 1. In contrast to the principle described in FIG. 1, two different operating modes can be selected in the circuit arrangement according to the invention with the aid of corresponding additional circuits which are implemented in the second switching branch. The actual characterization of the capacitance to be evaluated always takes place in the measuring branch.

In the first exemplary embodiment, in the two different operating modes within one and the same circuit branch, namely the measuring branch, either the sum of the capacitance to be assessed and parasitic capacitances, or only the sum of the parasitic capacitances, is evaluated. Since the evaluation of the parasitic capacitances always takes place within the same branch (measuring branch), the difference between the measured values from the measurements in the two operating modes, which are referred to below as mode A and mode B, gives an error-free measured value for the capacity to be evaluated.

According to the second exemplary embodiment mentioned, it is possible for the sum of the parasitic capacitances and a clearly definable, specifically changeable portion α of the capacitance to be assessed to be measured within one and the same branch (measuring branch). Here, too, the difference between the measurement from the measurements in the two operating modes, knowing the weighting factors α (mode A) and α (mode B), a measurement value for the capacity to be determined which is unaffected by the properties.

The circuit arrangements according to the invention can, for example, also generally be used as circuits for the — advantageously on-chip capacitance voltage or — advantageously — on-chip capacitance current conversion. In this case, they can be used, for example, in m products, in which sensor signals that come from capacitive sensors have to be evaluated and processed. Such sensors are, for example, capacitive pressure sensors, acceleration sensors or the like. Of course, other possible uses for the circuit arrangements according to the invention are also conceivable.

Since the parasitic capacitances, which are determined in the measurements in the respective operating modes, always come from one and the same branch (measurement branch), the evaluation of the capacitance using the circuit arrangements according to the invention always leads to a mismatch-error-free measurement result. This enables a particularly precise assessment of even small capacities.

The circuit arrangements according to the invention preferably have, as will be explained in more detail with reference to FIGS. 3 to 8, a number of different switching elements. The invention is not restricted to certain switching elements. However, at least some of the switching elements can advantageously be designed as transistors.

Even if the invention is not limited to the use of transistors as switching elements, it should be explained for better understanding on the basis of such an embodiment. Gem _ä ß a third aspect of the invention there is provided em method for evaluating capacity. If the method is carried out using the first-mentioned embodiment of a circuit arrangement, it has the following steps according to the invention:

a) Measuring a first capacitance value converted into a current in the measuring branch of the circuit arrangement, whereby the first branch (mode A) of the circuit arrangement is set by the second branch of the circuit arrangement, with which only the parasitic capacitances in the measuring branch are evaluated ;

b) Measuring a second capacitance value converted into a current in the same measuring branch of the circuit arrangement, the second branch of the circuit arrangement em setting the second operating mode (mode B) of the circuit arrangement, which is the sum of the capacitance to be evaluated and that in the measuring branch Parasitic capacities is assessed; and

c) Determining the capacitance to be assessed by forming the difference between the values measured in steps a) and b).

Finally, according to the fourth aspect of the invention, another method for evaluating capacities is provided. If the method is carried out using the second-mentioned embodiment of a circuit arrangement, it has the following steps according to the invention:

a) Measuring a first capacitance value converted into a current in the measuring branch of the circuit arrangement, the first operating mode (mode A) of the circuit arrangement being set by the second branch of the circuit arrangement, m the sum of the parasitic capacitances in the measuring branch and a defined one , specifically changeable proportion of the capacity to be assessed is measured; b) Measuring a second current value in the same measuring branch of the circuit arrangement, whereby the second branch of the circuit arrangement sets a second operating mode (mode B) of the circuit arrangement, which is the sum of the parasitic capacitances in the measuring branch and a defined one , the portion of the capacitance to be assessed, which can be specifically implemented, is measured, the portions of the capacitance to be assessed in steps a) and b) being of different sizes; and

c) Determining the capacitance to be evaluated by forming the difference between the values measured in steps a) and b).

The process according to the invention makes it simple

In this way it is possible to evaluate the capacities to be evaluated with high precision. With regard to the advantages, effects, effects and the mode of operation of the method according to the invention, reference is also made in full to the explanations of the corresponding circuit arrangements according to the invention, and reference is hereby made.

Preferred embodiments of the circuit arrangements according to the invention and the method according to the invention for evaluating capacities result from the respective subclaims.

In the following, various preferred embodiments and features of the invention are to be presented and explained in general. In this connection, reference is also made to the accompanying drawing, in which each specific embodiment of the invention is shown as an example. Show it:

Figure 1 e general measuring principle for evaluating small capacitors with idealized components, which as

The basis for the present invention functions; FIG. 2 shows a circuit arrangement known from the prior art, in which the influence of parasitic capacitances could be reduced;

3a and 3b show a first embodiment of a circuit arrangement according to the invention, FIG. 3a representing operating mode A and FIG. 3b representing operating mode B;

FIG. 4 shows another embodiment of a circuit arrangement according to the invention;

Figure 5 shows another embodiment of an inventive

Circuitry;

6a and 6b yet another embodiment of a circuit arrangement according to the invention, FIG. 6a representing operating mode A and FIG. 6b representing operating mode B;

Figure 7 shows another embodiment of an inventive

Circuitry; and

8 shows an extended modification of the circuit arrangement according to FIG. 7.

1 shows a circuit arrangement 60 for evaluating a capacitance 64. This circuit arrangement 60, which is constructed from idealized components, illustrates the general principle according to which the circuit arrangements according to the invention function, as are shown, for example, in FIGS. 3 to 8. The basic circuit with idealized components is shown in the upper area of FIG. The circuit arrangement 60 has two changeover switches 62, 63, which are connected to a node N12. The changeover switches 62, 63 are controlled via pulses S1 and S2. In the lower area of FIG. 1, a time slide is shown. shown that shows the temporal course of the pulses Sl and S2. A capacity value converted into a current can be measured via a current measuring device 61.

As can be seen from FIG. 1, one of the two electrodes of the capacitance to be evaluated is placed at a fixed potential. The GND potential was chosen for this in FIG. However, any other fixed potential is also conceivable. The other electrode of the capacitance 64 is connected to the potentials VDD and GND by means of the changeover switches 61, 62 m, so that the capacitance 64 to be evaluated is reloaded with the same period between these two potentials. The mean value of the charging or discharging current is measured via the current measuring device 61, the current measuring device 61 either, as shown in FIG. 1, between the changeover switch 62 and VDD potential, or alternatively between the changeover switch 63 and GND -Potential can be arranged.

According to the time diagram shown in FIG. 1, the change-over switches 62, 63 should be closed during the "CLOSED" phases and during the "OPEN" phases in the non-conductive state. The pulses S1 and S2 used to control the changeover switches 62, 63 form so-called non-overlapping clocks, which is a necessary condition for the use of this idealized circuit arrangement 60. During the intervals in which both changeover switches 62, 63 are open, the node N12 "floats" and no current flows anywhere in the circuit arrangement 60. Taking into account the finite conductance of the switches 62, 63 in the closed state, the condition must be met that the duration of the "CLOSED" phases is at least in each case long enough that the capacitance 64 can be practically completely reloaded, which means that the node N12 has reached GND or VDD potential at the beginning of the "OPEN" phases.

The time average of the current 112 results for this ideal circuit arrangement 60 112 = capacity 64 x VDD xf (la)

where f = 1 / T and T is the period. This results in the capacity to be assessed

Capacity 64 = 112 / (VDD x f) (lb)

If the changeover switches 62, 63 are now replaced by real components, the parasitic capacitances of these components play an important role.

As an example, the left-hand switching branch 72 of the circuit arrangement 70 according to FIG. 2 can be considered, that the changeover switch 62 by a transistor T1 (for example a p-MOS transistor) and the changeover switch 63 by a transistor T2 (for example an n-MOS) Transistor) was replaced. As can be seen from FIG. 2, in addition to the two transistors T1 and T2 mentioned and the capacitance to be evaluated, 71 parasitic capacitors Cpl and Cp2 are shown at node N12. These parasitic capacitances essentially consist of the capacities of the respective drain regions of the transistors against the substrate or the well. Instead of equation (1), the circuit arrangement 70 results for the branch 72

Capacity 71 = [112 / (VDD x f)] - (Cpl + Cp2) (2)

A simulation with concrete dimensioned elements was carried out, which gave the following results. The

Simulation was carried out on the basis of a 0.5μm CMOS process with minimum dimensions for both transistors T1 and T2, i.e. with a width W = 0.7μm and a length L = 0.5μm, and with a capacitance to be assessed of 10fF. For the total capacity determined from stream 112, the measured value was between 25 and 30 fF, i.e. a macceptable if there is a large deviation of more than 100% from the actual value of the capacity to be assessed 71.

To solve this problem, a circuit arrangement as shown in FIG. 2 has been developed in the prior art, as was also described in the description. This circuit arrangement 70 has two identical switching branches 72, 74, which each have transistors T1, T2 and T3 and T4. The transistors have the same dimensions and the same layout and each receive the same drive signals S1 and S2. However, the capacitance 71 to be evaluated is only realized in one branch 72. The branch 72 is used to determine the sum of the capacitance 71 to be evaluated and the parasitic capacitances Cpl and Cp2, while the other branch 74 is used to exclusively characterize the sum of the parasitic capacitances Cp3 and Cp4. Formulated analytically results for the currents 112 and 134 measured with the current measuring devices 73 and 75

112 (capacity 71 + Cpl + Cp2) x VDD x f

such as

134 = (Cp3 + Cp4) x VDD x f (4th

The difference between the two equations leads to

112-134 = (capacity 71 + Cpl + Cp2) - (Cp3 + Cp4) x VDD x f (5;

Under the assumption

Cpl + Cp2 = Cp3 + Cp4 (6a)

respectively

(Cpl + Cp2) / (Cp3 + Cp4) = _r = 1 (with "r" for "ratio") (6b) the exact value of the capacitance 71 to be evaluated can thus be determined from the measurement of both currents in accordance with equation (5).

As has already been explained in the context of the description, even components with the same dimensions and configuration have differences in their electrical parameters due to the mismatch effect.

The mismatch effect of the transistors T1, T2, T3 and T4 of the circuit arrangement 70 according to FIG. 2 means that the value "r" in equation (6b) assumes different values for multiple (identical implementation) of the circuit arrangement 70, which values are around 1 move around. Thus, the mismatch

Properties of the transistors in FIG. 2 or the parasitic capacitances associated with these transistors, the achievable resolution of this circuit arrangement for characterizing, in particular, small capacitances 71 in a negative manner. It follows from the fact that mismatch cannot be avoided that this measurement error is an inherent and Unavoidable property of the known concept according to FIG. 2, in which in a first branch 72 of the circuit arrangement 70 the sum of the capacitance 71 to be evaluated and the parasitic capacitances Cpl and Cp2 of this branch 72 and in the other branch 74 only the parasitic capacitances Cp3 and Cp4 des second branch can be determined.

FIGS. 3 to 8 now describe exemplary embodiments of circuit arrangements according to the present invention with which these mismatch effects can be prevented, so that an error-free, highly accurate evaluation of capacities is possible.

FIG. 3 shows a first embodiment of the circuit arrangement 10 according to the invention for evaluating a capacitance 11. This circuit arrangement 10 is based on the Principle of the circuit arrangement 60 shown in FIG. 1. The circuit arrangement 10 has a measuring branch 20 which is connected via a node N12 to an electrode 12 of the capacitance 11 to be evaluated. There are 20 em or more, preferably two parasitic capacitors Cpl and Cp2 in the measuring branch, which are advantageously associated with corresponding transistors T1 and T2. To measure a current 112 in the measuring branch 20, an measuring instrument is advantageously provided, in the present case an current measuring instrument 21.

Furthermore, the circuit arrangement 10 has a second branch 30. The second branch 30 can be used to set two operating modes of the circuit arrangement 10, namely an operating mode A, as shown in FIG. 3a, and an operating mode B, as shown in FIG. 3b. The second branch 30 is connected via a node N34 to the second electrode 13 of the capacitance 11 to be evaluated.

By selecting a suitable operating mode, either the sum of the capacitance 11 to be evaluated and the parasitic capacitances Cpl and Cp2 or only the sum of the parasitic capacitances can be evaluated within the same measuring branch 20. Since the evaluation always takes place within the measuring branch 20, the difference between the measured values from the measurements m in the two operating modes A and B (hereinafter referred to as mode A and mode B) results in an error-free measured value for the capacitance 11 to be evaluated.

In FIG. 3 and all other FIGS. 4 to 8, the measurement is in each case carried out in the measuring branch 20 (the left branch of the circuit arrangements), consisting of one or more, preferably two, transistors T1 and T2 and the measuring instrument 21. Similar to FIG. 2, in FIG. 3 an electrode 12 of capacitance 11 is connected to the common dram node N12 of transistors T1 and T2. However, the second electrode 13 of the capacitance 11 to be evaluated is not opened fixed potential, but connected to the node N34 of the second branch 30, the second branch 30, preferably consisting of the transistors T3 and T4, except for the measuring instrument being constructed like the measuring branch 20. Alldmgs is an exact match Characteristics of the transistors of both branches are not required.

By means of two changeover switches 31 and 32, the gates of the transistors T3 and T4 can be switched so that T3 receives the same signal as T1, in the present case thus a clock signal S1, and T4 receives the same signal as T2, in the present case em Clock signal S2. In this case, the circuit arrangement 10 is in mode A. However, it is also possible for the gates of T3 and T4 to be at VDD potential via the position of the changeover switches 31, 32, so that T3 m is closed and T4 m is open located. In this case, the circuit arrangement 10 is in mode B.

In operating mode A, both electrodes 12, 13 of the capacitance 11 to be evaluated are switched in the same direction between VDD and GND potential, so that the state of charge of the capacitance 11 does not change. Differences in the node potentials N12 and N34 during the recharging processes of the nodes N12 and N34 due to the mismatch of the transistors T1 and T3 or T2 and T4 have no disadvantageous effects. It is only important that the voltage drop across the capacitance 11 is identical at the point in time when the signal S1 goes to L potential (see lower area of FIG. 3b), that is to say the beginning of the "CLOSED" phase of T1 and T3 with the voltage drop across the capacitance 11 at the time at which the signal S1 goes back to H potential, that is to say when the "CLOSED" phase of T1 and T3 ends. This general condition means that no net current flows through the measuring element 21, which measures the current 112, which contributes to the recharging of the capacitance 11. In mode A, the result of the measurement is the current

112 (mode A (= (Cpl + Cp2) x VDD x f (7)

while mode B results

112 (mode B) = (capacity 11 + Cpl + Cp2) x VDD x f (8)

It is important that m two equations (7) and (8) have the same parasite sizes - different from m the equations (3) and (4) according to the prior art - so that the subtraction of equation (8) and equation (7) leads to a mismatch error-free result for the capacitance 11:

Capacity 11 = (112 (mode A) - 112 (mode B)) / (VDD x f) (9)

FIG. 4 shows another embodiment of the circuit arrangement 10 according to the invention. The circuit arrangement 10 has the basic structure and the basic function like that from FIG. 3. However, the switch 31

32 from FIG. 3 has been replaced by a number of transfer gates T5, T6, T7, T8 and pass transistors T9 and T10. The coupling of the gates of T3 and T4 to the signals S1 and S2 in mode A is carried out here via the transfer gates T6 and T5 or T8 and T7, which are preferably designed as n- and p-MOS transistors ensures that the clock signals S1 and S2 m are transmitted in full amplitude.

For the coupling of gates T3 and T4 to VDD potential in mode B, on the other hand, transistors T9 and T10 are sufficient, which can be designed as p-MOS transistors.

The selection of the respective operating mode takes place via a control signal SEL, which together with one via an inverter

33 generated signal complementary to the SEL signal via connections 40 the transfer gates and pass transistors em- is coupled and controls the state of the transfer gates T5, T6 or T7, T8 and the pass transistors T9 and T10.

As shown in the circuit arrangement 10 according to FIG. 5, the selection of the respective operating modes A or B according to the basic circuit according to FIG. 3 can also be made by removing the changeover switches 31 and 32 and by replacing two clock signals S1 and S2 with four clock signals or Control signals Sl to S4 are used. Each of these clock and control signals S1 to S4 is fed directly to the gate of a respective transistor T1 to T4.

In mode A, the signals S3 and S4 must then be selected equal to the signals S1 and S2, that is to say S1 = S3 and S2 = S4. In mode B, the signals S3 and S4 are set to H potential.

FIG. 6 shows a circuit arrangement 10 in which the capacitance 11 to be determined in mode A, like in FIG. 3, makes no contribution to current 112, while in mode B it has a weighting α, in the present case preferably a weighting α = 2 , is applied. The mode of operation m mode A is analogous to the corresponding mode of operation m mode A in FIGS. 3 to 5, so that reference is made to the above statements in this regard. The measured current 112 thus results in

112 (mode A) = (Cpl + Cp2) x VDD x f (10)

In mode B, as can be seen from FIG. 6, both electrodes 12, 13 of the capacitor 11 are recharged in opposite phases. If the node N12 located in the measuring branch 20 is referred to as the input node, the capacitance 11 to be evaluated now acts on this node N12, based on the known so-called Miller effect, weighted by the difference in the voltage swing on both electrodes 12, 13 of the capacitance 11. correct ¹ - normalized to the stroke at the input node N12. Since the stroke at the input node N12 during the charging phase of the node N12, that is to say during the phase in which the current 112 is generated by the measuring instrument 21, is VDD, but the stroke at the node N34 is equal to -VDD, one obtains the weighting factor

α = (VDD - (-VDD)) / VDD = 2 (11)

This results in mode B for the current m

112 (mode B) = (2 x capacity 11 + Cpl + Cp2) x VDD x f (12)

and as a final result for the capacity to be assessed 11

Capacity 11 = (112 (mode B) -112 (mode A)) / (2 x VDD x f) (13)

Since the weighting factor is known, the capacitance 11 can be assessed precisely. The switching of the clocks or operating modes can be carried out by similar measures as described when the circuit arrangement 10 m FIG. 3 was changed to the circuit arrangements m FIGS. 4 and 5.

Another embodiment of a circuit arrangement 20 according to the invention is shown in FIG. In this case, within the measuring branch 20 m, the two operating modes A and B each measure the sum of the parasitic capacitances and a clearly definable, specifically changeable portion of the capacity to be evaluated. Here, too, the difference between the measured values from the measurements in both operating modes, when the weighting factors α (mode A) and α (mode B) are known, gives a measurement value for the capacitance to be evaluated which is unaffected by the properties of the parasitic capacitors.

In the circuit arrangement 10 according to FIG. 7, the capacitance 11 to be assessed and the parasitic Capacity capacitors Cpl and Cp2 in that when measuring the current 112 m, the different operating modes A and B receive the capacitance 11 with different weightings. In contrast to the circuit arrangements described above, the transistors T1 to T4 in both modes receive unchanged clock signals. The circuit arrangement 10 has two voltage sources 34 35, which are connected to the node N34 via the transistors T3 and T4. Variable voltage values can be set via the voltage sources 34, 35.

Depending on the choice of voltages V3 and V4, the measuring current results

112 = [capacity 11 x (VDD- (V3-V)) + (Cp3 + Cp4) x VDD] x f (14)

or using the notation with the weighting factor α

112 = (α x capacity 11 + Cp3 + Cp4) x VDD x f (15)

With

α [VDD- (V3-V4)] / VDD = 1 - (V3-V4) / VDD: i ^β :

In the operating modes A and B, different value pairs are selected for the voltages V3 and V4, so that m modes A and B result in different weighting factors α according to equation (16). Subtracting equation (15) for both modes finally gives

Capacity 11 = [112 (mode A) - 112 (mode B) / [(α (mode A) - α (mode B)) x VDD x f] (17)

When selecting voltages V3 and V4, care must be taken that transistors T3 and T4 match the selected voltages. can also switch through at full height at node N34.

Some exemplary examples of the selection of these two potentials in modes A and B are described below:

Mode A: V3 = VDD; V4 = GND potential = 0; (=> α = 0) (18a) mode B: V3 = V4 = VDD / 2; (=> α = 1) (18b)

or

Mode A: V4 = GND potential = 0; V3 = 0.5xVDD; (=> α = 0.5)

(19a) Mode B: V4 = GND potential = 0; V3 = 0.75xVDD; (=> α = 0.25)

(19b)

the invention is not restricted to the examples mentioned.

The choice V3 = GND potential = 0; V4 = VDD; (=> α = 2), on the other hand, is not possible since the transistor T4, which is preferably designed as an n-MOS transistor, is not able to pass on the VDD potential of the voltage source 35 to node N34 without voltage loss, either transistor T3, which is preferably designed as a p-MOS transistor, is not able to pass on the GND potential of voltage source 34 to node N34 without voltage loss.

Finally, FIG. 8 shows a further modification of the circuit arrangement 10 according to FIG. 7 in order to allow a completely free choice of the potentials V3 and V4 within the framework given by GND potential and VDD. In the right, second switching branch 30 of the circuit arrangement 10, the connection from node N34 to the voltage sources

34, 35 each made via transfer gates T3 and transistor 38 or T4 and transistor 39, which m each Case are able to guarantee full level at node N34. The signals required for the transistors 38 and 39 newly introduced compared to FIG. 7 are provided by inversion of the signals S1 and S2 via the inverters 36 and 37.

Claims

claims

1. Circuit arrangement for evaluating capacitances (11), with a measuring branch (20) which is connected via a node (N12) to an electrode (12) of the capacitance (11) to be evaluated, wherein in the measuring branch (20) em or more Parasitic capacitances (Cpl, Cp2) are present, and with a second branch (30) for setting different operating modes m of the circuit arrangement (10), which is connected via a node (N34) to the other electrode (13) of the capacitance (11 ) is connected and is designed such that within the measuring branch (20) either the sum of the capacitance (11) to be assessed and the parasite capacity (s) (Cpl, Cp2) or only the parasite capacity (s) (Cpl, Cp2) is evaluated will / will be or can be evaluated.

2. Circuit arrangement for evaluating capacitances (11), with a measuring branch (20) which is connected via a node (N12) to an electrode (12) of the capacitance (11) to be evaluated, wherein in the measuring branch (20) em or more Parasitic capacitances (Cpl, Cp2) are present, and with a second branch (30) for setting different operating modes m of the circuit arrangement (10), which ver (N34) with the other electrode (13) of the capacitance (11) to be evaluated - Bound and which is designed such that within the measuring branch (20) the sum of the parasitic capacity (s) (Cpl, Cp2) and a defined, specifically changeable portion (α) of the capacity (11) to be evaluated is / are evaluated or is / are assessable.

3rd Circuit arrangement according to Claim 1 or 2, characterized in that the measuring branch (20) has one or more, preferably two, switching elements (T1, T2) which are connected to the node (N12).

4. Circuit arrangement according to one of claims 1 to 3, d a d u r c h g e k e n n z e i c h n e t that in the measuring branch (20) em measuring instrument (21), in particular em current measuring instrument, is provided.

5. Circuit arrangement according to one of claims 1 to 4, d a d u r c h g e k e n n z e i c h n e t that the second branch (30) has em or more, preferably two, switching elements (T3, T4) which is / are connected to the node (N34).

6. Circuit arrangement according to one of claims 3 to 5, d a d u r c h g e k e n n z e i c h n e t that for driving the switching elements (Tl, T2; T3, T4)

Clock signals, preferably two or four clock signals (S1, S2, S3, S4) are provided, which are guided directly and / or indirectly in the switching elements (T1, T2; T3, T4).

7. Circuit arrangement according to claim 5 or 6, if jerk-related to claim 1, so that the second branch (30) has one or more, preferably two, switches (31, 32) for switching the switching elements (T3, T4).

8. Circuit arrangement according to claim 7, so that the switch or switches (31, 32) is / are each formed from one or more switching elements (T5 to T10).

9. Circuit arrangement according to claim 8, characterized in that for setting the operating mode of the circuit arrangement (10) e control signal (SEL) and em inverter (33) is provided for generating a signal complementary to the control signal (SEL), the signal (s) ) via connections (40) m the switching elements (T5 to T10) are / are or can be / are uncoupled.

10. Circuit arrangement according to one of claims 5 to 9, as far as jerk-related to claim 2, characterized in that one or more, preferably two, voltage sources (34, 35) is / are provided in the second branch (30), which via the or the switching elements (T3, T4) is / are connected to the node (N34).

11. Circuit arrangement according to claim 10, so that the voltage source (s) (34, 35) is / are additionally connected to the node (N34) via each e switching element (38, 39) and one inverter (36, 37).

12. Circuit arrangement according to one of claims 3 to 11, d a d u r c h g e k e n n z e i c h n e t that at least individual switching elements (Tl to T10, 38, 39) are designed as transistors.

13. Circuit arrangement according to claim 12, that the switching elements (T5 to T8) are designed as transfer gates and / or the switching elements (T9, T10) are designed as pass transistors.

14. A method for evaluating capacities using a circuit arrangement according to one of claims 1 and 3 to 13, with the following steps:

a) Measuring a first capacitance value converted into a current in the measuring branch of the circuit arrangement, the first operating mode (mode A) of the circuit arrangement being set by the second branch of the circuit arrangement will be evaluated only the parasitic capacitances in the measuring branch;

b) measuring a second capacitance value converted into a current in the same measuring branch of the circuit arrangement, the second operating mode (mode B) of the circuit arrangement being set by the second branch of the circuit arrangement, the sum of the capacitance to be evaluated and that in the measuring branch Parasitic capacities is assessed; and

15. The method according to claim 14, so that the different operating modes for the circuit arrangement are set via one or more changeover switches, each of which switches one or more switching elements in the second branch of the circuit arrangement.

16. The method according to claim 14, characterized in that the setting of the different operating modes for the circuit arrangement via one or more changeover switches, which are each formed from one or more switching elements, the setting of the respective operating mode via em control signal, which is carried out together with a controls the state of the switching element or elements via an inverter-generated complementary signal of the control signal.

17. The method according to claim 14, characterized in that the setting of the different operating modes for the circuit arrangement over a number of clock signals. follows, with each clock signal at each em em scarf Tele ^¬ ment of the measuring branch and the second branch is guided.

18. The method according to any one of claims 14 to 17, so that the capacity values evaluated according to step b) in operating mode B are loaded with a weighting factor (α).

19. A method for evaluating capacities using a circuit arrangement according to one of claims 2 to 113, comprising the following steps:

a) measuring a first capacitance value converted into a current in the measuring branch of the circuit arrangement, the first branch mode (mode A) of the circuit arrangement being set by the second branch of the circuit arrangement, m the sum of the parasitic capacitances in the measuring branch and a defined, specifically changeable proportion of the capacity to be assessed is measured;

b) Measuring a second capacitance value converted into a current in the same measuring branch of the circuit arrangement, the second branch of the circuit arrangement em setting the second operating mode (mode B) of the circuit arrangement, the sum of the parasitic capacitances in the measuring branch and a defined one , a specifically variable proportion of the capacity to be assessed is measured, the proportions of the capacity to be assessed m in steps a) and b) being of different sizes; and

20. The method according to claim 19, characterized in that the m steps a) and b) of different sizes, defined portions of the capacitance to be evaluated are set via one or more, preferably two, variable voltage sources in the second branch of the circuit arrangement.