EP1248978A2 - Memoire de donnees - Google Patents

Memoire de donnees

Info

Publication number
EP1248978A2
EP1248978A2 EP01900126A EP01900126A EP1248978A2 EP 1248978 A2 EP1248978 A2 EP 1248978A2 EP 01900126 A EP01900126 A EP 01900126A EP 01900126 A EP01900126 A EP 01900126A EP 1248978 A2 EP1248978 A2 EP 1248978A2
Authority
EP
European Patent Office
Prior art keywords
data
memory
address
redundancy
data memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01900126A
Other languages
German (de)
English (en)
Inventor
Steffen Paul
Volker Schöber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1248978A2 publication Critical patent/EP1248978A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage

Definitions

  • the invention relates to a data storage device with a short access time, which has a main data storage device and a redundancy data storage device for replacing faulty data storage units of the main data storage device.
  • data memories as well as the degree of integration of data memories is increasing due to the increased requirements, especially with customer-specific ASIC circuits. Due to the necessary high degree of integration and the necessary large memory sizes, in addition to the functioning data storage units, occasionally faulty data storage units are also generated in the course of the complex manufacturing process. To find such faulty memory cells, data memories are subjected to a memory test after they have been produced, in which test data patterns are applied to the memory, and it is then checked whether the data read out correspond to an expected test data readout pattern.
  • data storage units are increasingly providing redundant storage areas which serve to replace faulty data storage units.
  • additional storage rows and replacement storage columns are additionally installed on the data storage chip.
  • Figure 1 shows schematically the structure of a data memory with a redundant memory area according to the prior art.
  • an address comparison is first carried out in the redundancy logic and then, if the addressed data storage unit is not defective, the addressed data storage unit within the data memory is accessed or, if the addressed data storage unit is recognized as a defective data storage unit, a replacement data storage unit accessed within the redundant memory.
  • a disadvantage of the prior art arrangement shown in FIG. 1 is that the redundant memory is integrated in the original data memory.
  • the data memory In the case of a predetermined data memory of a predetermined size, for example a RAM memory with one megabyte of storage space, the data memory must be adapted accordingly in terms of circuitry in order to integrate a redundant memory space.
  • the memory shown in FIG. 1 also has the serious disadvantage that the memory access to a data storage unit takes a relatively long time.
  • the memory access time T access f to a data storage unit within the memory shown in FIG. 1 is the sum of the address comparison time T v that is required for address comparison within the redundancy logic and the access time to the data memory T ZD .
  • the invention provides a data store with a main data store consisting of a plurality of data storage units, a redundancy data store consisting of several redundancy data storage units for replacing faulty data storage units of the main data store, and with a redundancy control logic for control access to the redundancy data memory, the main data memory and the redundancy data memory being connected to a data bus in parallel with one another via data lines, the main data memory and the redundancy control logic being connected in parallel with one another via address lines to an address bus for addressing data storage units in the data Memory are connected.
  • An advantage of the data memory according to the invention is that it has a redundant memory without that the main data memory can be adapted in terms of circuitry, etc.
  • Another advantage of the data memory with the features specified in patent claim 1 is its ease of testing, since the redundancy data memory can be tested immediately when a test pattern is created to check the functionality of the data memory.
  • the redundancy control logic has an address memory with a plurality of address memory units which store addresses of faulty data memory units in the main data memory.
  • the address storage units are associative storage units CAM, which are connected to the address bus, the associative storage units being provided for enabling associated redundancy data storage units of the redundancy data store.
  • the address storage units are address storage registers.
  • the address storage registers preferably each have a flag bit that indicates whether the content of the address storage register is valid.
  • the redundancy control logic preferably has a plurality of comparators, each of which is connected to an address memory register and the address bus and releases an associated redundancy data storage unit of the redundancy data memory. switch when the address present in the address bus matches the address stored in the address memory register.
  • the redundancy control logic preferably controls a first multiplexer for reading out data from the main data store or from the redundancy data store.
  • the main data store, the redundancy data store and the redundancy control logic are connected in parallel to one another to a control bus for controlling the read or write access to the data store.
  • the address memory is connected to a programmed, non-erasable address read-only memory for the permanent storage of addresses of faulty data storage units of the main data memory.
  • the redundancy control logic preferably controls a second multiplexer which is connected on the input side to the redundancy data storage units of the redundancy memory and is used for reading data from one of the redundancy data storage units.
  • the redundancy data storage units of the redundancy memory are preferably data registers.
  • the main data memory is a RAM data memory. In a further preferred embodiment, the main data memory is an SRAM data memory.
  • An address of a defective data storage unit of the main data memory can preferably be read out in an address storage unit of the address memory from a memory test logic integrated in the data memory, from a test machine or from the address read-only memory and can be written into the address memory unit.
  • Figure 1 shows a data memory with redundant memory according to the prior art
  • FIG. 2 shows a block diagram of the data memory according to the invention with a redundancy data memory
  • FIG. 3 shows a first embodiment of the data memory according to the invention
  • Figure 4 shows a second embodiment of the data memory according to the invention
  • FIG. 5 shows a flowchart which represents the testing and the address reprogramming in the data memory according to the invention
  • FIG. 2 shows a block diagram of the data memory 1 according to the invention.
  • the data memory 1 has a main data memory 2, a redundancy data memory 3, a redundancy control logic 4 and a data readout multiplexer 5.
  • the main data memory 2 is preferably a RAM memory, in particular an SRAM memory.
  • the data memory 1 is connected to a data bus 6, an address bus 7 and a control bus 8.
  • the main data memory 2 is connected via data lines 9 to the data bus 6, via address lines 10 to the address bus 7 and via control lines 11 to the control bus 8.
  • the redundancy data memory 3 is connected to the data bus 6 via data lines 12, to the address bus 7 via address lines 13 and to the control bus 8 via control lines 14.
  • the redundancy control logic 4 is connected to the address bus 7 via address lines 15 and to the control bus 8 via control lines 16.
  • the main data memory 2 is connected via data read-out lines 17 to a first input of the data read-out multiplexer 5 and the redundancy data memory 3 is connected via data read-out lines 18 to a second input of the data read-out multiplexer 5.
  • the data read-out multiplexer 5 can be connected on the output side via data lines 19 to the data bus 6 or to another data bus.
  • the redundancy control logic 4 controls the writing of data into the redundancy data memory 3 via a control line 20 and the switching of the data read-out multiplexer 5 between the data read-out lines 17, 18 via a control line 21.
  • the main data storage 2 consists of a multiplicity of data storage units. With the data storage units, it can are individual data bits, data words, data columns, data series, data fields or data macro areas. The data storage units can be addressed by their own individual address.
  • the redundant data storage 3 has a plurality of redundancy data storage units for replacing faulty data storage units within the main data storage 2.
  • the number of redundancy data storage units is considerably less than the number of data storage units within the main data store 2. If defective data storage units are produced within the main data store 2 in the manufacturing process of the data store 1, the redundancy data storage units within the redundancy data store take over 3 whose memory functions.
  • the redundant control logic 4 controls access to the redundancy data store 3 when access to a faulty data storage unit of the main data store 2 is determined.
  • the main data memory 2 and the redundancy data memory 3 are connected to the data bus 6 in parallel with one another via the data write lines 10, 12. On the output side, the main data store 2 and the redundancy data store 3 are likewise connected in parallel to the data bus 6 via the data readout multiplexer 5 and the data readout lines 19.
  • the main data store 2 and the redundancy control logic 4 are connected in parallel to one another via the address lines 10, 15 to the address bus 7 for addressing data storage units in the data store 1.
  • the redundancy data memory 3 and the redundancy control logic 4 are in one Integrated component, whereby the electrical connection to an existing main data memory 2 is facilitated.
  • the redundancy control logic 4 contains an address memory 22 with a plurality of address memory units 22a to 22g, in which the addresses of faulty data memory units within the main data memory 2 can be stored.
  • the address storage units 22a to 22g are address storage registers. Each address storage register 22a to 22g preferably has a flag bit which indicates whether the content of the address storage register is valid.
  • the redundancy control logic 4 also contains an address comparison circuit 23 with a plurality of address comparators 23a to 23g, each of which is connected to an address memory register 22a to 22g via internal address lines 24a to 24g and to the address bus 7 via address lines 15.
  • the comparators 23a to 23g each have address bit comparison circuits for comparing the address bit levels present on the address lines 15 and the internal address lines 24. After the memory test has been carried out, the addresses of faulty data storage units within the main data memory 2 are written into the address registers 22a to 22g.
  • redundancy data storage unit 26a to 26g of the redundancy data memory 3 is activated via control lines 25a to 25g and the corresponding redundancy data storage unit 26a to 26g via an internal ternal data readout multiplexer 27 of the redundancy data memory 3 connected to the data readout multiplexer 5.
  • the redundancy data storage units 26a to 26g of the redundancy data store 3 are connected to the internal multiplexers 27 of the redundancy data store 3 via internal data lines 28a to 28g.
  • the address applied to the address lines 15 corresponds to the address stored in the address memory register 22a
  • this is recognized by the comparator 23a of the address comparison circuit 23 and the redundancy data storage unit 26a of the redundancy data memory 3 is sent via the control line 25a activated.
  • the address comparison circuit 23 switches the multiplexer 27 via the control line 22 such that the internal line 28a is switched through to the output line 18 of the multiplexer 27.
  • the address comparison circuit 23 controls the multiplexer 5 in such a way that it connects the data line 18 to the data line 19, so that the data contained in the redundancy data storage unit 26a are output to the data bus 6 via the data lines 19.
  • the multiplexer 5 is switched in such a way that the data lines 17 are directly connected to the data lines 19.
  • the data access to a data storage unit within the main data storage 2 takes place very quickly, since the address comparison within the redundancy control logic 4 takes place in parallel in time.
  • the redundancy data store 3 has a much shorter access time than the main data store 2.
  • the redundancy data store 3 has only a few redundancy data stores registers 26a to 26g for replacing faulty data stores units within the main data memory 2.
  • the time T required by the address comparison circuit 23 for the address comparison is also relatively short, so that the sum of the address comparison time T v and the memory access time to the redundancy data memory 3 T ZR is less than the access Grip time T ZH on the main data memory 2.
  • the memory access time to the data memory 1 according to the invention thus results when the non-faulty data storage unit of the main data memory 2 is accessed:
  • T MUX is the switching time of the multiplexer 5.
  • the switching time of the multiplexer 5 M U X is very low. It is far lower than the address comparison time of the address comparison circuit 23.
  • the memory access time T z is much higher in the conventional arrangement than in the data memory 1 according to the invention.
  • the memory access time T z is :
  • T is the address comparison time that the redundancy logic needs to determine whether a faulty address is present on the address bus A and
  • T ZH represents the memory access time to the main data memory.
  • the maximum memory access time T z of the data memory 1 according to the invention is:
  • T z T perennialu ⁇ + T ZH if T v + T m ⁇ T m
  • T MU ⁇ is the switching time of the multiplexer 5 and T ZH represents the memory access time to the main data memory 2.
  • This time advantage is achieved by the fact that during the memory access time T ZH on data storage units within the main data memory 2, the address comparison within the redundancy control logic 4 is already taking place in parallel and after the memory access to the main data memory 2 has ended, only as a function of the same result between the redundancy data memory 3 and the main data memory 2 is switched by the multiplexer 5.
  • the main data store 2, the redundancy data store 3 and the redundancy control logic 4 are parallel to one another via control lines 11, 14, 16 on the control bus 8 for controlling a read or write access to the data store 1 connected.
  • the writing process into the redundancy data memory 3 takes place in two steps. With a rising clock edge, the input addresses and the input data are stored in a buffer.
  • the comparators 23a to 23g compare the input address with the contents of the address storage registers 22a to 22g. If one of the stored addresses corresponds to the input address, the temporarily stored input data are written to the corresponding data storage register 26a to 26g on the next clock edge.
  • the address memory 22 is connected via address read lines 29a to 29g to an address read-only memory 30 for the permanent storage of addresses of faulty data storage units of the main data memory 2.
  • the addresses incorrectly recognized after testing data memory 1 are permanently programmed in address read-only memory 30.
  • the address read-only memory 30 is preferably a non-volatile memory.
  • the address read-only memory 30 preferably consists of fuses which are burned according to the incorrectly identified addresses after the test process.
  • the address memory 22 preferably contains a plurality of address memory registers 22a to 22g, each of which has a flag bit which indicates whether the content of the address register 22a to 22g is valid. If it is recognized after the test that the main data store 2 contains no faulty data storage units, the redundancy control logic 4 is deactivated by all flag bits remaining reset.
  • FIG. 4 shows an alternative embodiment of the redundancy control logic 4, in which the address memory units 22a to 22g of the address memory 22 are associative memory units connected to the address bus 7 for enabling the associated redundancy data storage units 26a to 26g of the redundancy data memory 3 ,
  • FIG. 5 shows a flow chart to illustrate the programming process of the data memory according to the invention with addresses of faulty data storage units.
  • step S 0 A memory test is started in a step S 0 .
  • step Si is initialized for fields and address memory registers.
  • step S 2 an address is applied to the address bus 7 and a test date to the data bus 6.
  • step S 3 it is evaluated whether the output data value present on the data bus 6 corresponds to an expected data output value. If this is the case, a decision is made in step S 4 as to whether the test has ended. If the test run of the main data memory 2 has not yet ended, the next address is generated in step S5 and applied to the address bus 7 again in step S 2 .
  • the one consisting of steps S 2 , S 3 , S 4 , S 5 Loop is run for all addresses of the main data store 2.
  • step S 6 it is checked whether there are still free address memory registers or associative memories 22a to 22g within the redundancy control logic 4. If the address memory 22 of the redundancy control logic 4 is already filled with addresses of faulty data storage units and thus no further address storage units are available within the redundancy control logic 4, the data memory 1 which has been incorrectly manufactured in this way can no longer be repaired because too many manufacturing defects have occurred and the sequence shown in FIG. 5 emits a display signal in step S 7 , which indicates that the data memory 1 cannot be repaired.
  • step S 8 If it is determined in step S ⁇ that a free address storage unit 22a to 22g is still present within the redundancy control logic 4, in step S 8 the address recognized as faulty is written into the address storage unit of the address memory 22 and, if appropriate, an existing flag bit set.
  • step S 8 the test data to be created are reset and the test started again.
  • the addresses of the data storage units within the main data storage 2 which are recognized as being defective are sent to address storage units 22a to 22g of the address storage chers 22 inscribed within the redundancy control logic 4.
  • the addresses identified as defective can come from an integrated memory test logic BIST integrated in the data memory 1, a test machine TA or from the address read-only memory 30. Due to the parallel arrangement of the redundancy data memory 3 and the main data memory 2 in relation to the data bus 6 and by the parallel arrangement of the redundancy control logic 4 and the main data memory 2 in relation to the address bus 7, the memory access time from the data memory 1 significantly shortened.
  • the redundancy control logic 4 and the redundancy data memory 3 can be constructed in an integrated manner as an electronic component.
  • an existing main data memory 2 can be provided with a redundant memory space in a simple manner by switching with such a component integrated via a multiplexer 5.
  • the multiplexer 5 with the redundancy control logic 4 and the redundancy data memory 3 and the address read-only memory 30 is integrated in an electronic circuit.
  • a component integrated in this way only has to be connected to the data bus 6, the address bus 7, the control bus 8 and via line 17 to the main data store 2 in order to expand an existing main data store 2.

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

L'invention concerne une mémoire de données composée d'une mémoire de données principale (2) comportant une pluralité d'unités de mémoire de données, d'une mémoire de données de redondance (3) comportant plusieurs unités de mémoires de données de redondance pour le remplacement d'unités de données défectueuses de la mémoire de données principale (2), et d'une logique de commande de redondance (4) destinée à commander l'accès à la mémoire de données de redondance (3). La mémoire de données principale (2) et la mémoire de données de redondance (3) sont reliées parallèlement l'une à l'autre à un bus de données (6) au moyen de lignes de données (9, 12), et la mémoire de données principale (2) et la commande de logique de redondance (4) sont reliées parallèlement l'une à l'autre à un bus d'adresse (7) au moyen de lignes d'adresses (10, 15) pour l'adressage d'unités de mémoire de données dans la mémoire de données (1).
EP01900126A 2000-01-19 2001-01-05 Memoire de donnees Withdrawn EP1248978A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10002139 2000-01-19
DE10002139A DE10002139A1 (de) 2000-01-19 2000-01-19 Datenspeicher
PCT/EP2001/000075 WO2001053944A2 (fr) 2000-01-19 2001-01-05 Memoire de donnees

Publications (1)

Publication Number Publication Date
EP1248978A2 true EP1248978A2 (fr) 2002-10-16

Family

ID=7628020

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01900126A Withdrawn EP1248978A2 (fr) 2000-01-19 2001-01-05 Memoire de donnees

Country Status (5)

Country Link
US (1) US6785170B2 (fr)
EP (1) EP1248978A2 (fr)
DE (1) DE10002139A1 (fr)
TW (1) TW487921B (fr)
WO (1) WO2001053944A2 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10338022A1 (de) 2003-08-19 2005-03-31 Infineon Technologies Ag Verfahren zum Adressieren eines regulären und eines redundanten Speicherbereiches in einer Speicherschaltung sowie eine Adressdecodierschaltung hierfür
EP1536431A1 (fr) 2003-11-26 2005-06-01 Infineon Technologies AG Architecture de mémoire pour stocker des données
JP2006012234A (ja) * 2004-06-23 2006-01-12 Toshiba Corp メモリテスト回路およびメモリテスト方法
US7519875B2 (en) * 2004-08-20 2009-04-14 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and apparatus for enabling a user to determine whether a defective location in a memory device has been remapped to a redundant memory portion
JP2006107590A (ja) * 2004-10-04 2006-04-20 Nec Electronics Corp 半導体集積回路装置及びそのテスト方法
US7672150B2 (en) * 2007-09-27 2010-03-02 Infineon Technologies Ag Apparatus, embedded memory, address decoder, method of reading out data and method of configuring a memory

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5262994A (en) 1992-01-31 1993-11-16 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with a multiplexer for selecting an output for a redundant memory access
EP0637034B1 (fr) 1993-07-26 1999-01-13 STMicroelectronics S.r.l. Procédé de détection d'éléments défectueux d'une mémoire redondante à semi-conducteur
FR2716743B1 (fr) * 1994-02-28 1996-09-27 Sgs Thomson Microelectronics Circuit de redondance de mémoire.
EP0675440B1 (fr) * 1994-03-29 1998-08-05 STMicroelectronics S.r.l. Circuit de redondance pour un dispositif de mémoire à semi-conducteur
US5438546A (en) 1994-06-02 1995-08-01 Intel Corporation Programmable redundancy scheme suitable for single-bit state and multibit state nonvolatile memories
JPH1074396A (ja) * 1996-08-30 1998-03-17 Nec Corp 半導体記憶装置
US5793683A (en) * 1997-01-17 1998-08-11 International Business Machines Corporation Wordline and bitline redundancy with no performance penalty
US5841710A (en) * 1997-02-14 1998-11-24 Micron Electronics, Inc. Dynamic address remapping decoder
JPH10334689A (ja) 1997-05-30 1998-12-18 Fujitsu Ltd 半導体記憶装置
JP3225938B2 (ja) * 1998-12-17 2001-11-05 日本電気株式会社 半導体装置およびその故障救済方法
JP2003022693A (ja) * 2001-07-09 2003-01-24 Mitsubishi Electric Corp 半導体メモリ

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0153944A2 *

Also Published As

Publication number Publication date
WO2001053944A3 (fr) 2002-02-14
US20030076716A1 (en) 2003-04-24
US6785170B2 (en) 2004-08-31
TW487921B (en) 2002-05-21
WO2001053944A2 (fr) 2001-07-26
DE10002139A1 (de) 2001-08-02

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