Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
  • G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
  • G06F12/023—Free address space management
  • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
  • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
  • G06F2212/10—Providing a specific technical effect
  • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
  • G06F2212/1036—Life time enhancement
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
  • G06F2212/72—Details relating to flash memory management
  • G06F2212/7211—Wear leveling

Definitions

• the invention relates to a storage system comprising at least one memory and means for managing said memory with anti-wear so as to increase the lifetime of said memory.
• the invention also relates to a method of anti-wear management of such a memory.
• the invention applies to any non-volatile memory or whose content is saved, likely to have frequent updates of certain data.
• the invention is particularly applicable to storage media such as smart cards.
• FeRAM know that whatever the technology of non-volatile memories, there is a maximum number N of write-reads possible for each cell constituting a memory.
• An object of the present invention is to solve this problem.
• Another object of the invention is to provide a solution to the wear and tear of memories, including in cases where it is not known a priori which memory cells will be stressed. This will be more and more the case with the possibility which is offered to load in the cards of the interpretable programs (the program consists of data in interpretable language). Loads of interpretable programs may be downloads made by the users themselves. Said programs can be developed without taking into account the distribution of the wear of the memory cells. This will be directly taken into account by means for managing the memory of the card according to the invention.
• Another object of the invention is to provide a solution to spying on sensitive data, since as we will see in detail, this data will be moved into memory.
• the first object of the invention is a storage system comprising at least one non-volatile memory containing information capable of being updated, mainly characterized in that it includes means for managing this memory capable of moving over all or part of the memory respectively all or part of the content of said memory.
• all the contents of the memory will be moved with the exception of the data which would be in this memory and for which it is imperative to maintain the physical address. This is for example the case of management data (and / or instructions) of the mechanism implemented by the management means according to the invention. If this data is stored in this memory, then the memory part containing all this data (and / or instructions) will not be moved.
• the memory management means are capable of performing iterative displacements.
• the iterative movements are cyclical.
• the means for moving include: means of transfer from a first region to a second region,
• - Address conversion means so that all requests for access to the first region are converted into requests for access to the second region into which the content of the first region has been transferred.
• the means for moving operate by progressive shifting of the content from a first region to a second region.
• the memory is organized into regions comprising one or more cells, at least one of the regions is empty and the management means operate progressive shifts of the content from a first region to a second region said second region being the region empty or emptied during a previous shift.
• the means for moving the contents of a first region by progressive shift to a second empty or emptied region further comprise means for controlling the shift.
• the offset control means are produced by a clock signal.
• the offset control means are produced by a random control signal.
• the offset control means include counting means for comparing the number of accesses to the memory with respect to a predetermined threshold.
• the transfer means include a program for reading the entire first region concerned and writing in the second region concerned.
• the address conversion means comprise a logic unit produced by a program.
• the address conversion means comprise a physical unit produced by a logic circuit in the memory addressing circuit.
• the storage system consists of a smart card.
• Another object of the invention is a method for managing a non-volatile memory containing information capable of being updated, mainly characterized in that it comprises a step of moving over all or part of the memory respectively all or part of the content of said memory.
• the memory is organized into regions, and the displacement step comprises steps for transferring the content of the regions.
• the method comprises the step of: - providing at least one free region in said memory, the information intended to be recorded in said memory being recorded in regions of memory other than this empty region.
• the displacement step is carried out by progressive shifting of the content from a first region to a second region, said second region being the region empty or emptied during a previous shift.
• the progressive shift includes a step of: locating the new free region.
• the moving step further includes a step of converting addresses so that all requests for access to the first region are converted into requests for access to the second region, in which the content of the first region has been transfered.
• the progressive shift step includes a shift control step.
• the offset control can be performed by a clock signal.
• the shift can be controlled by a random signal.
• the shift control step comprises counting the number of accesses to said memory and a comparison of this number of accesses to a predetermined threshold (S) for said number.
• the transfer step is carried out by means of a program for reading the entire first region concerned and writing in the second region concerned.
• FIG. 1 represents the diagram of a storage system according to a first embodiment
• FIG. 2 represents the diagram of a storage system according to a second embodiment
• FIG. 3 schematically represents a memory plane illustrating the mechanism implemented by the management means according to the invention
• the smart card 1 comprises only a memory MA for data (and / or interpretable programs), some of which are liable to be updated.
• the management means 2 of said memory MA are deported in this case to the smart card reader.
• the smart card includes both the memory management means 2 and the memory MA itself.
• the invention therefore applies to any storage system comprising management means, that these memory management means are on the same support as the memory itself, wherever they are deported for example in a reader. smart cards.
• FIG. 1 represents more particularly management means formed by a processing unit UT which will for example be a microprocessor, a program memory MP (ROM or PROM) associated with this microprocessor MP.
• This program memory MP generally comprises an application program AP.
• the program memory will also include a program P making it possible to implement the management mechanism which will be described below.
• the management means 2 of the memory MA of application data therefore consist of the processing unit UT and at least one program memory MP, which contains the program P capable of implementing the mechanism for managing this MA memory.
• this program P contains a subroutine T for data transfer, a program for counting CPC of the number Nj ⁇ of access to the memory MA and of comparing said number of accesses J ⁇ JJ to a predetermined threshold S .
• This program P can also contain a conversion program CA1 which will make it possible to make physical address conversions for a logical address requested by the application program AP.
• the memory is organized into regions called pages, each page having a size of several bytes.
• the diagram in FIG. 3 illustrates two memory planes, a first plan taken at time To, time for which the number of memory accesses N ⁇ JJ is zero for example and, a second plan at time Tl, time for which this number of accesses N ⁇ has reached the predetermined threshold S.
• the mechanism therefore made it possible to shift the content of region A into the empty region Po.
• the new region Po is in the old location of region A.
• the mechanism has therefore made it possible to operate a data transfer from region A into the empty region Po.
• This mechanism also makes it possible vis-à-vis the application program AP making requests for access DA (reads or writes ) to logical addresses for data located in region A, to convert the physical address (corresponding to the requested logical address), to the physical address which is the one corresponding to the new location of said data in region A.
• the order to carry out a transfer from a region A to the empty or emptied region Po is passed through the management means, that is to say by the program P when the subroutine counting the number of access N ⁇ JJ has reached the predetermined threshold S.
• FIG. 4 illustrates the mechanism according to the invention when one has operated at all the offsets necessary to obtain an offset of all the regions of the memory. If the number of regions is n the number of shifts operated by the memory management means will be equal to this number n, so that the entire content of the memory has been transferred from one region to another region by using the start region then the region that was emptied at each shift.
• the management mechanism will carry out 100x100 shifts to find the starting point which corresponds to the original physical address Arjo on page P 0 .
• FIG. 5 illustrates a means for locating the location of the empty region Po.
• a zone Zo is provided which can be located in a fixed zone of this memory MA reserved for this purpose or in an electrically programmable memory zone of the management system.
• This zone has a length at least equal to n bits, n corresponding to the number of offsets to operate a complete shift cycle (shift of all regions).
• the mechanism according to the invention makes it possible to set a bit to 1 each time the empty region Po is moved.
• This region Zo thus makes it possible to locate the physical location of the empty region.
• Another counter will count the number of complete cycles of shifts.
• This counter CP can be produced by the program P for example.
• This mechanism makes it possible that the data of the regions of memory which are most often modified (or read) are not always located in the same regions, but that they are moved from one region to another and this, for all regions without these regions needing to be identified.
• the data of a region are for example at the beginning of the memory and gradually will slide towards the end and start coming again at the beginning.
• the application program makes its read-write accesses without realizing that the physical location of the data to which it wishes to access has been changed.
• the program will for example access 1,000,000 times to information, but this information will have been successively moved to 100 cells for example, each cell will therefore have been stressed 10,000 times.
• the invention therefore allows such a program not to always stress, for a datum to be updated, the same cells or the same regions. Said program will stress for this data another set of memory cells, then yet another set of cells, etc. The wear and tear caused by updates to this data will therefore be distributed over several sets of cells or regions.
• the management means which are used to obtain this distribution of stress make it possible to have complete transparency with respect to the application program.
• Application program places access orders
• the management means receive these commands and conventionally carry out the correspondence between the physical address and the requested logical address, as long as the data has not been transferred to a other physical address.
• the management means carry out a physical address conversion for said data each time there has been an offset, that is to say the transfer the content of the region in which this data is found in another region.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Techniques For Improving Reliability Of Storages (AREA)
• Storage Device Security (AREA)
• Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
• Memory System (AREA)

Applications Claiming Priority (3)

Publications (2)

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• 1998
  • 1998-12-22 FR FR9816216A patent/FR2787601A1/fr active Pending
• 1999
  • 1999-12-21 JP JP2000590059A patent/JP3926985B2/ja not_active Expired - Lifetime
  • 1999-12-21 AT AT99961124T patent/ATE436052T1/de not_active IP Right Cessation
  • 1999-12-21 EP EP99961124A patent/EP1151384B1/de not_active Expired - Lifetime
  • 1999-12-21 CN CNB998163201A patent/CN100367236C/zh not_active Expired - Lifetime
  • 1999-12-21 WO PCT/FR1999/003222 patent/WO2000038067A1/fr active Application Filing
  • 1999-12-21 AU AU17844/00A patent/AU1784400A/en not_active Abandoned
  • 1999-12-21 DE DE69941095T patent/DE69941095D1/de not_active Expired - Lifetime
  • 1999-12-22 US US09/468,879 patent/US6539453B1/en not_active Expired - Lifetime
• 2006
  • 2006-09-13 JP JP2006247979A patent/JP4604144B2/ja not_active Expired - Lifetime

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